reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AArch64/AArch64GenInstrInfo.inc

 6849   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
 7278   { 431,	1,	0,	4,	862,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr },  // Inst #431 = BR

gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc

16064   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
18125   { 2063,	1,	0,	4,	6,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x5ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr },  // Inst #2063 = S_SETPC_B64

gen/lib/Target/AMDGPU/R600GenInstrInfo.inc

  640   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR

gen/lib/Target/ARC/ARCGenInstrInfo.inc

  645   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
  947   { 304,	1,	0,	4,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #304 = J
  948   { 305,	1,	0,	4,	0,	0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList1, ImplicitList3, OperandInfo52, -1 ,nullptr },  // Inst #305 = JL

gen/lib/Target/ARM/ARMGenInstrInfo.inc

 5835   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
 6022   { 189,	3,	0,	4,	859,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #189 = BR_JTadd
 6023   { 190,	3,	0,	4,	862,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr },  // Inst #190 = BR_JTm_i12
 6024   { 191,	4,	0,	4,	862,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr },  // Inst #191 = BR_JTm_rs
 6025   { 192,	2,	0,	4,	860,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr },  // Inst #192 = BR_JTr
 6065   { 232,	1,	0,	4,	880,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #232 = MOVPCRX
 6353   { 520,	3,	0,	4,	860,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #520 = t2BR_JT
 6392   { 559,	4,	0,	4,	860,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #559 = t2TBB_JT
 6393   { 560,	4,	0,	4,	860,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr },  // Inst #560 = t2TBH_JT
 6403   { 570,	3,	0,	2,	860,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #570 = tBRIND
 6428   { 595,	4,	0,	2,	5,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #595 = tTBB_JT
 6429   { 596,	4,	0,	2,	5,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #596 = tTBH_JT
 6460   { 627,	1,	0,	4,	851,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x180ULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr },  // Inst #627 = BX
 6463   { 630,	3,	0,	4,	851,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x180ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #630 = BX_pred
 9596   { 3763,	3,	0,	4,	861,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo177, -1 ,nullptr },  // Inst #3763 = t2BXJ
 9910   { 4077,	4,	0,	4,	859,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo495, -1 ,nullptr },  // Inst #4077 = t2TBB
 9911   { 4078,	4,	0,	4,	859,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::NotDuplicable)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo495, -1 ,nullptr },  // Inst #4078 = t2TBH
 9978   { 4145,	3,	0,	2,	851,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #4145 = tBX
 9979   { 4146,	3,	0,	2,	851,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo114, -1 ,nullptr },  // Inst #4146 = tBXNS

gen/lib/Target/AVR/AVRGenInstrInfo.inc

  485   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
  761   { 278,	0,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList4, nullptr, nullptr, -1 ,nullptr },  // Inst #278 = EIJMP
  770   { 287,	0,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList4, nullptr, nullptr, -1 ,nullptr },  // Inst #287 = IJMP

gen/lib/Target/BPF/BPFGenInstrInfo.inc

  422   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR

gen/lib/Target/Hexagon/HexagonGenInstrInfo.inc

 3632   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
 3949   { 319,	1,	0,	4,	38,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x1000000024ULL, nullptr, ImplicitList19, OperandInfo71, -1 ,nullptr },  // Inst #319 = PS_tailcall_r
 4707   { 1077,	1,	0,	4,	38,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000000024ULL, ImplicitList22, ImplicitList19, OperandInfo71, -1 ,nullptr },  // Inst #1077 = EH_RETURN_JMPR
 4781   { 1151,	1,	0,	4,	38,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x1000000024ULL, nullptr, ImplicitList19, OperandInfo71, -1 ,nullptr },  // Inst #1151 = J2_jumpr
 4782   { 1152,	2,	0,	4,	16,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr },  // Inst #1152 = J2_jumprf
 4783   { 1153,	2,	0,	4,	108,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000001c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr },  // Inst #1153 = J2_jumprfnew
 4784   { 1154,	2,	0,	4,	108,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x2001000001c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr },  // Inst #1154 = J2_jumprfnewpt
 4785   { 1155,	2,	0,	4,	109,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x2001000000c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr },  // Inst #1155 = J2_jumprfpt
 4792   { 1162,	2,	0,	4,	16,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr },  // Inst #1162 = J2_jumprt
 4793   { 1163,	2,	0,	4,	108,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000001424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr },  // Inst #1163 = J2_jumprtnew
 4794   { 1164,	2,	0,	4,	108,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x2001000001424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr },  // Inst #1164 = J2_jumprtnewpt
 4795   { 1165,	2,	0,	4,	109,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x2001000000424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr },  // Inst #1165 = J2_jumprtpt
 4923   { 1293,	1,	0,	4,	38,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000024ULL, nullptr, nullptr, OperandInfo71, -1 ,nullptr },  // Inst #1293 = J4_hintjumpr
 5166   { 1536,	2,	1,	4,	28,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x2809000000025ULL, ImplicitList34, ImplicitList36, OperandInfo51, -1 ,nullptr },  // Inst #1536 = L4_return
 5167   { 1537,	3,	1,	4,	23,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x2809000000c25ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr },  // Inst #1537 = L4_return_f
 5168   { 1538,	3,	1,	4,	24,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x809000001c25ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr },  // Inst #1538 = L4_return_fnew_pnt
 5169   { 1539,	3,	1,	4,	24,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x2809000001c25ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr },  // Inst #1539 = L4_return_fnew_pt
 5170   { 1540,	3,	1,	4,	23,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x2809000000425ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr },  // Inst #1540 = L4_return_t
 5171   { 1541,	3,	1,	4,	24,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x809000001425ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr },  // Inst #1541 = L4_return_tnew_pnt
 5172   { 1542,	3,	1,	4,	24,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x2809000001425ULL, ImplicitList34, ImplicitList36, OperandInfo52, -1 ,nullptr },  // Inst #1542 = L4_return_tnew_pt
 5500   { 1870,	1,	0,	4,	38,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Terminator), 0x1000000024ULL, nullptr, ImplicitList19, OperandInfo71, -1 ,nullptr },  // Inst #1870 = PS_jmpret
 5501   { 1871,	2,	0,	4,	16,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000000c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr },  // Inst #1871 = PS_jmpretf
 5502   { 1872,	2,	0,	4,	108,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000001c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr },  // Inst #1872 = PS_jmpretfnew
 5503   { 1873,	2,	0,	4,	108,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x2001000001c24ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr },  // Inst #1873 = PS_jmpretfnewpt
 5504   { 1874,	2,	0,	4,	16,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000000424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr },  // Inst #1874 = PS_jmprett
 5505   { 1875,	2,	0,	4,	108,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x1000001424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr },  // Inst #1875 = PS_jmprettnew
 5506   { 1876,	2,	0,	4,	108,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x2001000001424ULL, nullptr, ImplicitList19, OperandInfo49, -1 ,nullptr },  // Inst #1876 = PS_jmprettnewpt
 6014   { 2384,	0,	0,	4,	178,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x100000002bULL, ImplicitList46, ImplicitList19, nullptr, -1 ,nullptr },  // Inst #2384 = SL2_jumpr31
 6015   { 2385,	0,	0,	4,	178,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000000c2bULL, ImplicitList47, ImplicitList19, nullptr, -1 ,nullptr },  // Inst #2385 = SL2_jumpr31_f
 6016   { 2386,	0,	0,	4,	178,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x1000001c2bULL, ImplicitList47, ImplicitList19, nullptr, -1 ,nullptr },  // Inst #2386 = SL2_jumpr31_fnew
 6017   { 2387,	0,	0,	4,	178,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x100000042bULL, ImplicitList47, ImplicitList19, nullptr, -1 ,nullptr },  // Inst #2387 = SL2_jumpr31_t
 6018   { 2388,	0,	0,	4,	178,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x100000142bULL, ImplicitList47, ImplicitList19, nullptr, -1 ,nullptr },  // Inst #2388 = SL2_jumpr31_tnew
 6024   { 2394,	0,	0,	4,	179,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x80900000002bULL, ImplicitList44, ImplicitList48, nullptr, -1 ,nullptr },  // Inst #2394 = SL2_return
 6025   { 2395,	0,	0,	4,	179,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x809000000c2bULL, ImplicitList49, ImplicitList48, nullptr, -1 ,nullptr },  // Inst #2395 = SL2_return_f
 6026   { 2396,	0,	0,	4,	179,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x809000001c2bULL, ImplicitList49, ImplicitList48, nullptr, -1 ,nullptr },  // Inst #2396 = SL2_return_fnew
 6027   { 2397,	0,	0,	4,	179,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x80900000042bULL, ImplicitList49, ImplicitList48, nullptr, -1 ,nullptr },  // Inst #2397 = SL2_return_t
 6028   { 2398,	0,	0,	4,	179,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x80900000142bULL, ImplicitList49, ImplicitList48, nullptr, -1 ,nullptr },  // Inst #2398 = SL2_return_tnew

gen/lib/Target/Lanai/LanaiGenInstrInfo.inc

  372   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
  568   { 198,	2,	0,	4,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo40, -1 ,nullptr },  // Inst #198 = BRIND_CC
  569   { 199,	3,	0,	4,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList3, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #199 = BRIND_CCA
  572   { 202,	1,	0,	4,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo37, -1 ,nullptr },  // Inst #202 = JR

gen/lib/Target/MSP430/MSP430GenInstrInfo.inc

  643   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
  962   { 321,	1,	0,	4,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #321 = Bi
  963   { 322,	2,	0,	4,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #322 = Bm
  964   { 323,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo66, -1 ,nullptr },  // Inst #323 = Br

gen/lib/Target/Mips/MipsGenInstrInfo.inc

 4817   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
 5255   { 440,	1,	0,	4,	382,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #440 = PseudoIndirectBranch
 5256   { 441,	1,	0,	4,	1012,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #441 = PseudoIndirectBranch64
 5257   { 442,	1,	0,	4,	1016,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #442 = PseudoIndirectBranch64R6
 5258   { 443,	1,	0,	4,	928,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #443 = PseudoIndirectBranchR6
 5259   { 444,	1,	0,	4,	957,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #444 = PseudoIndirectBranch_MM
 5260   { 445,	1,	0,	4,	990,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #445 = PseudoIndirectBranch_MMR6
 5261   { 446,	1,	0,	4,	382,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #446 = PseudoIndirectHazardBranch
 5262   { 447,	1,	0,	4,	1012,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #447 = PseudoIndirectHazardBranch64
 5263   { 448,	1,	0,	4,	1016,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #448 = PseudoIndrectHazardBranch64R6
 5264   { 449,	1,	0,	4,	928,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x10ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #449 = PseudoIndrectHazardBranchR6
 6465   { 1650,	2,	1,	4,	994,	0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x3ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #1650 = JALRC_HB_MMR6
 6469   { 1654,	2,	1,	4,	403,	0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #1654 = JALR_HB
 6470   { 1655,	2,	1,	4,	1005,	0|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo111, -1 ,nullptr },  // Inst #1655 = JALR_HB64
 6476   { 1661,	2,	0,	4,	920,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo103, -1 ,nullptr },  // Inst #1661 = JIALC
 6477   { 1662,	2,	0,	4,	1013,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Call)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList3, OperandInfo101, -1 ,nullptr },  // Inst #1662 = JIALC64
 6479   { 1664,	2,	0,	4,	925,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo103, -1 ,nullptr },  // Inst #1664 = JIC
 6480   { 1665,	2,	0,	4,	1011,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, ImplicitList2, OperandInfo101, -1 ,nullptr },  // Inst #1665 = JIC64
 6482   { 1667,	1,	0,	4,	915,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #1667 = JR
 6483   { 1668,	1,	0,	2,	946,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #1668 = JR16_MM
 6484   { 1669,	1,	0,	4,	1003,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1669 = JR64
 6485   { 1670,	1,	0,	2,	985,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #1670 = JRADDIUSP
 6486   { 1671,	1,	0,	2,	986,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #1671 = JRC16_MM
 6487   { 1672,	1,	0,	2,	987,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #1672 = JRC16_MMR6
 6488   { 1673,	1,	0,	2,	985,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo2, -1 ,nullptr },  // Inst #1673 = JRCADDIUSP_MMR6
 6489   { 1674,	1,	0,	4,	381,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #1674 = JR_HB
 6490   { 1675,	1,	0,	4,	1006,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x13ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1675 = JR_HB64
 6491   { 1676,	1,	0,	4,	1014,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo86, -1 ,nullptr },  // Inst #1676 = JR_HB64_R6
 6492   { 1677,	1,	0,	4,	926,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x16ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #1677 = JR_HB_R6
 6493   { 1678,	1,	0,	4,	946,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x11ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr },  // Inst #1678 = JR_MM
 6497   { 1682,	0,	0,	2,	931,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1682 = JrRa16
 6498   { 1683,	0,	0,	2,	931,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #1683 = JrcRa16
 6499   { 1684,	1,	0,	2,	931,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr },  // Inst #1684 = JrcRx16

gen/lib/Target/NVPTX/NVPTXGenInstrInfo.inc

 6633   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR

gen/lib/Target/PowerPC/PPCGenInstrInfo.inc

 2910   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
 3280   { 372,	2,	0,	4,	287,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #372 = BCCCTR
 3281   { 373,	2,	0,	4,	287,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, nullptr, OperandInfo69, -1 ,nullptr },  // Inst #373 = BCCCTR8
 3288   { 380,	1,	0,	4,	287,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #380 = BCCTR
 3289   { 381,	1,	0,	4,	287,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #381 = BCCTR8
 3290   { 382,	1,	0,	4,	287,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #382 = BCCTR8n
 3295   { 387,	1,	0,	4,	287,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, nullptr, OperandInfo70, -1 ,nullptr },  // Inst #387 = BCCTRn
 3316   { 408,	0,	0,	4,	287,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList9, nullptr, nullptr, -1 ,nullptr },  // Inst #408 = BCTR
 3317   { 409,	0,	0,	4,	287,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList10, nullptr, nullptr, -1 ,nullptr },  // Inst #409 = BCTR8
 4531   { 1623,	0,	0,	4,	287,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList11, nullptr, nullptr, -1 ,nullptr },  // Inst #1623 = TAILBCTR
 4532   { 1624,	0,	0,	4,	287,	0|(1ULL<<MCID::Return)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x38ULL, ImplicitList13, nullptr, nullptr, -1 ,nullptr },  // Inst #1624 = TAILBCTR8

gen/lib/Target/RISCV/RISCVGenInstrInfo.inc

  664   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
  843   { 181,	2,	0,	4,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Call)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, ImplicitList2, OperandInfo40, -1 ,nullptr },  // Inst #181 = PseudoBRIND
 1003   { 341,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x8ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr },  // Inst #341 = C_JR

gen/lib/Target/Sparc/SparcGenInstrInfo.inc

  932   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
 1147   { 217,	2,	0,	4,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr },  // Inst #217 = BINDri
 1148   { 218,	2,	0,	4,	1,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::DelaySlot)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr },  // Inst #218 = BINDrr

gen/lib/Target/SystemZ/SystemZGenInstrInfo.inc

 4322   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
 4804   { 484,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x8ULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #484 = B
 4811   { 491,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #491 = BAsmE
 4812   { 492,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #492 = BAsmH
 4813   { 493,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #493 = BAsmHE
 4814   { 494,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #494 = BAsmL
 4815   { 495,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #495 = BAsmLE
 4816   { 496,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #496 = BAsmLH
 4817   { 497,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #497 = BAsmM
 4818   { 498,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #498 = BAsmNE
 4819   { 499,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #499 = BAsmNH
 4820   { 500,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #500 = BAsmNHE
 4821   { 501,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #501 = BAsmNL
 4822   { 502,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #502 = BAsmNLE
 4823   { 503,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #503 = BAsmNLH
 4824   { 504,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #504 = BAsmNM
 4825   { 505,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #505 = BAsmNO
 4826   { 506,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #506 = BAsmNP
 4827   { 507,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #507 = BAsmNZ
 4828   { 508,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #508 = BAsmO
 4829   { 509,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #509 = BAsmP
 4830   { 510,	3,	0,	4,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #510 = BAsmZ
 4831   { 511,	5,	0,	4,	4,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x40008ULL, ImplicitList1, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #511 = BC
 4832   { 512,	4,	0,	4,	4,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x8ULL, ImplicitList1, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #512 = BCAsm
 4833   { 513,	3,	0,	2,	4,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x40000ULL, ImplicitList1, nullptr, OperandInfo127, -1 ,nullptr },  // Inst #513 = BCR
 4834   { 514,	2,	0,	2,	4,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo128, -1 ,nullptr },  // Inst #514 = BCRAsm
 4839   { 519,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, nullptr, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #519 = BI
 4840   { 520,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #520 = BIAsmE
 4841   { 521,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #521 = BIAsmH
 4842   { 522,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #522 = BIAsmHE
 4843   { 523,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #523 = BIAsmL
 4844   { 524,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #524 = BIAsmLE
 4845   { 525,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #525 = BIAsmLH
 4846   { 526,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #526 = BIAsmM
 4847   { 527,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #527 = BIAsmNE
 4848   { 528,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #528 = BIAsmNH
 4849   { 529,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #529 = BIAsmNHE
 4850   { 530,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #530 = BIAsmNL
 4851   { 531,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #531 = BIAsmNLE
 4852   { 532,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #532 = BIAsmNLH
 4853   { 533,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #533 = BIAsmNM
 4854   { 534,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #534 = BIAsmNO
 4855   { 535,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #535 = BIAsmNP
 4856   { 536,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #536 = BIAsmNZ
 4857   { 537,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #537 = BIAsmO
 4858   { 538,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #538 = BIAsmP
 4859   { 539,	3,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo122, -1 ,nullptr },  // Inst #539 = BIAsmZ
 4860   { 540,	5,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x4000cULL, ImplicitList1, nullptr, OperandInfo125, -1 ,nullptr },  // Inst #540 = BIC
 4861   { 541,	4,	0,	6,	6,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0xcULL, ImplicitList1, nullptr, OperandInfo126, -1 ,nullptr },  // Inst #541 = BICAsm
 4864   { 544,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #544 = BR
 4867   { 547,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #547 = BRAsmE
 4868   { 548,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #548 = BRAsmH
 4869   { 549,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #549 = BRAsmHE
 4870   { 550,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #550 = BRAsmL
 4871   { 551,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #551 = BRAsmLE
 4872   { 552,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #552 = BRAsmLH
 4873   { 553,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #553 = BRAsmM
 4874   { 554,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #554 = BRAsmNE
 4875   { 555,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #555 = BRAsmNH
 4876   { 556,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #556 = BRAsmNHE
 4877   { 557,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #557 = BRAsmNL
 4878   { 558,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #558 = BRAsmNLE
 4879   { 559,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #559 = BRAsmNLH
 4880   { 560,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #560 = BRAsmNM
 4881   { 561,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #561 = BRAsmNO
 4882   { 562,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #562 = BRAsmNP
 4883   { 563,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #563 = BRAsmNZ
 4884   { 564,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #564 = BRAsmO
 4885   { 565,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #565 = BRAsmP
 4886   { 566,	1,	0,	2,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, ImplicitList1, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #566 = BRAsmZ
 4975   { 655,	5,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #655 = CGIB
 4976   { 656,	5,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #656 = CGIBAsm
 4977   { 657,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #657 = CGIBAsmE
 4978   { 658,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #658 = CGIBAsmH
 4979   { 659,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #659 = CGIBAsmHE
 4980   { 660,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #660 = CGIBAsmL
 4981   { 661,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #661 = CGIBAsmLE
 4982   { 662,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #662 = CGIBAsmLH
 4983   { 663,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #663 = CGIBAsmNE
 4984   { 664,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #664 = CGIBAsmNH
 4985   { 665,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #665 = CGIBAsmNHE
 4986   { 666,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #666 = CGIBAsmNL
 4987   { 667,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #667 = CGIBAsmNLE
 4988   { 668,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #668 = CGIBAsmNLH
 5018   { 698,	5,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #698 = CGRB
 5019   { 699,	5,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #699 = CGRBAsm
 5020   { 700,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #700 = CGRBAsmE
 5021   { 701,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #701 = CGRBAsmH
 5022   { 702,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #702 = CGRBAsmHE
 5023   { 703,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #703 = CGRBAsmL
 5024   { 704,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #704 = CGRBAsmLE
 5025   { 705,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #705 = CGRBAsmLH
 5026   { 706,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #706 = CGRBAsmNE
 5027   { 707,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #707 = CGRBAsmNH
 5028   { 708,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #708 = CGRBAsmNHE
 5029   { 709,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #709 = CGRBAsmNL
 5030   { 710,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #710 = CGRBAsmNLE
 5031   { 711,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #711 = CGRBAsmNLH
 5075   { 755,	5,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr },  // Inst #755 = CIB
 5076   { 756,	5,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr },  // Inst #756 = CIBAsm
 5077   { 757,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #757 = CIBAsmE
 5078   { 758,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #758 = CIBAsmH
 5079   { 759,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #759 = CIBAsmHE
 5080   { 760,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #760 = CIBAsmL
 5081   { 761,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #761 = CIBAsmLE
 5082   { 762,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #762 = CIBAsmLH
 5083   { 763,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #763 = CIBAsmNE
 5084   { 764,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #764 = CIBAsmNH
 5085   { 765,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #765 = CIBAsmNHE
 5086   { 766,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #766 = CIBAsmNL
 5087   { 767,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #767 = CIBAsmNLE
 5088   { 768,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #768 = CIBAsmNLH
 5155   { 835,	5,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #835 = CLGIB
 5156   { 836,	5,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo160, -1 ,nullptr },  // Inst #836 = CLGIBAsm
 5157   { 837,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #837 = CLGIBAsmE
 5158   { 838,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #838 = CLGIBAsmH
 5159   { 839,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #839 = CLGIBAsmHE
 5160   { 840,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #840 = CLGIBAsmL
 5161   { 841,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #841 = CLGIBAsmLE
 5162   { 842,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #842 = CLGIBAsmLH
 5163   { 843,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #843 = CLGIBAsmNE
 5164   { 844,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #844 = CLGIBAsmNH
 5165   { 845,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #845 = CLGIBAsmNHE
 5166   { 846,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #846 = CLGIBAsmNL
 5167   { 847,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #847 = CLGIBAsmNLE
 5168   { 848,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr },  // Inst #848 = CLGIBAsmNLH
 5198   { 878,	5,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #878 = CLGRB
 5199   { 879,	5,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo163, -1 ,nullptr },  // Inst #879 = CLGRBAsm
 5200   { 880,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #880 = CLGRBAsmE
 5201   { 881,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #881 = CLGRBAsmH
 5202   { 882,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #882 = CLGRBAsmHE
 5203   { 883,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #883 = CLGRBAsmL
 5204   { 884,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #884 = CLGRBAsmLE
 5205   { 885,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #885 = CLGRBAsmLH
 5206   { 886,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #886 = CLGRBAsmNE
 5207   { 887,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #887 = CLGRBAsmNH
 5208   { 888,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #888 = CLGRBAsmNHE
 5209   { 889,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #889 = CLGRBAsmNL
 5210   { 890,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #890 = CLGRBAsmNLE
 5211   { 891,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo164, -1 ,nullptr },  // Inst #891 = CLGRBAsmNLH
 5263   { 943,	5,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr },  // Inst #943 = CLIB
 5264   { 944,	5,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr },  // Inst #944 = CLIBAsm
 5265   { 945,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #945 = CLIBAsmE
 5266   { 946,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #946 = CLIBAsmH
 5267   { 947,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #947 = CLIBAsmHE
 5268   { 948,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #948 = CLIBAsmL
 5269   { 949,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #949 = CLIBAsmLE
 5270   { 950,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #950 = CLIBAsmLH
 5271   { 951,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #951 = CLIBAsmNE
 5272   { 952,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #952 = CLIBAsmNH
 5273   { 953,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #953 = CLIBAsmNHE
 5274   { 954,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #954 = CLIBAsmNL
 5275   { 955,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #955 = CLIBAsmNLE
 5276   { 956,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr },  // Inst #956 = CLIBAsmNLH
 5297   { 977,	5,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #977 = CLRB
 5298   { 978,	5,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #978 = CLRBAsm
 5299   { 979,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #979 = CLRBAsmE
 5300   { 980,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #980 = CLRBAsmH
 5301   { 981,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #981 = CLRBAsmHE
 5302   { 982,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #982 = CLRBAsmL
 5303   { 983,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #983 = CLRBAsmLE
 5304   { 984,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #984 = CLRBAsmLH
 5305   { 985,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #985 = CLRBAsmNE
 5306   { 986,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #986 = CLRBAsmNH
 5307   { 987,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #987 = CLRBAsmNHE
 5308   { 988,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #988 = CLRBAsmNL
 5309   { 989,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #989 = CLRBAsmNLE
 5310   { 990,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #990 = CLRBAsmNLH
 5366   { 1046,	5,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1046 = CRB
 5367   { 1047,	5,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1047 = CRBAsm
 5368   { 1048,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1048 = CRBAsmE
 5369   { 1049,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1049 = CRBAsmH
 5370   { 1050,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1050 = CRBAsmHE
 5371   { 1051,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1051 = CRBAsmL
 5372   { 1052,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1052 = CRBAsmLE
 5373   { 1053,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1053 = CRBAsmLH
 5374   { 1054,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1054 = CRBAsmNE
 5375   { 1055,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1055 = CRBAsmNH
 5376   { 1056,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1056 = CRBAsmNHE
 5377   { 1057,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1057 = CRBAsmNL
 5378   { 1058,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1058 = CRBAsmNLE
 5379   { 1059,	4,	0,	6,	12,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator), 0x0ULL, nullptr, nullptr, OperandInfo183, -1 ,nullptr },  // Inst #1059 = CRBAsmNLH

gen/lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc

 1557   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR

gen/lib/Target/X86/X86GenInstrInfo.inc

17690   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
18640   { 952,	2,	0,	0,	7,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3a80080088ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #952 = FARJMP16i
18641   { 953,	5,	0,	0,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc00000adULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #953 = FARJMP16m
18642   { 954,	2,	0,	0,	7,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3a800c0108ULL, nullptr, nullptr, OperandInfo8, -1 ,nullptr },  // Inst #954 = FARJMP32i
18643   { 955,	5,	0,	0,	5,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc000012dULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #955 = FARJMP32m
18644   { 956,	5,	0,	0,	758,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc001002dULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #956 = FARJMP64
18840   { 1152,	5,	0,	0,	831,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x3fc00000acULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #1152 = JMP16m
18841   { 1153,	5,	0,	0,	831,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x20003fc00000acULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #1153 = JMP16m_NT
18842   { 1154,	1,	0,	0,	816,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x3fc00000bcULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #1154 = JMP16r
18843   { 1155,	1,	0,	0,	816,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x20003fc00000bcULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #1155 = JMP16r_NT
18844   { 1156,	5,	0,	0,	831,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x3fc000012cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #1156 = JMP32m
18845   { 1157,	5,	0,	0,	831,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x20003fc000012cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #1157 = JMP32m_NT
18846   { 1158,	1,	0,	0,	816,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x3fc000013cULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #1158 = JMP32r
18847   { 1159,	1,	0,	0,	816,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x20003fc000013cULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #1159 = JMP32r_NT
18848   { 1160,	5,	0,	0,	831,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x3fc000002cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #1160 = JMP64m
18849   { 1161,	5,	0,	0,	831,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator), 0x20003fc000002cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #1161 = JMP64m_NT
18850   { 1162,	5,	0,	0,	831,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc001002cULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr },  // Inst #1162 = JMP64m_REX
18851   { 1163,	1,	0,	0,	816,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x3fc000003cULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #1163 = JMP64r
18852   { 1164,	1,	0,	0,	816,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator), 0x20003fc000003cULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #1164 = JMP64r_NT
18853   { 1165,	1,	0,	0,	816,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects), 0x3fc001003cULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #1165 = JMP64r_REX

gen/lib/Target/XCore/XCoreGenInstrInfo.inc

  501   { 2,	0,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::Variadic)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #2 = INLINEASM_BR
  675   { 176,	2,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #176 = BR_JT
  676   { 177,	2,	0,	0,	0,	0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr },  // Inst #177 = BR_JT32
  690   { 191,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #191 = BAU_1r
  713   { 214,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo38, -1 ,nullptr },  // Inst #214 = BRU_1r
  719   { 220,	1,	0,	4,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #220 = CLRSR_branch_lu6
  720   { 221,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #221 = CLRSR_branch_u6
  858   { 359,	1,	0,	4,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #359 = SETSR_branch_lu6
  859   { 360,	1,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo3, -1 ,nullptr },  // Inst #360 = SETSR_branch_u6
  894   { 395,	0,	0,	2,	0,	0|(1ULL<<MCID::Branch)|(1ULL<<MCID::IndirectBranch)|(1ULL<<MCID::Barrier)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Terminator)|(1ULL<<MCID::UnmodeledSideEffects)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, nullptr, -1 ,nullptr },  // Inst #395 = WAITEU_0R

include/llvm/CodeGen/MachineInstr.h

  713     return hasProperty(MCID::IndirectBranch, Type);

include/llvm/MC/MCInstrDesc.h

  300   bool isIndirectBranch() const { return Flags & (1ULL << MCID::IndirectBranch); }