|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6014 { 181, 6, 0, 0, 711, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #181 = ASRi
6015 { 182, 6, 0, 0, 712, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #182 = ASRr
6053 { 220, 6, 0, 0, 873, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #220 = LSLi
6054 { 221, 6, 0, 0, 712, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #221 = LSLr
6055 { 222, 6, 0, 0, 873, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #222 = LSRi
6056 { 223, 6, 0, 0, 712, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #223 = LSRr
6058 { 225, 7, 1, 4, 337, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr }, // Inst #225 = MLAv5
6073 { 240, 6, 1, 4, 336, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #240 = MULv5
6096 { 263, 6, 0, 0, 711, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #263 = RORi
6097 { 264, 6, 0, 0, 712, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #264 = RORr
6099 { 266, 5, 0, 0, 717, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #266 = RRXi
6103 { 270, 9, 2, 4, 340, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #270 = SMLALv5
6104 { 271, 7, 2, 4, 338, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #271 = SMULLv5
6124 { 291, 9, 2, 4, 340, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo74, -1 ,nullptr }, // Inst #291 = UMLALv5
6125 { 292, 7, 2, 4, 338, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x0ULL, nullptr, nullptr, OperandInfo75, -1 ,nullptr }, // Inst #292 = UMULLv5
6431 { 598, 6, 1, 4, 690, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #598 = ADCri
6432 { 599, 6, 1, 4, 697, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #599 = ADCrr
6433 { 600, 7, 1, 4, 700, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo129, -1 ,nullptr }, // Inst #600 = ADCrsi
6434 { 601, 8, 1, 4, 706, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo130, -1 ,nullptr }, // Inst #601 = ADCrsr
6435 { 602, 6, 1, 4, 690, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #602 = ADDri
6436 { 603, 6, 1, 4, 697, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #603 = ADDrr
6437 { 604, 7, 1, 4, 700, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #604 = ADDrsi
6438 { 605, 8, 1, 4, 706, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #605 = ADDrsr
6444 { 611, 6, 1, 4, 321, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #611 = ANDri
6445 { 612, 6, 1, 4, 322, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #612 = ANDrr
6446 { 613, 7, 1, 4, 323, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #613 = ANDrsi
6447 { 614, 8, 1, 4, 324, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #614 = ANDrsr
6450 { 617, 6, 1, 4, 321, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #617 = BICri
6451 { 618, 6, 1, 4, 322, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #618 = BICrr
6452 { 619, 7, 1, 4, 323, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #619 = BICrsi
6453 { 620, 8, 1, 4, 324, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #620 = BICrsr
6489 { 656, 6, 1, 4, 321, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #656 = EORri
6490 { 657, 6, 1, 4, 322, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #657 = EORrr
6491 { 658, 7, 1, 4, 323, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #658 = EORrsi
6492 { 659, 8, 1, 4, 324, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #659 = EORrsr
6582 { 749, 7, 1, 4, 337, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo166, -1 ,nullptr }, // Inst #749 = MLA
6586 { 753, 5, 1, 4, 864, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #753 = MOVi
6588 { 755, 5, 1, 4, 865, 0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #755 = MOVr
6589 { 756, 5, 1, 4, 865, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo170, -1 ,nullptr }, // Inst #756 = MOVr_TC
6590 { 757, 6, 1, 4, 326, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x3501ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #757 = MOVsi
6591 { 758, 7, 1, 4, 686, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2281ULL, nullptr, nullptr, OperandInfo172, -1 ,nullptr }, // Inst #758 = MOVsr
6602 { 769, 6, 1, 4, 336, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo43, -1 ,nullptr }, // Inst #769 = MUL
7458 { 1625, 5, 1, 4, 708, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0x2201ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1625 = MVNi
7459 { 1626, 5, 1, 4, 329, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2201ULL, nullptr, nullptr, OperandInfo73, -1 ,nullptr }, // Inst #1626 = MVNr
7460 { 1627, 6, 1, 4, 709, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x3501ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1627 = MVNsi
7461 { 1628, 7, 1, 4, 327, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x2281ULL, nullptr, nullptr, OperandInfo251, -1 ,nullptr }, // Inst #1628 = MVNsr
7470 { 1637, 6, 1, 4, 321, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #1637 = ORRri
7471 { 1638, 6, 1, 4, 322, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1638 = ORRrr
7472 { 1639, 7, 1, 4, 323, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #1639 = ORRrsi
7473 { 1640, 8, 1, 4, 324, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1640 = ORRrsr
7504 { 1671, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #1671 = RSBri
7505 { 1672, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1672 = RSBrr
7506 { 1673, 7, 1, 4, 700, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #1673 = RSBrsi
7507 { 1674, 8, 1, 4, 706, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1674 = RSBrsr
7508 { 1675, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #1675 = RSCri
7509 { 1676, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::UnmodeledSideEffects), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #1676 = RSCrr
7510 { 1677, 7, 1, 4, 700, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo129, -1 ,nullptr }, // Inst #1677 = RSCrsi
7511 { 1678, 8, 1, 4, 706, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo131, -1 ,nullptr }, // Inst #1678 = RSCrsr
7516 { 1683, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #1683 = SBCri
7517 { 1684, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x201ULL, ImplicitList1, ImplicitList1, OperandInfo128, -1 ,nullptr }, // Inst #1684 = SBCrr
7518 { 1685, 7, 1, 4, 700, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x1501ULL, ImplicitList1, ImplicitList1, OperandInfo129, -1 ,nullptr }, // Inst #1685 = SBCrsi
7519 { 1686, 8, 1, 4, 706, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0x281ULL, ImplicitList1, ImplicitList1, OperandInfo130, -1 ,nullptr }, // Inst #1686 = SBCrsr
7546 { 1713, 9, 2, 4, 340, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #1713 = SMLAL
7571 { 1738, 7, 2, 4, 381, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #1738 = SMULL
7650 { 1817, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo42, -1 ,nullptr }, // Inst #1817 = SUBri
7651 { 1818, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x201ULL, nullptr, nullptr, OperandInfo128, -1 ,nullptr }, // Inst #1818 = SUBrr
7652 { 1819, 7, 1, 4, 3, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x1501ULL, nullptr, nullptr, OperandInfo129, -1 ,nullptr }, // Inst #1819 = SUBrsi
7653 { 1820, 8, 1, 4, 41, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x281ULL, nullptr, nullptr, OperandInfo131, -1 ,nullptr }, // Inst #1820 = SUBrsr
7687 { 1854, 9, 2, 4, 340, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo261, -1 ,nullptr }, // Inst #1854 = UMLAL
7688 { 1855, 7, 2, 4, 339, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80ULL, nullptr, nullptr, OperandInfo263, -1 ,nullptr }, // Inst #1855 = UMULL
9572 { 3739, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo447, -1 ,nullptr }, // Inst #3739 = t2ADCri
9573 { 3740, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo448, -1 ,nullptr }, // Inst #3740 = t2ADCrr
9574 { 3741, 7, 1, 4, 702, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo449, -1 ,nullptr }, // Inst #3741 = t2ADCrs
9575 { 3742, 6, 1, 4, 690, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo450, -1 ,nullptr }, // Inst #3742 = t2ADDri
9577 { 3744, 6, 1, 4, 697, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo452, -1 ,nullptr }, // Inst #3744 = t2ADDrr
9578 { 3745, 7, 1, 4, 702, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo453, -1 ,nullptr }, // Inst #3745 = t2ADDrs
9580 { 3747, 6, 1, 4, 692, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3747 = t2ANDri
9581 { 3748, 6, 1, 4, 699, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3748 = t2ANDrr
9582 { 3749, 7, 1, 4, 703, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo449, -1 ,nullptr }, // Inst #3749 = t2ANDrs
9583 { 3750, 6, 1, 4, 872, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3750 = t2ASRri
9584 { 3751, 6, 1, 4, 879, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3751 = t2ASRrr
9593 { 3760, 6, 1, 4, 692, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3760 = t2BICri
9594 { 3761, 6, 1, 4, 699, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3761 = t2BICrr
9595 { 3762, 7, 1, 4, 703, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo449, -1 ,nullptr }, // Inst #3762 = t2BICrs
9629 { 3796, 6, 1, 4, 692, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3796 = t2EORri
9630 { 3797, 6, 1, 4, 699, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3797 = t2EORrr
9631 { 3798, 7, 1, 4, 703, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo449, -1 ,nullptr }, // Inst #3798 = t2EORrs
9709 { 3876, 6, 1, 4, 872, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3876 = t2LSLri
9710 { 3877, 6, 1, 4, 879, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3877 = t2LSLrr
9711 { 3878, 6, 1, 4, 872, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3878 = t2LSRri
9712 { 3879, 6, 1, 4, 879, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3879 = t2LSRrr
9720 { 3887, 5, 1, 4, 679, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo474, -1 ,nullptr }, // Inst #3887 = t2MOVi
9722 { 3889, 5, 1, 4, 877, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo475, -1 ,nullptr }, // Inst #3889 = t2MOVr
9737 { 3904, 5, 1, 4, 694, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::CheapAsAMove), 0xc80ULL, nullptr, nullptr, OperandInfo474, -1 ,nullptr }, // Inst #3904 = t2MVNi
9738 { 3905, 5, 1, 4, 695, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo479, -1 ,nullptr }, // Inst #3905 = t2MVNr
9739 { 3906, 6, 1, 4, 696, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo480, -1 ,nullptr }, // Inst #3906 = t2MVNs
9740 { 3907, 6, 1, 4, 42, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3907 = t2ORNri
9741 { 3908, 6, 1, 4, 43, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3908 = t2ORNrr
9742 { 3909, 7, 1, 4, 71, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo449, -1 ,nullptr }, // Inst #3909 = t2ORNrs
9743 { 3910, 6, 1, 4, 692, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3910 = t2ORRri
9744 { 3911, 6, 1, 4, 43, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3911 = t2ORRrr
9745 { 3912, 7, 1, 4, 703, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo449, -1 ,nullptr }, // Inst #3912 = t2ORRrs
9777 { 3944, 6, 1, 4, 872, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3944 = t2RORri
9778 { 3945, 6, 1, 4, 879, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3945 = t2RORrr
9779 { 3946, 5, 1, 4, 872, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, ImplicitList1, nullptr, OperandInfo479, -1 ,nullptr }, // Inst #3946 = t2RRX
9780 { 3947, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo447, -1 ,nullptr }, // Inst #3947 = t2RSBri
9781 { 3948, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0xc80ULL, nullptr, nullptr, OperandInfo448, -1 ,nullptr }, // Inst #3948 = t2RSBrr
9782 { 3949, 7, 1, 4, 704, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo449, -1 ,nullptr }, // Inst #3949 = t2RSBrs
9787 { 3954, 6, 1, 4, 690, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo447, -1 ,nullptr }, // Inst #3954 = t2SBCri
9788 { 3955, 6, 1, 4, 697, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo448, -1 ,nullptr }, // Inst #3955 = t2SBCrr
9789 { 3956, 7, 1, 4, 702, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::HasPostISelHook), 0xc80ULL, ImplicitList1, ImplicitList1, OperandInfo449, -1 ,nullptr }, // Inst #3956 = t2SBCrs
9900 { 4067, 6, 1, 4, 1, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo450, -1 ,nullptr }, // Inst #4067 = t2SUBri
9902 { 4069, 6, 1, 4, 2, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo452, -1 ,nullptr }, // Inst #4069 = t2SUBrr
9903 { 4070, 7, 1, 4, 35, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0xc80ULL, nullptr, nullptr, OperandInfo453, -1 ,nullptr }, // Inst #4070 = t2SUBrs
9958 { 4125, 6, 2, 2, 37, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x80c80ULL, ImplicitList1, nullptr, OperandInfo497, -1 ,nullptr }, // Inst #4125 = tADC
9960 { 4127, 6, 2, 2, 38, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo498, -1 ,nullptr }, // Inst #4127 = tADDi3
9961 { 4128, 6, 2, 2, 38, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo499, -1 ,nullptr }, // Inst #4128 = tADDi8
9964 { 4131, 6, 2, 2, 37, 0|(1ULL<<MCID::Add)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo502, -1 ,nullptr }, // Inst #4131 = tADDrr
9968 { 4135, 6, 2, 2, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo497, -1 ,nullptr }, // Inst #4135 = tAND
9969 { 4136, 6, 2, 2, 872, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo498, -1 ,nullptr }, // Inst #4136 = tASRri
9970 { 4137, 6, 2, 2, 879, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo497, -1 ,nullptr }, // Inst #4137 = tASRrr
9972 { 4139, 6, 2, 2, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo497, -1 ,nullptr }, // Inst #4139 = tBIC
9988 { 4155, 6, 2, 2, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo497, -1 ,nullptr }, // Inst #4155 = tEOR
10005 { 4172, 6, 2, 2, 872, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo498, -1 ,nullptr }, // Inst #4172 = tLSLri
10006 { 4173, 6, 2, 2, 879, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo497, -1 ,nullptr }, // Inst #4173 = tLSLrr
10007 { 4174, 6, 2, 2, 872, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo498, -1 ,nullptr }, // Inst #4174 = tLSRri
10008 { 4175, 6, 2, 2, 879, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo497, -1 ,nullptr }, // Inst #4175 = tLSRrr
10010 { 4177, 5, 2, 2, 1017, 0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo515, -1 ,nullptr }, // Inst #4177 = tMOVi8
10012 { 4179, 6, 2, 2, 881, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo516, -1 ,nullptr }, // Inst #4179 = tMUL
10013 { 4180, 5, 2, 2, 870, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo517, -1 ,nullptr }, // Inst #4180 = tMVN
10014 { 4181, 6, 2, 2, 313, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo497, -1 ,nullptr }, // Inst #4181 = tORR
10021 { 4188, 6, 2, 2, 878, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo497, -1 ,nullptr }, // Inst #4188 = tROR
10022 { 4189, 5, 2, 2, 38, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo517, -1 ,nullptr }, // Inst #4189 = tRSB
10023 { 4190, 6, 2, 2, 37, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef)|(1ULL<<MCID::UnmodeledSideEffects), 0x80c80ULL, ImplicitList1, nullptr, OperandInfo497, -1 ,nullptr }, // Inst #4190 = tSBC
10033 { 4200, 6, 2, 2, 38, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo498, -1 ,nullptr }, // Inst #4200 = tSUBi3
10034 { 4201, 6, 2, 2, 38, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo499, -1 ,nullptr }, // Inst #4201 = tSUBi8
10035 { 4202, 6, 2, 2, 37, 0|(1ULL<<MCID::Predicable)|(1ULL<<MCID::HasOptionalDef), 0x80c80ULL, nullptr, nullptr, OperandInfo502, -1 ,nullptr }, // Inst #4202 = tSUBrr
include/llvm/CodeGen/MachineInstr.h 663 return hasProperty(MCID::HasOptionalDef, Type);
include/llvm/MC/MCInstrDesc.h 258 bool hasOptionalDef() const { return Flags & (1ULL << MCID::HasOptionalDef); }
unittests/CodeGen/MachineInstrTest.cpp 178 0, NumOps, NumDefs, 0, 0, 1ULL << MCID::HasOptionalDef,
247 0, NumOps, NumDefs, 0, 0, 1ULL << MCID::HasOptionalDef,