|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenInstrInfo.inc 6361 { 528, 3, 1, 0, 388, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #528 = t2LDRpci_pic
6545 { 712, 5, 1, 4, 386, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo154, -1 ,nullptr }, // Inst #712 = LDRBi12
6546 { 713, 6, 1, 4, 387, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x300ULL, nullptr, nullptr, OperandInfo155, -1 ,nullptr }, // Inst #713 = LDRBrs
6575 { 742, 5, 1, 4, 397, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #742 = LDRcp
6576 { 743, 5, 1, 4, 385, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x310ULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #743 = LDRi12
6577 { 744, 6, 1, 4, 348, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x300ULL, nullptr, nullptr, OperandInfo161, -1 ,nullptr }, // Inst #744 = LDRrs
8467 { 2634, 5, 1, 4, 585, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x18b05ULL, nullptr, nullptr, OperandInfo83, -1 ,nullptr }, // Inst #2634 = VLDRD
8468 { 2635, 5, 1, 4, 744, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x18b11ULL, nullptr, nullptr, OperandInfo362, -1 ,nullptr }, // Inst #2635 = VLDRH
8469 { 2636, 5, 1, 4, 586, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0x18b05ULL, nullptr, nullptr, OperandInfo363, -1 ,nullptr }, // Inst #2636 = VLDRS
9703 { 3870, 5, 1, 4, 389, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8bULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #3870 = t2LDRi12
9704 { 3871, 5, 1, 4, 389, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8cULL, nullptr, nullptr, OperandInfo72, -1 ,nullptr }, // Inst #3871 = t2LDRi8
9705 { 3872, 4, 1, 4, 389, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8eULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #3872 = t2LDRpci
9706 { 3873, 6, 1, 4, 390, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8dULL, nullptr, nullptr, OperandInfo471, -1 ,nullptr }, // Inst #3873 = t2LDRs
9995 { 4162, 5, 1, 2, 903, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL, nullptr, nullptr, OperandInfo512, -1 ,nullptr }, // Inst #4162 = tLDRBi
9996 { 4163, 5, 1, 2, 394, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc87ULL, nullptr, nullptr, OperandInfo513, -1 ,nullptr }, // Inst #4163 = tLDRBr
9997 { 4164, 5, 1, 2, 903, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL, nullptr, nullptr, OperandInfo512, -1 ,nullptr }, // Inst #4164 = tLDRHi
9998 { 4165, 5, 1, 2, 394, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc88ULL, nullptr, nullptr, OperandInfo513, -1 ,nullptr }, // Inst #4165 = tLDRHr
10001 { 4168, 5, 1, 2, 904, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL, nullptr, nullptr, OperandInfo512, -1 ,nullptr }, // Inst #4168 = tLDRi
10002 { 4169, 4, 1, 2, 904, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc8aULL, nullptr, nullptr, OperandInfo505, -1 ,nullptr }, // Inst #4169 = tLDRpci
10003 { 4170, 5, 1, 2, 395, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable)|(1ULL<<MCID::Rematerializable), 0xc89ULL, nullptr, nullptr, OperandInfo513, -1 ,nullptr }, // Inst #4170 = tLDRr
10004 { 4171, 5, 1, 2, 904, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Predicable), 0xc8aULL, nullptr, nullptr, OperandInfo514, -1 ,nullptr }, // Inst #4171 = tLDRspi
gen/lib/Target/AVR/AVRGenInstrInfo.inc 686 { 203, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo49, -1 ,nullptr }, // Inst #203 = INWRdA
687 { 204, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #204 = LDDWRdPtrQ
688 { 205, 3, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #205 = LDDWRdYQ
690 { 207, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #207 = LDSWRdK
691 { 208, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #208 = LDWRdPtr
694 { 211, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #211 = LPMWRdZ
695 { 212, 2, 1, 2, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList4, OperandInfo56, -1 ,nullptr }, // Inst #212 = LPMWRdZPi
772 { 289, 2, 1, 2, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #289 = INRdA
777 { 294, 3, 1, 2, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo80, -1 ,nullptr }, // Inst #294 = LDDRdPtrQ
779 { 296, 2, 1, 2, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo81, -1 ,nullptr }, // Inst #296 = LDRdPtr
782 { 299, 2, 1, 4, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo79, -1 ,nullptr }, // Inst #299 = LDSRdK
783 { 300, 0, 0, 2, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, ImplicitList4, ImplicitList7, nullptr, -1 ,nullptr }, // Inst #300 = LPM
784 { 301, 2, 1, 2, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo78, -1 ,nullptr }, // Inst #301 = LPMRdZ
785 { 302, 2, 1, 2, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList4, OperandInfo78, -1 ,nullptr }, // Inst #302 = LPMRdZPi
gen/lib/Target/MSP430/MSP430GenInstrInfo.inc 1027 { 386, 3, 1, 4, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo57, -1 ,nullptr }, // Inst #386 = MOV16rm
1028 { 387, 2, 1, 2, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr }, // Inst #387 = MOV16rn
1038 { 397, 3, 1, 4, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr }, // Inst #397 = MOV8rm
1039 { 398, 2, 1, 2, 0, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr }, // Inst #398 = MOV8rn
gen/lib/Target/Mips/MipsGenInstrInfo.inc 5176 { 361, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo89, -1 ,nullptr }, // Inst #361 = LOAD_ACC128
5177 { 362, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo90, -1 ,nullptr }, // Inst #362 = LOAD_ACC64
5178 { 363, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo91, -1 ,nullptr }, // Inst #363 = LOAD_ACC64DSP
5179 { 364, 3, 1, 4, 0, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo92, -1 ,nullptr }, // Inst #364 = LOAD_CCOND_DSP
6501 { 1686, 3, 1, 4, 426, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1686 = LB
6502 { 1687, 3, 1, 4, 1158, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1687 = LB64
6503 { 1688, 3, 1, 4, 436, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1688 = LBE
6504 { 1689, 3, 1, 4, 1083, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1689 = LBE_MM
6505 { 1690, 3, 1, 2, 1110, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #1690 = LBU16_MM
6509 { 1694, 3, 1, 4, 1111, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1694 = LB_MM
6511 { 1696, 3, 1, 4, 427, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1696 = LBu
6512 { 1697, 3, 1, 4, 1159, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1697 = LBu64
6513 { 1698, 3, 1, 4, 437, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1698 = LBuE
6514 { 1699, 3, 1, 4, 1084, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1699 = LBuE_MM
6515 { 1700, 3, 1, 4, 1110, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1700 = LBu_MM
6516 { 1701, 3, 1, 4, 1155, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1701 = LD
6529 { 1714, 4, 1, 4, 1165, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #1714 = LDL
6531 { 1716, 4, 1, 4, 1166, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #1716 = LDR
6541 { 1726, 3, 1, 4, 428, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1726 = LH
6542 { 1727, 3, 1, 4, 1160, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1727 = LH64
6543 { 1728, 3, 1, 4, 438, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1728 = LHE
6544 { 1729, 3, 1, 4, 1085, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1729 = LHE_MM
6545 { 1730, 3, 1, 2, 1112, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #1730 = LHU16_MM
6548 { 1733, 3, 1, 4, 1113, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1733 = LH_MM
6549 { 1734, 3, 1, 4, 429, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1734 = LHu
6550 { 1735, 3, 1, 4, 1161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1735 = LHu64
6551 { 1736, 3, 1, 4, 439, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1736 = LHuE
6552 { 1737, 3, 1, 4, 1086, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1737 = LHuE_MM
6553 { 1738, 3, 1, 4, 1112, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1738 = LHu_MM
6576 { 1761, 3, 1, 4, 430, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1761 = LW
6577 { 1762, 3, 1, 2, 1115, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo262, -1 ,nullptr }, // Inst #1762 = LW16_MM
6578 { 1763, 3, 1, 4, 1162, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1763 = LW64
6585 { 1770, 3, 1, 4, 1331, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #1770 = LWDSP
6586 { 1771, 3, 1, 4, 1494, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo280, -1 ,nullptr }, // Inst #1771 = LWDSP_MM
6587 { 1772, 3, 1, 4, 440, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1772 = LWE
6588 { 1773, 3, 1, 4, 1087, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1773 = LWE_MM
6589 { 1774, 3, 1, 2, 1115, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo281, -1 ,nullptr }, // Inst #1774 = LWGP_MM
6590 { 1775, 4, 1, 4, 443, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1775 = LWL
6591 { 1776, 4, 1, 4, 1163, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #1776 = LWL64
6592 { 1777, 4, 1, 4, 445, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1777 = LWLE
6593 { 1778, 4, 1, 4, 1088, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1778 = LWLE_MM
6594 { 1779, 4, 1, 4, 1116, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1779 = LWL_MM
6601 { 1786, 4, 1, 4, 444, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1786 = LWR
6602 { 1787, 4, 1, 4, 1164, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo272, -1 ,nullptr }, // Inst #1787 = LWR64
6603 { 1788, 4, 1, 4, 446, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x6ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1788 = LWRE
6604 { 1789, 4, 1, 4, 1089, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1789 = LWRE_MM
6605 { 1790, 4, 1, 4, 1119, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo282, -1 ,nullptr }, // Inst #1790 = LWR_MM
6606 { 1791, 3, 1, 2, 1115, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::UnmodeledSideEffects), 0x0ULL, nullptr, nullptr, OperandInfo285, -1 ,nullptr }, // Inst #1791 = LWSP_MM
6608 { 1793, 3, 1, 4, 1120, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1793 = LWU_MM
6614 { 1799, 3, 1, 4, 1115, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1799 = LW_MM
6615 { 1800, 3, 1, 4, 1144, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x6ULL, nullptr, nullptr, OperandInfo87, -1 ,nullptr }, // Inst #1800 = LW_MMR6
6616 { 1801, 3, 1, 4, 1157, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x2ULL, nullptr, nullptr, OperandInfo102, -1 ,nullptr }, // Inst #1801 = LWu
gen/lib/Target/SystemZ/SystemZGenInstrInfo.inc 4638 { 318, 4, 1, 0, 36, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x1dULL, nullptr, nullptr, OperandInfo67, -1 ,nullptr }, // Inst #318 = L128
4648 { 328, 4, 1, 0, 33, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x8dULL, nullptr, nullptr, OperandInfo55, -1 ,nullptr }, // Inst #328 = LMux
4655 { 335, 4, 1, 0, 352, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x1dULL, nullptr, nullptr, OperandInfo77, -1 ,nullptr }, // Inst #335 = LX
5645 { 1325, 4, 1, 4, 33, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x89ULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1325 = L
5683 { 1363, 4, 1, 4, 351, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x109ULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1363 = LD
5685 { 1365, 4, 1, 6, 351, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x89ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1365 = LDE32
5697 { 1377, 4, 1, 6, 351, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x10dULL, nullptr, nullptr, OperandInfo135, -1 ,nullptr }, // Inst #1377 = LDY
5698 { 1378, 4, 1, 4, 350, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x89ULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1378 = LE
5707 { 1387, 4, 1, 6, 350, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x8dULL, nullptr, nullptr, OperandInfo142, -1 ,nullptr }, // Inst #1387 = LEY
5709 { 1389, 4, 1, 6, 33, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x8dULL, nullptr, nullptr, OperandInfo168, -1 ,nullptr }, // Inst #1389 = LFH
5712 { 1392, 4, 1, 6, 35, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x10dULL, nullptr, nullptr, OperandInfo36, -1 ,nullptr }, // Inst #1392 = LG
5727 { 1407, 2, 1, 6, 35, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo95, -1 ,nullptr }, // Inst #1407 = LGRL
6001 { 1681, 2, 1, 6, 33, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo152, -1 ,nullptr }, // Inst #1681 = LRL
6037 { 1717, 4, 1, 6, 33, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x8dULL, nullptr, nullptr, OperandInfo134, -1 ,nullptr }, // Inst #1717 = LY
gen/lib/Target/X86/X86GenInstrInfo.inc17873 { 185, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #185 = AVX1_SETALLONES
17874 { 186, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #186 = AVX2_SETALLONES
17875 { 187, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #187 = AVX512_128_SET0
17876 { 188, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo46, -1 ,nullptr }, // Inst #188 = AVX512_256_SET0
17877 { 189, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #189 = AVX512_512_SET0
17878 { 190, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo47, -1 ,nullptr }, // Inst #190 = AVX512_512_SETALLONES
17881 { 193, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo45, -1 ,nullptr }, // Inst #193 = AVX512_FsFLD0F128
17882 { 194, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo50, -1 ,nullptr }, // Inst #194 = AVX512_FsFLD0SD
17883 { 195, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo51, -1 ,nullptr }, // Inst #195 = AVX512_FsFLD0SS
17884 { 196, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo44, -1 ,nullptr }, // Inst #196 = AVX_SET0
17885 { 197, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #197 = FsFLD0F128
17886 { 198, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo53, -1 ,nullptr }, // Inst #198 = FsFLD0SD
17887 { 199, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo54, -1 ,nullptr }, // Inst #199 = FsFLD0SS
17896 { 208, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr }, // Inst #208 = MMX_SET0
17927 { 239, 6, 1, 0, 1159, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #239 = VMOVAPSZ128rm_NOVLX
17929 { 241, 6, 1, 0, 1185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #241 = VMOVAPSZ256rm_NOVLX
17931 { 243, 6, 1, 0, 1159, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #243 = VMOVUPSZ128rm_NOVLX
17933 { 245, 6, 1, 0, 1185, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x0ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #245 = VMOVUPSZ256rm_NOVLX
17934 { 246, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #246 = V_SET0
17935 { 247, 1, 1, 0, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo52, -1 ,nullptr }, // Inst #247 = V_SETALLONES
18953 { 1265, 6, 1, 0, 62, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x200000ULL, ImplicitList12, ImplicitList13, OperandInfo197, -1 ,nullptr }, // Inst #1265 = LD_Fp32m
18956 { 1268, 6, 1, 0, 62, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x200000ULL, ImplicitList12, ImplicitList13, OperandInfo198, -1 ,nullptr }, // Inst #1268 = LD_Fp64m
18958 { 1270, 6, 1, 0, 62, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x200000ULL, ImplicitList12, ImplicitList13, OperandInfo199, -1 ,nullptr }, // Inst #1270 = LD_Fp80m
19167 { 1479, 6, 1, 0, 188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad), 0x1bc0002021ULL, nullptr, nullptr, OperandInfo246, -1 ,nullptr }, // Inst #1479 = MMX_MOVQ64rm
19342 { 1654, 6, 1, 0, 938, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x22c00000a1ULL, nullptr, nullptr, OperandInfo126, -1 ,nullptr }, // Inst #1654 = MOV16rm
19362 { 1674, 6, 1, 0, 62, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x22c0000121ULL, nullptr, nullptr, OperandInfo115, -1 ,nullptr }, // Inst #1674 = MOV32rm
19379 { 1691, 6, 1, 0, 62, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x22c0010021ULL, nullptr, nullptr, OperandInfo117, -1 ,nullptr }, // Inst #1691 = MOV64rm
19398 { 1710, 6, 1, 0, 62, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2280000021ULL, nullptr, nullptr, OperandInfo162, -1 ,nullptr }, // Inst #1710 = MOV8rm
19399 { 1711, 6, 1, 0, 62, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2280000021ULL, nullptr, nullptr, OperandInfo286, -1 ,nullptr }, // Inst #1711 = MOV8rm_NOREX
19404 { 1716, 6, 1, 0, 11, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0xa08002821ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1716 = MOVAPDrm
19408 { 1720, 6, 1, 0, 11, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0xa04002021ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1720 = MOVAPSrm
19428 { 1740, 6, 1, 0, 177, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x1bcc002821ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1740 = MOVDQArm
19432 { 1744, 6, 1, 0, 624, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x1bcc003021ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1744 = MOVDQUrm
19465 { 1777, 6, 1, 0, 747, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x408003821ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1777 = MOVSDrm
19466 { 1778, 6, 1, 0, 747, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x408003821ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #1778 = MOVSDrm_alt
19478 { 1790, 6, 1, 0, 747, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x404003021ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1790 = MOVSSrm
19479 { 1791, 6, 1, 0, 747, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x404003021ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #1791 = MOVSSrm_alt
19504 { 1816, 6, 1, 0, 625, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x408002821ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1816 = MOVUPDrm
19508 { 1820, 6, 1, 0, 625, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x404002021ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #1820 = MOVUPSrm
25264 { 7576, 6, 1, 0, 13, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x10a18002821ULL, nullptr, nullptr, OperandInfo413, -1 ,nullptr }, // Inst #7576 = VMOVAPDYrm
25269 { 7581, 6, 1, 0, 1159, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2004a38002821ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7581 = VMOVAPDZ128rm
25280 { 7592, 6, 1, 0, 1185, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4014a38002821ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #7592 = VMOVAPDZ256rm
25291 { 7603, 6, 1, 0, 1185, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8084a38002821ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #7603 = VMOVAPDZrm
25301 { 7613, 6, 1, 0, 11, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0xa18002821ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #7613 = VMOVAPDrm
25305 { 7617, 6, 1, 0, 13, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x10a14002021ULL, nullptr, nullptr, OperandInfo413, -1 ,nullptr }, // Inst #7617 = VMOVAPSYrm
25310 { 7622, 6, 1, 0, 1159, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2000a34002021ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7622 = VMOVAPSZ128rm
25321 { 7633, 6, 1, 0, 1185, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4010a34002021ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #7633 = VMOVAPSZ256rm
25332 { 7644, 6, 1, 0, 1185, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8080a34002021ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #7644 = VMOVAPSZrm
25342 { 7654, 6, 1, 0, 11, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0xa14002021ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #7654 = VMOVAPSrm
25375 { 7687, 6, 1, 0, 1161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2001bfc002821ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7687 = VMOVDQA32Z128rm
25386 { 7698, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4011bfc002821ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #7698 = VMOVDQA32Z256rm
25397 { 7709, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8081bfc002821ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #7709 = VMOVDQA32Zrm
25408 { 7720, 6, 1, 0, 1161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2005bfc002821ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7720 = VMOVDQA64Z128rm
25419 { 7731, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4015bfc002821ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #7731 = VMOVDQA64Z256rm
25430 { 7742, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8085bfc002821ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #7742 = VMOVDQA64Zrm
25440 { 7752, 6, 1, 0, 447, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x11bdc002821ULL, nullptr, nullptr, OperandInfo413, -1 ,nullptr }, // Inst #7752 = VMOVDQAYrm
25444 { 7756, 6, 1, 0, 177, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x1bdc002821ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #7756 = VMOVDQArm
25449 { 7761, 6, 1, 0, 1161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2005bfc003821ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7761 = VMOVDQU16Z128rm
25460 { 7772, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4015bfc003821ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #7772 = VMOVDQU16Z256rm
25471 { 7783, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8085bfc003821ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #7783 = VMOVDQU16Zrm
25482 { 7794, 6, 1, 0, 1161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2001bfc003021ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7794 = VMOVDQU32Z128rm
25493 { 7805, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4011bfc003021ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #7805 = VMOVDQU32Z256rm
25504 { 7816, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8081bfc003021ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #7816 = VMOVDQU32Zrm
25515 { 7827, 6, 1, 0, 1161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2005bfc003021ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7827 = VMOVDQU64Z128rm
25526 { 7838, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4015bfc003021ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #7838 = VMOVDQU64Z256rm
25537 { 7849, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8085bfc003021ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #7849 = VMOVDQU64Zrm
25548 { 7860, 6, 1, 0, 1161, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2001bfc003821ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7860 = VMOVDQU8Z128rm
25559 { 7871, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4011bfc003821ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #7871 = VMOVDQU8Z256rm
25570 { 7882, 6, 1, 0, 1188, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8081bfc003821ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #7882 = VMOVDQU8Zrm
25580 { 7892, 6, 1, 0, 447, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x11bdc003021ULL, nullptr, nullptr, OperandInfo413, -1 ,nullptr }, // Inst #7892 = VMOVDQUYrm
25584 { 7896, 6, 1, 0, 177, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x1bdc003021ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #7896 = VMOVDQUrm
25647 { 7959, 6, 1, 0, 1142, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x1004438003821ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #7959 = VMOVSDZrm
25648 { 7960, 6, 1, 0, 1142, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x1004438003821ULL, nullptr, nullptr, OperandInfo473, -1 ,nullptr }, // Inst #7960 = VMOVSDZrm_alt
25658 { 7970, 6, 1, 0, 747, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x418003821ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #7970 = VMOVSDrm
25659 { 7971, 6, 1, 0, 747, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x418003821ULL, nullptr, nullptr, OperandInfo169, -1 ,nullptr }, // Inst #7971 = VMOVSDrm_alt
25712 { 8024, 6, 1, 0, 1142, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x800434003021ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #8024 = VMOVSSZrm
25713 { 8025, 6, 1, 0, 1142, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x800434003021ULL, nullptr, nullptr, OperandInfo475, -1 ,nullptr }, // Inst #8025 = VMOVSSZrm_alt
25723 { 8035, 6, 1, 0, 747, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x414003021ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #8035 = VMOVSSrm
25724 { 8036, 6, 1, 0, 747, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x414003021ULL, nullptr, nullptr, OperandInfo171, -1 ,nullptr }, // Inst #8036 = VMOVSSrm_alt
25728 { 8040, 6, 1, 0, 13, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x10418002821ULL, nullptr, nullptr, OperandInfo413, -1 ,nullptr }, // Inst #8040 = VMOVUPDYrm
25733 { 8045, 6, 1, 0, 1159, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2004438002821ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #8045 = VMOVUPDZ128rm
25744 { 8056, 6, 1, 0, 1185, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4014438002821ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #8056 = VMOVUPDZ256rm
25755 { 8067, 6, 1, 0, 1185, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8084438002821ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #8067 = VMOVUPDZrm
25765 { 8077, 6, 1, 0, 11, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x418002821ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #8077 = VMOVUPDrm
25769 { 8081, 6, 1, 0, 13, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x10414002021ULL, nullptr, nullptr, OperandInfo413, -1 ,nullptr }, // Inst #8081 = VMOVUPSYrm
25774 { 8086, 6, 1, 0, 1159, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x2000434002021ULL, nullptr, nullptr, OperandInfo68, -1 ,nullptr }, // Inst #8086 = VMOVUPSZ128rm
25785 { 8097, 6, 1, 0, 1185, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x4010434002021ULL, nullptr, nullptr, OperandInfo70, -1 ,nullptr }, // Inst #8097 = VMOVUPSZ256rm
25796 { 8108, 6, 1, 0, 1185, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x8080434002021ULL, nullptr, nullptr, OperandInfo419, -1 ,nullptr }, // Inst #8108 = VMOVUPSZrm
25806 { 8118, 6, 1, 0, 11, 0|(1ULL<<MCID::FoldableAsLoad)|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::Rematerializable), 0x414002021ULL, nullptr, nullptr, OperandInfo100, -1 ,nullptr }, // Inst #8118 = VMOVUPSrm
include/llvm/CodeGen/MachineInstr.h 803 return hasProperty(MCID::FoldableAsLoad, Type);
include/llvm/MC/MCInstrDesc.h 358 bool canFoldAsLoad() const { return Flags & (1ULL << MCID::FoldableAsLoad); }