|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AMDGPU/AMDGPUGenInstrInfo.inc19614 { 3552, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x80000000008002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3552 = V_DOT2C_F32_F16_dpp
19615 { 3553, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000000000102ULL, ImplicitList2, nullptr, OperandInfo367, -1 ,nullptr }, // Inst #3553 = V_DOT2C_F32_F16_e32
19616 { 3554, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000000000402ULL, ImplicitList2, nullptr, OperandInfo368, -1 ,nullptr }, // Inst #3554 = V_DOT2C_F32_F16_e64
19617 { 3555, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x80000000008002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3555 = V_DOT2C_I32_I16_dpp
19618 { 3556, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000000000102ULL, ImplicitList2, nullptr, OperandInfo369, -1 ,nullptr }, // Inst #3556 = V_DOT2C_I32_I16_e32
19619 { 3557, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000000000402ULL, ImplicitList2, nullptr, OperandInfo370, -1 ,nullptr }, // Inst #3557 = V_DOT2C_I32_I16_e64
19623 { 3561, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x80000000008002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3561 = V_DOT4C_I32_I8_dpp
19624 { 3562, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000000000102ULL, ImplicitList2, nullptr, OperandInfo369, -1 ,nullptr }, // Inst #3562 = V_DOT4C_I32_I8_e32
19625 { 3563, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000000000402ULL, ImplicitList2, nullptr, OperandInfo370, -1 ,nullptr }, // Inst #3563 = V_DOT4C_I32_I8_e64
19628 { 3566, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x80000000008002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3566 = V_DOT8C_I32_I4_dpp
19629 { 3567, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000000000102ULL, ImplicitList2, nullptr, OperandInfo369, -1 ,nullptr }, // Inst #3567 = V_DOT8C_I32_I4_e32
19630 { 3568, 7, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x80000000000402ULL, ImplicitList2, nullptr, OperandInfo370, -1 ,nullptr }, // Inst #3568 = V_DOT8C_I32_I4_e64
19669 { 3607, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3607 = V_FMAC_F16_dpp
19670 { 3608, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo376, -1 ,nullptr }, // Inst #3608 = V_FMAC_F16_e32
19671 { 3609, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo377, -1 ,nullptr }, // Inst #3609 = V_FMAC_F16_e64
19672 { 3610, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo378, -1 ,nullptr }, // Inst #3610 = V_FMAC_F16_sdwa
19673 { 3611, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3611 = V_FMAC_F32_dpp
19674 { 3612, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo379, -1 ,nullptr }, // Inst #3612 = V_FMAC_F32_e32
19675 { 3613, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo380, -1 ,nullptr }, // Inst #3613 = V_FMAC_F32_e64
19676 { 3614, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo381, -1 ,nullptr }, // Inst #3614 = V_FMAC_F32_sdwa
19781 { 3719, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3719 = V_MAC_F16_dpp
19782 { 3720, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo376, -1 ,nullptr }, // Inst #3720 = V_MAC_F16_e32
19783 { 3721, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo377, -1 ,nullptr }, // Inst #3721 = V_MAC_F16_e64
19784 { 3722, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo378, -1 ,nullptr }, // Inst #3722 = V_MAC_F16_sdwa
19785 { 3723, 10, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::Convergent), 0x8002ULL, ImplicitList2, nullptr, OperandInfo366, -1 ,nullptr }, // Inst #3723 = V_MAC_F32_dpp
19786 { 3724, 4, 1, 4, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x102ULL, ImplicitList2, nullptr, OperandInfo379, -1 ,nullptr }, // Inst #3724 = V_MAC_F32_e32
19787 { 3725, 9, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::HasPostISelHook)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0xa00000000402ULL, ImplicitList2, nullptr, OperandInfo380, -1 ,nullptr }, // Inst #3725 = V_MAC_F32_e64
19788 { 3726, 12, 1, 8, 2, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable)|(1ULL<<MCID::ExtraSrcRegAllocReq), 0x4002ULL, ImplicitList2, nullptr, OperandInfo381, -1 ,nullptr }, // Inst #3726 = V_MAC_F32_sdwa
gen/lib/Target/SystemZ/SystemZGenInstrInfo.inc 4663 { 343, 3, 1, 0, 146, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x23000ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #343 = NIFMux
4664 { 344, 3, 1, 6, 148, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #344 = NIHF64
4665 { 345, 3, 1, 4, 149, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #345 = NIHH64
4666 { 346, 3, 1, 4, 150, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #346 = NIHL64
4667 { 347, 3, 1, 0, 146, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #347 = NIHMux
4668 { 348, 3, 1, 6, 151, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #348 = NILF64
4669 { 349, 3, 1, 4, 152, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #349 = NILH64
4670 { 350, 3, 1, 4, 153, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo66, -1 ,nullptr }, // Inst #350 = NILL64
4671 { 351, 3, 1, 0, 146, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #351 = NILMux
6157 { 1837, 3, 1, 6, 148, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x23000ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #1837 = NIHF
6158 { 1838, 3, 1, 4, 149, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #1838 = NIHH
6159 { 1839, 3, 1, 4, 150, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo115, -1 ,nullptr }, // Inst #1839 = NIHL
6160 { 1840, 3, 1, 6, 151, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x23000ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #1840 = NILF
6161 { 1841, 3, 1, 4, 152, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #1841 = NILH
6162 { 1842, 3, 1, 4, 153, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo108, -1 ,nullptr }, // Inst #1842 = NILL
gen/lib/Target/X86/X86GenInstrInfo.inc17862 { 174, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #174 = ADD16ri8_DB
17863 { 175, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #175 = ADD16ri_DB
17864 { 176, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #176 = ADD16rr_DB
17865 { 177, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #177 = ADD32ri8_DB
17866 { 178, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #178 = ADD32ri_DB
17867 { 179, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #179 = ADD32rr_DB
17868 { 180, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #180 = ADD64ri32_DB
17869 { 181, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #181 = ADD64ri8_DB
17870 { 182, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #182 = ADD64rr_DB
17871 { 183, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr), 0x0ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #183 = ADD8ri_DB
17872 { 184, 3, 1, 0, 1, 0|(1ULL<<MCID::Pseudo)|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x0ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #184 = ADD8rr_DB
17991 { 303, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x20400800b8ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #303 = ADD16ri
17992 { 304, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c00200b8ULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #304 = ADD16ri8
17994 { 306, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x400000b0ULL, nullptr, ImplicitList1, OperandInfo37, -1 ,nullptr }, // Inst #306 = ADD16rr
18000 { 312, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x20400c0138ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #312 = ADD32ri
18001 { 313, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c0020138ULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #313 = ADD32ri8
18003 { 315, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x40000130ULL, nullptr, ImplicitList1, OperandInfo39, -1 ,nullptr }, // Inst #315 = ADD32rr
18009 { 321, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x2040110038ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #321 = ADD64ri32
18010 { 322, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c0030038ULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #322 = ADD64ri8
18012 { 324, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x40010030ULL, nullptr, ImplicitList1, OperandInfo41, -1 ,nullptr }, // Inst #324 = ADD64rr
18018 { 330, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x2000020038ULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #330 = ADD8ri
18021 { 333, 3, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr)|(1ULL<<MCID::Commutable), 0x30ULL, nullptr, ImplicitList1, OperandInfo43, -1 ,nullptr }, // Inst #333 = ADD8rr
18536 { 848, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3fc00000b9ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #848 = DEC16r
18539 { 851, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3fc0000139ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #851 = DEC32r
18542 { 854, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3fc0010039ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #854 = DEC64r
18544 { 856, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3f80000039ULL, nullptr, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #856 = DEC8r
18772 { 1084, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3fc00000b8ULL, nullptr, ImplicitList1, OperandInfo127, -1 ,nullptr }, // Inst #1084 = INC16r
18775 { 1087, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3fc0000138ULL, nullptr, ImplicitList1, OperandInfo71, -1 ,nullptr }, // Inst #1087 = INC32r
18778 { 1090, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3fc0010038ULL, nullptr, ImplicitList1, OperandInfo72, -1 ,nullptr }, // Inst #1090 = INC64r
18780 { 1092, 2, 1, 0, 1, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x3f80000038ULL, nullptr, ImplicitList1, OperandInfo190, -1 ,nullptr }, // Inst #1092 = INC8r
20303 { 2615, 3, 1, 0, 290, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x30400200bcULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2615 = SHL16ri
20309 { 2621, 3, 1, 0, 290, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x304002013cULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2621 = SHL32ri
20315 { 2627, 3, 1, 0, 290, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x304003003cULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2627 = SHL64ri
20321 { 2633, 3, 1, 0, 290, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x300002003cULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2633 = SHL8ri
20453 { 2765, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x20400800bdULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2765 = SUB16ri
20454 { 2766, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c00200bdULL, nullptr, ImplicitList1, OperandInfo36, -1 ,nullptr }, // Inst #2766 = SUB16ri8
20462 { 2774, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x20400c013dULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2774 = SUB32ri
20463 { 2775, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c002013dULL, nullptr, ImplicitList1, OperandInfo38, -1 ,nullptr }, // Inst #2775 = SUB32ri8
20471 { 2783, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x204011003dULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2783 = SUB64ri32
20472 { 2784, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x20c003003dULL, nullptr, ImplicitList1, OperandInfo40, -1 ,nullptr }, // Inst #2784 = SUB64ri8
20480 { 2792, 3, 1, 0, 1, 0|(1ULL<<MCID::Compare)|(1ULL<<MCID::ConvertibleTo3Addr), 0x200002003dULL, nullptr, ImplicitList1, OperandInfo42, -1 ,nullptr }, // Inst #2792 = SUB8ri
21122 { 3434, 8, 1, 0, 1182, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x1034678004821ULL, nullptr, nullptr, OperandInfo425, -1 ,nullptr }, // Inst #3434 = VBROADCASTSDZ256mk
21128 { 3440, 8, 1, 0, 1182, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x10a4678004821ULL, nullptr, nullptr, OperandInfo427, -1 ,nullptr }, // Inst #3440 = VBROADCASTSDZmk
21136 { 3448, 8, 1, 0, 1158, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x820634004821ULL, nullptr, nullptr, OperandInfo429, -1 ,nullptr }, // Inst #3448 = VBROADCASTSSZ128mk
21142 { 3454, 8, 1, 0, 1182, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x830634004821ULL, nullptr, nullptr, OperandInfo414, -1 ,nullptr }, // Inst #3454 = VBROADCASTSSZ256mk
21148 { 3460, 8, 1, 0, 1182, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x8a0634004821ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #3460 = VBROADCASTSSZmk
25270 { 7582, 8, 1, 0, 1159, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x2024a38002821ULL, nullptr, nullptr, OperandInfo496, -1 ,nullptr }, // Inst #7582 = VMOVAPDZ128rmk
25274 { 7586, 4, 1, 0, 213, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x2024a38002831ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #7586 = VMOVAPDZ128rrk
25281 { 7593, 8, 1, 0, 1185, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x4034a38002821ULL, nullptr, nullptr, OperandInfo425, -1 ,nullptr }, // Inst #7593 = VMOVAPDZ256rmk
25285 { 7597, 4, 1, 0, 456, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x4034a38002831ULL, nullptr, nullptr, OperandInfo482, -1 ,nullptr }, // Inst #7597 = VMOVAPDZ256rrk
25292 { 7604, 8, 1, 0, 1185, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a4a38002821ULL, nullptr, nullptr, OperandInfo427, -1 ,nullptr }, // Inst #7604 = VMOVAPDZrmk
25296 { 7608, 4, 1, 0, 456, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a4a38002831ULL, nullptr, nullptr, OperandInfo487, -1 ,nullptr }, // Inst #7608 = VMOVAPDZrrk
25311 { 7623, 8, 1, 0, 1159, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x2020a34002021ULL, nullptr, nullptr, OperandInfo429, -1 ,nullptr }, // Inst #7623 = VMOVAPSZ128rmk
25315 { 7627, 4, 1, 0, 213, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x2020a34002031ULL, nullptr, nullptr, OperandInfo432, -1 ,nullptr }, // Inst #7627 = VMOVAPSZ128rrk
25322 { 7634, 8, 1, 0, 1185, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x4030a34002021ULL, nullptr, nullptr, OperandInfo414, -1 ,nullptr }, // Inst #7634 = VMOVAPSZ256rmk
25326 { 7638, 4, 1, 0, 456, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x4030a34002031ULL, nullptr, nullptr, OperandInfo491, -1 ,nullptr }, // Inst #7638 = VMOVAPSZ256rrk
25333 { 7645, 8, 1, 0, 1185, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a0a34002021ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #7645 = VMOVAPSZrmk
25337 { 7649, 4, 1, 0, 456, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a0a34002031ULL, nullptr, nullptr, OperandInfo494, -1 ,nullptr }, // Inst #7649 = VMOVAPSZrrk
25376 { 7688, 8, 1, 0, 1161, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x2021bfc002821ULL, nullptr, nullptr, OperandInfo429, -1 ,nullptr }, // Inst #7688 = VMOVDQA32Z128rmk
25380 { 7692, 4, 1, 0, 190, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x2021bfc002831ULL, nullptr, nullptr, OperandInfo432, -1 ,nullptr }, // Inst #7692 = VMOVDQA32Z128rrk
25387 { 7699, 8, 1, 0, 1188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x4031bfc002821ULL, nullptr, nullptr, OperandInfo414, -1 ,nullptr }, // Inst #7699 = VMOVDQA32Z256rmk
25391 { 7703, 4, 1, 0, 462, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x4031bfc002831ULL, nullptr, nullptr, OperandInfo491, -1 ,nullptr }, // Inst #7703 = VMOVDQA32Z256rrk
25398 { 7710, 8, 1, 0, 1188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a1bfc002821ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #7710 = VMOVDQA32Zrmk
25402 { 7714, 4, 1, 0, 462, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a1bfc002831ULL, nullptr, nullptr, OperandInfo494, -1 ,nullptr }, // Inst #7714 = VMOVDQA32Zrrk
25409 { 7721, 8, 1, 0, 1161, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x2025bfc002821ULL, nullptr, nullptr, OperandInfo496, -1 ,nullptr }, // Inst #7721 = VMOVDQA64Z128rmk
25413 { 7725, 4, 1, 0, 190, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x2025bfc002831ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #7725 = VMOVDQA64Z128rrk
25420 { 7732, 8, 1, 0, 1188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x4035bfc002821ULL, nullptr, nullptr, OperandInfo425, -1 ,nullptr }, // Inst #7732 = VMOVDQA64Z256rmk
25424 { 7736, 4, 1, 0, 462, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x4035bfc002831ULL, nullptr, nullptr, OperandInfo482, -1 ,nullptr }, // Inst #7736 = VMOVDQA64Z256rrk
25431 { 7743, 8, 1, 0, 1188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a5bfc002821ULL, nullptr, nullptr, OperandInfo427, -1 ,nullptr }, // Inst #7743 = VMOVDQA64Zrmk
25435 { 7747, 4, 1, 0, 462, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a5bfc002831ULL, nullptr, nullptr, OperandInfo487, -1 ,nullptr }, // Inst #7747 = VMOVDQA64Zrrk
25450 { 7762, 8, 1, 0, 1161, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x2025bfc003821ULL, nullptr, nullptr, OperandInfo517, -1 ,nullptr }, // Inst #7762 = VMOVDQU16Z128rmk
25454 { 7766, 4, 1, 0, 190, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x2025bfc003831ULL, nullptr, nullptr, OperandInfo770, -1 ,nullptr }, // Inst #7766 = VMOVDQU16Z128rrk
25461 { 7773, 8, 1, 0, 1188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x4035bfc003821ULL, nullptr, nullptr, OperandInfo522, -1 ,nullptr }, // Inst #7773 = VMOVDQU16Z256rmk
25465 { 7777, 4, 1, 0, 462, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x4035bfc003831ULL, nullptr, nullptr, OperandInfo773, -1 ,nullptr }, // Inst #7777 = VMOVDQU16Z256rrk
25472 { 7784, 8, 1, 0, 1188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a5bfc003821ULL, nullptr, nullptr, OperandInfo776, -1 ,nullptr }, // Inst #7784 = VMOVDQU16Zrmk
25476 { 7788, 4, 1, 0, 462, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a5bfc003831ULL, nullptr, nullptr, OperandInfo778, -1 ,nullptr }, // Inst #7788 = VMOVDQU16Zrrk
25483 { 7795, 8, 1, 0, 1161, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x2021bfc003021ULL, nullptr, nullptr, OperandInfo429, -1 ,nullptr }, // Inst #7795 = VMOVDQU32Z128rmk
25487 { 7799, 4, 1, 0, 190, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x2021bfc003031ULL, nullptr, nullptr, OperandInfo432, -1 ,nullptr }, // Inst #7799 = VMOVDQU32Z128rrk
25494 { 7806, 8, 1, 0, 1188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x4031bfc003021ULL, nullptr, nullptr, OperandInfo414, -1 ,nullptr }, // Inst #7806 = VMOVDQU32Z256rmk
25498 { 7810, 4, 1, 0, 462, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x4031bfc003031ULL, nullptr, nullptr, OperandInfo491, -1 ,nullptr }, // Inst #7810 = VMOVDQU32Z256rrk
25505 { 7817, 8, 1, 0, 1188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a1bfc003021ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #7817 = VMOVDQU32Zrmk
25509 { 7821, 4, 1, 0, 462, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a1bfc003031ULL, nullptr, nullptr, OperandInfo494, -1 ,nullptr }, // Inst #7821 = VMOVDQU32Zrrk
25516 { 7828, 8, 1, 0, 1161, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x2025bfc003021ULL, nullptr, nullptr, OperandInfo496, -1 ,nullptr }, // Inst #7828 = VMOVDQU64Z128rmk
25520 { 7832, 4, 1, 0, 190, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x2025bfc003031ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #7832 = VMOVDQU64Z128rrk
25527 { 7839, 8, 1, 0, 1188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x4035bfc003021ULL, nullptr, nullptr, OperandInfo425, -1 ,nullptr }, // Inst #7839 = VMOVDQU64Z256rmk
25531 { 7843, 4, 1, 0, 462, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x4035bfc003031ULL, nullptr, nullptr, OperandInfo482, -1 ,nullptr }, // Inst #7843 = VMOVDQU64Z256rrk
25538 { 7850, 8, 1, 0, 1188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a5bfc003021ULL, nullptr, nullptr, OperandInfo427, -1 ,nullptr }, // Inst #7850 = VMOVDQU64Zrmk
25542 { 7854, 4, 1, 0, 462, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a5bfc003031ULL, nullptr, nullptr, OperandInfo487, -1 ,nullptr }, // Inst #7854 = VMOVDQU64Zrrk
25549 { 7861, 8, 1, 0, 1161, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x2021bfc003821ULL, nullptr, nullptr, OperandInfo781, -1 ,nullptr }, // Inst #7861 = VMOVDQU8Z128rmk
25553 { 7865, 4, 1, 0, 190, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x2021bfc003831ULL, nullptr, nullptr, OperandInfo783, -1 ,nullptr }, // Inst #7865 = VMOVDQU8Z128rrk
25560 { 7872, 8, 1, 0, 1188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x4031bfc003821ULL, nullptr, nullptr, OperandInfo786, -1 ,nullptr }, // Inst #7872 = VMOVDQU8Z256rmk
25564 { 7876, 4, 1, 0, 462, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x4031bfc003831ULL, nullptr, nullptr, OperandInfo788, -1 ,nullptr }, // Inst #7876 = VMOVDQU8Z256rrk
25571 { 7883, 8, 1, 0, 1188, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a1bfc003821ULL, nullptr, nullptr, OperandInfo791, -1 ,nullptr }, // Inst #7883 = VMOVDQU8Zrmk
25575 { 7887, 4, 1, 0, 462, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a1bfc003831ULL, nullptr, nullptr, OperandInfo793, -1 ,nullptr }, // Inst #7887 = VMOVDQU8Zrrk
25734 { 8046, 8, 1, 0, 1159, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x2024438002821ULL, nullptr, nullptr, OperandInfo496, -1 ,nullptr }, // Inst #8046 = VMOVUPDZ128rmk
25738 { 8050, 4, 1, 0, 213, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x2024438002831ULL, nullptr, nullptr, OperandInfo478, -1 ,nullptr }, // Inst #8050 = VMOVUPDZ128rrk
25745 { 8057, 8, 1, 0, 1185, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x4034438002821ULL, nullptr, nullptr, OperandInfo425, -1 ,nullptr }, // Inst #8057 = VMOVUPDZ256rmk
25749 { 8061, 4, 1, 0, 456, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x4034438002831ULL, nullptr, nullptr, OperandInfo482, -1 ,nullptr }, // Inst #8061 = VMOVUPDZ256rrk
25756 { 8068, 8, 1, 0, 1185, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a4438002821ULL, nullptr, nullptr, OperandInfo427, -1 ,nullptr }, // Inst #8068 = VMOVUPDZrmk
25760 { 8072, 4, 1, 0, 456, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a4438002831ULL, nullptr, nullptr, OperandInfo487, -1 ,nullptr }, // Inst #8072 = VMOVUPDZrrk
25775 { 8087, 8, 1, 0, 1159, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x2020434002021ULL, nullptr, nullptr, OperandInfo429, -1 ,nullptr }, // Inst #8087 = VMOVUPSZ128rmk
25779 { 8091, 4, 1, 0, 213, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x2020434002031ULL, nullptr, nullptr, OperandInfo432, -1 ,nullptr }, // Inst #8091 = VMOVUPSZ128rrk
25786 { 8098, 8, 1, 0, 1185, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x4030434002021ULL, nullptr, nullptr, OperandInfo414, -1 ,nullptr }, // Inst #8098 = VMOVUPSZ256rmk
25790 { 8102, 4, 1, 0, 456, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x4030434002031ULL, nullptr, nullptr, OperandInfo491, -1 ,nullptr }, // Inst #8102 = VMOVUPSZ256rrk
25797 { 8109, 8, 1, 0, 1185, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a0434002021ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #8109 = VMOVUPSZrmk
25801 { 8113, 4, 1, 0, 456, 0|(1ULL<<MCID::ConvertibleTo3Addr), 0x80a0434002031ULL, nullptr, nullptr, OperandInfo494, -1 ,nullptr }, // Inst #8113 = VMOVUPSZrrk
26736 { 9048, 8, 1, 0, 1157, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x82163c004821ULL, nullptr, nullptr, OperandInfo429, -1 ,nullptr }, // Inst #9048 = VPBROADCASTDZ128mk
26742 { 9054, 8, 1, 0, 1180, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x83163c004821ULL, nullptr, nullptr, OperandInfo414, -1 ,nullptr }, // Inst #9054 = VPBROADCASTDZ256mk
26748 { 9060, 8, 1, 0, 1180, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x8a163c004821ULL, nullptr, nullptr, OperandInfo420, -1 ,nullptr }, // Inst #9060 = VPBROADCASTDZmk
26773 { 9085, 8, 1, 0, 1157, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x102567c004821ULL, nullptr, nullptr, OperandInfo496, -1 ,nullptr }, // Inst #9085 = VPBROADCASTQZ128mk
26779 { 9091, 8, 1, 0, 1180, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x103567c004821ULL, nullptr, nullptr, OperandInfo425, -1 ,nullptr }, // Inst #9091 = VPBROADCASTQZ256mk
26785 { 9097, 8, 1, 0, 1180, 0|(1ULL<<MCID::MayLoad)|(1ULL<<MCID::ConvertibleTo3Addr), 0x10a567c004821ULL, nullptr, nullptr, OperandInfo427, -1 ,nullptr }, // Inst #9097 = VPBROADCASTQZmk
include/llvm/CodeGen/MachineInstr.h 927 return hasProperty(MCID::ConvertibleTo3Addr, Type);
include/llvm/MC/MCInstrDesc.h 478 return Flags & (1ULL << MCID::ConvertibleTo3Addr);