reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenInstrInfo.inc
 8600   { 2767,	4,	1,	4,	574,	0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Predicable), 0x18900ULL, nullptr, nullptr, OperandInfo379, -1 ,nullptr },  // Inst #2767 = VMOVRS
 8602   { 2769,	4,	1,	4,	575,	0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Predicable), 0x18a00ULL, nullptr, nullptr, OperandInfo380, -1 ,nullptr },  // Inst #2769 = VMOVSR
gen/lib/Target/Mips/MipsGenInstrInfo.inc
 6096   { 1281,	2,	1,	4,	1328,	0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo221, -1 ,nullptr },  // Inst #1281 = DMFC1
 6104   { 1289,	2,	1,	4,	1329,	0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo123, -1 ,nullptr },  // Inst #1289 = DMTC1
 6691   { 1876,	2,	1,	4,	687,	0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #1876 = MFC1
 6693   { 1878,	2,	1,	4,	1255,	0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #1878 = MFC1_MM
 6694   { 1879,	2,	1,	4,	1300,	0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, nullptr, OperandInfo110, -1 ,nullptr },  // Inst #1879 = MFC1_MMR6
 6834   { 2019,	2,	1,	4,	678,	0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #2019 = MTC1
 6837   { 2022,	2,	1,	4,	1257,	0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x4ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #2022 = MTC1_MM
 6838   { 2023,	2,	1,	4,	1301,	0|(1ULL<<MCID::Bitcast), 0x6ULL, nullptr, nullptr, OperandInfo118, -1 ,nullptr },  // Inst #2023 = MTC1_MMR6
gen/lib/Target/NVPTX/NVPTXGenInstrInfo.inc
 6845   { 214,	2,	1,	0,	0,	0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo58, -1 ,nullptr },  // Inst #214 = BITCONVERT_16_F2I
 6846   { 215,	2,	1,	0,	0,	0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo59, -1 ,nullptr },  // Inst #215 = BITCONVERT_16_I2F
 6847   { 216,	2,	1,	0,	0,	0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo60, -1 ,nullptr },  // Inst #216 = BITCONVERT_32_F16x22I
 6848   { 217,	2,	1,	0,	0,	0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo61, -1 ,nullptr },  // Inst #217 = BITCONVERT_32_F2I
 6849   { 218,	2,	1,	0,	0,	0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo62, -1 ,nullptr },  // Inst #218 = BITCONVERT_32_I2F
 6850   { 219,	2,	1,	0,	0,	0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo63, -1 ,nullptr },  // Inst #219 = BITCONVERT_32_I2F16x2
 6851   { 220,	2,	1,	0,	0,	0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo64, -1 ,nullptr },  // Inst #220 = BITCONVERT_64_F2I
 6852   { 221,	2,	1,	0,	0,	0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, nullptr, OperandInfo65, -1 ,nullptr },  // Inst #221 = BITCONVERT_64_I2F
gen/lib/Target/PowerPC/PPCGenInstrInfo.inc
 5093   { 2185,	1,	1,	4,	97,	0|(1ULL<<MCID::MoveImm)|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::Rematerializable)|(1ULL<<MCID::CheapAsAMove), 0x0ULL, nullptr, nullptr, OperandInfo296, -1 ,nullptr },  // Inst #2185 = XXLEQVOnes
gen/lib/Target/SystemZ/SystemZGenInstrInfo.inc
 5690   { 1370,	2,	1,	4,	343,	0|(1ULL<<MCID::Bitcast), 0x0ULL, nullptr, nullptr, OperandInfo138, -1 ,nullptr },  // Inst #1370 = LDGR
 5716   { 1396,	2,	1,	4,	344,	0|(1ULL<<MCID::Bitcast), 0x0ULL, nullptr, nullptr, OperandInfo199, -1 ,nullptr },  // Inst #1396 = LGDR
gen/lib/Target/WebAssembly/WebAssemblyGenInstrInfo.inc
 2187   { 632,	2,	1,	0,	0,	0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo122, -1 ,nullptr },  // Inst #632 = F32_REINTERPRET_I32
 2199   { 644,	2,	1,	0,	0,	0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo126, -1 ,nullptr },  // Inst #644 = F64_REINTERPRET_I64
 2307   { 752,	2,	1,	0,	0,	0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo128, -1 ,nullptr },  // Inst #752 = I32_REINTERPRET_F32
 2337   { 782,	2,	1,	0,	0,	0|(1ULL<<MCID::Bitcast)|(1ULL<<MCID::ExtraSrcRegAllocReq)|(1ULL<<MCID::ExtraDefRegAllocReq), 0x0ULL, nullptr, ImplicitList1, OperandInfo131, -1 ,nullptr },  // Inst #782 = I64_REINTERPRET_F64
gen/lib/Target/X86/X86GenInstrInfo.inc
19154   { 1466,	2,	1,	0,	187,	0|(1ULL<<MCID::Bitcast), 0x1f80012030ULL, nullptr, nullptr, OperandInfo252, -1 ,nullptr },  // Inst #1466 = MMX_MOVD64from64rr
19160   { 1472,	2,	1,	0,	189,	0|(1ULL<<MCID::Bitcast), 0x1b80012031ULL, nullptr, nullptr, OperandInfo255, -1 ,nullptr },  // Inst #1472 = MMX_MOVD64to64rr
19168   { 1480,	2,	1,	0,	192,	0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x1bc0002031ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr },  // Inst #1480 = MMX_MOVQ64rr
19169   { 1481,	2,	1,	0,	192,	0|(1ULL<<MCID::MoveReg)|(1ULL<<MCID::Bitcast), 0x1fc0002030ULL, nullptr, nullptr, OperandInfo250, -1 ,nullptr },  // Inst #1481 = MMX_MOVQ64rr_REV
19386   { 1698,	2,	1,	0,	189,	0|(1ULL<<MCID::Bitcast), 0x1b8c012831ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #1698 = MOV64toSDrr
19421   { 1733,	2,	1,	0,	189,	0|(1ULL<<MCID::Bitcast), 0x1b8c002831ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr },  // Inst #1733 = MOVDI2SSrr
19469   { 1781,	2,	1,	0,	187,	0|(1ULL<<MCID::Bitcast), 0x1f8c012830ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr },  // Inst #1781 = MOVSDto64rr
19476   { 1788,	2,	1,	0,	187,	0|(1ULL<<MCID::Bitcast), 0x1f8c002830ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr },  // Inst #1788 = MOVSS2DIrr
25261   { 7573,	2,	1,	0,	189,	0|(1ULL<<MCID::Bitcast), 0x2005bbc002831ULL, nullptr, nullptr, OperandInfo765, -1 ,nullptr },  // Inst #7573 = VMOV64toSDZrr
25262   { 7574,	2,	1,	0,	189,	0|(1ULL<<MCID::Bitcast), 0x5b9c002831ULL, nullptr, nullptr, OperandInfo182, -1 ,nullptr },  // Inst #7574 = VMOV64toSDrr
25371   { 7683,	2,	1,	0,	189,	0|(1ULL<<MCID::Bitcast), 0x2001bbc002831ULL, nullptr, nullptr, OperandInfo768, -1 ,nullptr },  // Inst #7683 = VMOVDI2SSZrr
25372   { 7684,	2,	1,	0,	189,	0|(1ULL<<MCID::Bitcast), 0x1b9c002831ULL, nullptr, nullptr, OperandInfo181, -1 ,nullptr },  // Inst #7684 = VMOVDI2SSrr
25662   { 7974,	2,	1,	0,	189,	0|(1ULL<<MCID::Bitcast), 0x2005fbc002830ULL, nullptr, nullptr, OperandInfo581, -1 ,nullptr },  // Inst #7974 = VMOVSDto64Zrr
25663   { 7975,	2,	1,	0,	187,	0|(1ULL<<MCID::Bitcast), 0x5f9c002830ULL, nullptr, nullptr, OperandInfo186, -1 ,nullptr },  // Inst #7975 = VMOVSDto64rr
25708   { 8020,	2,	1,	0,	187,	0|(1ULL<<MCID::Bitcast), 0x2001fbc002830ULL, nullptr, nullptr, OperandInfo584, -1 ,nullptr },  // Inst #8020 = VMOVSS2DIZrr
25709   { 8021,	2,	1,	0,	187,	0|(1ULL<<MCID::Bitcast), 0x1f9c002830ULL, nullptr, nullptr, OperandInfo189, -1 ,nullptr },  // Inst #8021 = VMOVSS2DIrr
include/llvm/CodeGen/MachineInstr.h
  761     return hasProperty(MCID::Bitcast, Type);
include/llvm/MC/MCInstrDesc.h
  337   bool isBitcast() const { return Flags & (1ULL << MCID::Bitcast); }