reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
301 .addReg(AArch64::X16) 302 .addReg(Reg) 307 .addReg(AArch64::W16) 308 .addReg(AArch64::X9) 309 .addReg(AArch64::X16) 315 .addReg(AArch64::XZR) 316 .addReg(AArch64::X16) 317 .addReg(Reg) 330 MCInstBuilder(AArch64::RET).addReg(AArch64::LR), *STI); 335 .addReg(AArch64::WZR) 336 .addReg(AArch64::W16) 349 .addReg(AArch64::X17) 350 .addReg(Reg) 356 .addReg(AArch64::X17) 357 .addReg(AArch64::X17) 362 .addReg(AArch64::WZR) 363 .addReg(AArch64::W16) 364 .addReg(AArch64::W17) 375 .addReg(AArch64::X16) 376 .addReg(Reg) 380 .addReg(AArch64::W16) 381 .addReg(AArch64::X16) 386 .addReg(AArch64::XZR) 387 .addReg(AArch64::X16) 388 .addReg(Reg) 401 .addReg(AArch64::SP) 402 .addReg(AArch64::X0) 403 .addReg(AArch64::X1) 404 .addReg(AArch64::SP) 408 .addReg(AArch64::FP) 409 .addReg(AArch64::LR) 410 .addReg(AArch64::SP) 416 .addReg(AArch64::X0) 417 .addReg(AArch64::XZR) 418 .addReg(Reg) 422 .addReg(AArch64::X1) 432 .addReg(AArch64::X16) 439 .addReg(AArch64::X16) 440 .addReg(AArch64::X16) 446 MCInstBuilder(AArch64::BR).addReg(AArch64::X16), *STI); 771 .addReg(DestReg) 778 .addReg(ScratchRegW) 779 .addReg(TableReg) 780 .addReg(EntryReg) 787 .addReg(DestReg) 788 .addReg(DestReg) 789 .addReg(ScratchReg) 836 .addReg(ScratchReg) 840 .addReg(ScratchReg) 841 .addReg(ScratchReg) 845 .addReg(ScratchReg) 846 .addReg(ScratchReg) 849 EmitToStreamer(OutStreamer, MCInstBuilder(AArch64::BLR).addReg(ScratchReg)); 1074 .addReg(ScratchReg) 1075 .addReg(TableReg) 1076 .addReg(EntryReg) 1080 .addReg(DestReg) 1081 .addReg(TableReg) 1082 .addReg(ScratchReg)lib/Target/ARM/ARMAsmPrinter.cpp
175 .addReg(TIP.first) 178 .addReg(0)); 1007 .addReg(0)); 1279 .addReg(MI->getOperand(0).getReg()) 1283 .addReg(MI->getOperand(3).getReg())); 1295 .addReg(MI->getOperand(0).getReg()) 1299 .addReg(MI->getOperand(3).getReg())); 1306 .addReg(ARM::LR) 1307 .addReg(ARM::PC) 1310 .addReg(0) 1312 .addReg(0)); 1316 .addReg(MI->getOperand(0).getReg())); 1346 .addImm(ARMCC::AL).addReg(0) 1352 .addReg(ARM::LR) 1353 .addReg(ARM::PC) 1356 .addReg(0) 1358 .addReg(0)); 1361 .addReg(ARM::PC) 1362 .addReg(MI->getOperand(0).getReg()) 1365 .addReg(0) 1367 .addReg(0)); 1372 .addReg(ARM::LR) 1373 .addReg(ARM::PC) 1376 .addReg(0) 1378 .addReg(0)); 1389 .addReg(0)); 1470 MCInst.addReg(MI->getOperand(1).getReg()); 1500 .addReg(MI->getOperand(3).getReg()); 1528 .addReg(MI->getOperand(0).getReg()) 1529 .addReg(MI->getOperand(0).getReg()) 1530 .addReg(ARM::PC) 1533 .addReg(0)); 1549 .addReg(MI->getOperand(0).getReg()) 1550 .addReg(ARM::PC) 1551 .addReg(MI->getOperand(1).getReg()) 1554 .addReg(MI->getOperand(4).getReg()) 1556 .addReg(0)); 1593 .addReg(MI->getOperand(0).getReg()) 1594 .addReg(ARM::PC) 1595 .addReg(MI->getOperand(1).getReg()) 1599 .addReg(MI->getOperand(4).getReg())); 1642 .addReg(ARM::PC) 1643 .addReg(MI->getOperand(0).getReg()) 1646 .addReg(0)); 1655 .addReg(MI->getOperand(0).getReg()) 1656 .addReg(MI->getOperand(1).getReg()) 1659 .addReg(0)); 1673 .addReg(Idx) 1674 .addReg(ARM::CPSR) 1675 .addReg(Idx) 1679 .addReg(0)); 1697 .addReg(Idx) 1698 .addReg(Idx) 1699 .addReg(Base) 1702 .addReg(0)); 1706 .addReg(Idx) 1707 .addReg(Idx) 1711 .addReg(0)); 1720 .addReg(Idx) 1721 .addReg(Base) 1722 .addReg(Idx) 1725 .addReg(0)); 1729 .addReg(Idx) 1730 .addReg(ARM::CPSR) 1731 .addReg(Idx) 1735 .addReg(0)); 1739 .addReg(ARM::PC) 1740 .addReg(ARM::PC) 1741 .addReg(Idx) 1744 .addReg(0)); 1795 .addReg(ARM::PC) 1796 .addReg(MI->getOperand(0).getReg()) 1797 .addReg(MI->getOperand(1).getReg()) 1800 .addReg(0) 1802 .addReg(0)); 1852 .addReg(ValReg) 1853 .addReg(ARM::PC) 1856 .addReg(0)); 1859 .addReg(ValReg) 1861 .addReg(ARM::CPSR) 1862 .addReg(ValReg) 1866 .addReg(0)); 1869 .addReg(ValReg) 1870 .addReg(SrcReg) 1876 .addReg(0)); 1879 .addReg(ARM::R0) 1880 .addReg(ARM::CPSR) 1884 .addReg(0)); 1890 .addReg(0)); 1894 .addReg(ARM::R0) 1895 .addReg(ARM::CPSR) 1899 .addReg(0)); 1918 .addReg(ValReg) 1919 .addReg(ARM::PC) 1923 .addReg(0) 1925 .addReg(0)); 1928 .addReg(ValReg) 1929 .addReg(SrcReg) 1933 .addReg(0)); 1936 .addReg(ARM::R0) 1940 .addReg(0) 1942 .addReg(0)); 1945 .addReg(ARM::PC) 1946 .addReg(ARM::PC) 1950 .addReg(0) 1952 .addReg(0)); 1956 .addReg(ARM::R0) 1960 .addReg(0) 1962 .addReg(0)); 1973 .addReg(ARM::SP) 1974 .addReg(SrcReg) 1978 .addReg(0)); 1981 .addReg(ScratchReg) 1982 .addReg(SrcReg) 1986 .addReg(0)); 1991 .addReg(FramePtr) 1992 .addReg(SrcReg) 1996 .addReg(0)); 2001 .addReg(ARM::R7) 2002 .addReg(SrcReg) 2006 .addReg(0)); 2008 .addReg(ARM::R11) 2009 .addReg(SrcReg) 2013 .addReg(0)); 2018 .addReg(ScratchReg) 2021 .addReg(0)); 2034 .addReg(ScratchReg) 2035 .addReg(SrcReg) 2041 .addReg(0)); 2044 .addReg(ARM::SP) 2045 .addReg(ScratchReg) 2048 .addReg(0)); 2051 .addReg(ScratchReg) 2052 .addReg(SrcReg) 2056 .addReg(0)); 2061 .addReg(FramePtr) 2062 .addReg(SrcReg) 2066 .addReg(0)); 2071 .addReg(ARM::R7) 2072 .addReg(SrcReg) 2076 .addReg(0)); 2078 .addReg(ARM::R11) 2079 .addReg(SrcReg) 2083 .addReg(0)); 2087 .addReg(ScratchReg) 2090 .addReg(0)); 2101 .addReg(ARM::R11) 2102 .addReg(SrcReg) 2106 .addReg(0)); 2108 .addReg(ARM::SP) 2109 .addReg(SrcReg) 2113 .addReg(0)); 2115 .addReg(ARM::PC) 2116 .addReg(SrcReg) 2120 .addReg(0));lib/Target/ARM/ARMMCInstLower.cpp
208 .addImm(ARMCC::AL).addReg(0));
lib/Target/Lanai/LanaiAsmPrinter.cpp159 .addReg(Lanai::RCA) 160 .addReg(Lanai::PC) 167 .addReg(Lanai::RCA) 168 .addReg(Lanai::SP) 181 .addReg(Lanai::PC) 182 .addReg(MI->getOperand(0).getReg()) 183 .addReg(Lanai::R0)lib/Target/Mips/MipsAsmPrinter.cpp
1210 .addReg(Mips::ZERO) 1211 .addReg(Mips::ZERO) 1216 .addReg(Mips::ZERO) 1217 .addReg(Mips::ZERO) 1225 .addReg(Mips::T9) 1226 .addReg(Mips::T9)lib/Target/PowerPC/PPCAsmPrinter.cpp
395 .addReg(ScratchReg) 399 .addReg(ScratchReg) 400 .addReg(ScratchReg) 404 .addReg(ScratchReg) 405 .addReg(ScratchReg) 409 .addReg(ScratchReg) 410 .addReg(ScratchReg) 416 .addReg(PPC::X2) 418 .addReg(PPC::X1)); 428 .addReg(PPC::X2) 430 .addReg(ScratchReg)); 433 .addReg(ScratchReg) 435 .addReg(ScratchReg)); 440 .addReg(ScratchReg)); 447 .addReg(PPC::X2) 449 .addReg(PPC::X1)); 642 MCInstBuilder(PPC::ADDIS).addReg(PICR).addReg(PICR).addExpr(DeltaHi)); 642 MCInstBuilder(PPC::ADDIS).addReg(PICR).addReg(PICR).addExpr(DeltaHi)); 647 MCInstBuilder(PPC::ADDI).addReg(PICR).addReg(PICR).addExpr(DeltaLo)); 647 MCInstBuilder(PPC::ADDI).addReg(PICR).addReg(PICR).addExpr(DeltaLo)); 931 .addReg(MI->getOperand(0).getReg()) 932 .addReg(MI->getOperand(1).getReg()) 972 .addReg(MI->getOperand(0).getReg())); 974 .addReg(MI->getOperand(1).getReg()) 976 .addReg(MI->getOperand(0).getReg())); 978 .addReg(MI->getOperand(0).getReg()) 979 .addReg(MI->getOperand(1).getReg()) 980 .addReg(MI->getOperand(0).getReg())); 991 .addReg(MI->getOperand(0).getReg()) 994 .addReg(MI->getOperand(0).getReg()) 995 .addReg(MI->getOperand(0).getReg()) 1010 .addReg(MI->getOperand(0).getReg()) 1011 .addReg(MI->getOperand(1).getReg()) 1030 .addReg(MI->getOperand(0).getReg()) 1031 .addReg(MI->getOperand(1).getReg()) 1055 .addReg(MI->getOperand(0).getReg()) 1056 .addReg(MI->getOperand(1).getReg()) 1075 .addReg(MI->getOperand(0).getReg()) 1076 .addReg(MI->getOperand(1).getReg()) 1104 .addReg(MI->getOperand(0).getReg()) 1105 .addReg(MI->getOperand(1).getReg()) 1123 .addReg(MI->getOperand(0).getReg()) 1124 .addReg(MI->getOperand(1).getReg()) 1138 .addReg(MI->getOperand(0).getReg())); 1155 .addReg(MI->getOperand(1).getReg())); 1212 MCInstBuilder(PPC::STD).addReg(PPC::X0).addImm(-8).addReg(PPC::X1)); 1212 MCInstBuilder(PPC::STD).addReg(PPC::X0).addImm(-8).addReg(PPC::X1)); 1213 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MFLR8).addReg(PPC::X0)); 1219 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MTLR8).addReg(PPC::X0)); 1274 .addReg(MI->getOperand(2).getReg()) 1298 MCInstBuilder(PPC::STD).addReg(PPC::X0).addImm(-8).addReg(PPC::X1)); 1298 MCInstBuilder(PPC::STD).addReg(PPC::X0).addImm(-8).addReg(PPC::X1)); 1299 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MFLR8).addReg(PPC::X0)); 1305 EmitToStreamer(*OutStreamer, MCInstBuilder(PPC::MTLR8).addReg(PPC::X0)); 1522 .addReg(PPC::X2) 1523 .addReg(PPC::X12) 1529 .addReg(PPC::X2) 1530 .addReg(PPC::X2) 1539 .addReg(PPC::X2) 1541 .addReg(PPC::X12)); 1543 .addReg(PPC::X2) 1544 .addReg(PPC::X2) 1545 .addReg(PPC::X12));lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
1603 Out, MCInstBuilder(RISCV::LUI).addReg(DestReg).addImm(Inst.Imm)); 1606 Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addImm( 1606 Out, MCInstBuilder(Inst.Opc).addReg(DestReg).addReg(SrcReg).addImm( 1759 .addReg(Reg) 1760 .addReg(RISCV::X0)lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp
123 .addReg(Ra) 130 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); 130 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0); 133 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0); 133 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);lib/Target/SystemZ/SystemZAsmPrinter.cpp
34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) 38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) 39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) 48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) 52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) 53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) 61 .addReg(MI->getOperand(0).getReg()) 62 .addReg(MI->getOperand(1).getReg()) 63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())) 108 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) 109 .addReg(MI->getOperand(1).getReg()) 111 .addReg(MI->getOperand(3).getReg()); 118 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) 119 .addReg(MI->getOperand(1).getReg()) 121 .addReg(MI->getOperand(3).getReg()) 130 LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R14D); 137 .addReg(SystemZ::R14D); 142 .addReg(MI->getOperand(0).getReg()) 143 .addReg(MI->getOperand(1).getReg()) 145 .addReg(SystemZ::R14D) 151 .addReg(MI->getOperand(0).getReg()) 152 .addReg(MI->getOperand(1).getReg()) 154 .addReg(SystemZ::R14D) 160 .addReg(MI->getOperand(0).getReg()) 163 .addReg(SystemZ::R14D) 169 .addReg(MI->getOperand(0).getReg()) 172 .addReg(SystemZ::R14D) 178 .addReg(MI->getOperand(0).getReg()) 179 .addReg(MI->getOperand(1).getReg()) 181 .addReg(SystemZ::R14D) 187 .addReg(MI->getOperand(0).getReg()) 188 .addReg(MI->getOperand(1).getReg()) 190 .addReg(SystemZ::R14D) 196 .addReg(MI->getOperand(0).getReg()) 199 .addReg(SystemZ::R14D) 205 .addReg(MI->getOperand(0).getReg()) 208 .addReg(SystemZ::R14D) 214 .addReg(SystemZ::R14D) 220 .addReg(SystemZ::R14D) 221 .addReg(MI->getOperand(0).getReg()); 237 LoweredMI = MCInstBuilder(SystemZ::BR).addReg(SystemZ::R1D); 244 .addReg(SystemZ::R1D); 249 .addReg(MI->getOperand(0).getReg()) 250 .addReg(MI->getOperand(1).getReg()) 252 .addReg(SystemZ::R1D) 258 .addReg(MI->getOperand(0).getReg()) 259 .addReg(MI->getOperand(1).getReg()) 261 .addReg(SystemZ::R1D) 267 .addReg(MI->getOperand(0).getReg()) 270 .addReg(SystemZ::R1D) 276 .addReg(MI->getOperand(0).getReg()) 279 .addReg(SystemZ::R1D) 285 .addReg(MI->getOperand(0).getReg()) 286 .addReg(MI->getOperand(1).getReg()) 288 .addReg(SystemZ::R1D) 294 .addReg(MI->getOperand(0).getReg()) 295 .addReg(MI->getOperand(1).getReg()) 297 .addReg(SystemZ::R1D) 303 .addReg(MI->getOperand(0).getReg()) 306 .addReg(SystemZ::R1D) 312 .addReg(MI->getOperand(0).getReg()) 315 .addReg(SystemZ::R1D) 321 .addReg(SystemZ::R14D) 328 .addReg(SystemZ::R14D) 335 .addReg(MI->getOperand(0).getReg()) 341 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) 347 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) 363 .addReg(MI->getOperand(0).getReg()) 364 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(1).getReg())) 365 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg())); 371 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) 372 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg())); 413 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(0).getReg())) 414 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg())) 415 .addReg(0).addImm(0); 420 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) 421 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg())) 422 .addReg(MI->getOperand(1).getReg()) 423 .addReg(0).addImm(0); 463 .addImm(14).addReg(SystemZ::R0D); 466 .addImm(15).addReg(SystemZ::R0D); 534 .addImm(0).addReg(SystemZ::R0D), STI); 539 .addImm(0).addReg(0).addImm(0).addReg(0), 539 .addImm(0).addReg(0).addImm(0).addReg(0), 566 .addReg(SystemZ::R0D).addExpr(Op), getSubtargetInfo()); 622 .addReg(ScratchReg) 627 .addReg(ScratchReg) 633 .addReg(SystemZ::R14D) 634 .addReg(ScratchReg)); 640 .addReg(SystemZ::R14D)lib/Target/X86/X86MCInstLower.cpp
920 .addReg(X86::RDI) 921 .addReg(X86::RIP) 923 .addReg(0) 925 .addReg(0)); 937 .addReg(X86::RIP) 939 .addReg(0) 941 .addReg(0)); 951 .addReg(X86::EAX) 952 .addReg(0) 954 .addReg(X86::EBX) 956 .addReg(0)); 959 .addReg(X86::EAX) 960 .addReg(X86::EBX) 962 .addReg(0) 964 .addReg(0)); 972 .addReg(X86::EBX) 974 .addReg(0) 976 .addReg(0)); 1069 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX), STI); 1069 OS.EmitInstruction(MCInstBuilder(Opc).addReg(X86::AX).addReg(X86::AX), STI); 1074 .addReg(BaseReg) 1076 .addReg(IndexReg) 1078 .addReg(SegmentReg), 1287 MCInstBuilder(X86::MOV64ri).addReg(ScratchReg).addOperand(CalleeMCOp)); 1292 EmitAndCountInstruction(MCInstBuilder(X86::CALL64r).addReg(ScratchReg)); 1357 MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I])); 1370 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); 1370 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); 1386 EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I])); 1453 MCInstBuilder(X86::PUSH64r).addReg(DestRegs[I])); 1471 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); 1471 MCInstBuilder(X86::MOV64rr).addReg(DestRegs[I]).addReg(SrcRegs[I])); 1487 EmitAndCountInstruction(MCInstBuilder(X86::POP64r).addReg(DestRegs[I])); 1907 MIB.addReg(Reg0); 1916 MIB.addReg(Reg1); 1940 MIB.addReg(Reg0); 1953 MIB.addReg(Reg1); 1992 MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg())); 2027 .addReg(MI->getOperand(0).getReg()) 2028 .addReg(MI->getOperand(1).getReg()) 2073 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX)); 2073 MCInstBuilder(X86::MOV64rr).addReg(X86::R10).addReg(X86::RAX));tools/llvm-exegesis/lib/AArch64/Target.cpp
32 .addReg(Reg)
tools/llvm-exegesis/lib/Mips/Target.cpp41 .addReg(Reg) 42 .addReg(Mips::ZERO)tools/llvm-exegesis/lib/PowerPC/Target.cpp
49 .addReg(Reg)
tools/llvm-exegesis/lib/X86/Target.cpp381 .addReg(Reg) 388 .addReg(X86::RSP) 389 .addReg(X86::RSP) 398 .addReg(X86::RSP) // BaseReg 400 .addReg(0) // IndexReg 402 .addReg(0) // Segment 410 .addReg(Reg) 412 .addReg(X86::RSP) // BaseReg 414 .addReg(0) // IndexReg 416 .addReg(0); // Segment 422 .addReg(X86::RSP) 423 .addReg(X86::RSP) 471 .addReg(X86::RSP) // BaseReg 473 .addReg(0) // IndexReg 475 .addReg(0)); // Segment 477 add(MCInstBuilder(X86::ST_Frr).addReg(Reg)); 485 .addReg(Reg) 487 .addReg(X86::RSP) // BaseReg 489 .addReg(0) // IndexReg 491 .addReg(0)); // Segmentunittests/tools/llvm-exegesis/ARM/AssemblerTest.cpp
37 .addReg(ARM::R0) 38 .addReg(ARM::R0) 39 .addReg(ARM::R0) 41 .addReg(0) 42 .addReg(0),unittests/tools/llvm-exegesis/X86/AssemblerTest.cpp
46 MCInstBuilder(XOR32rr).addReg(EAX).addReg(EAX).addReg(EAX), 46 MCInstBuilder(XOR32rr).addReg(EAX).addReg(EAX).addReg(EAX), 46 MCInstBuilder(XOR32rr).addReg(EAX).addReg(EAX).addReg(EAX), 54 Check({}, MCInstBuilder(MOV64ri32).addReg(RAX).addImm(42), 0x48, 0xc7, 0xc0, 59 Check({}, MCInstBuilder(MOV32ri).addReg(EAX).addImm(42), 0xb8, 0x2a, 0x00,unittests/tools/llvm-exegesis/X86/BenchmarkResultTest.cpp
67 .addReg(X86::AL) 68 .addReg(X86::AH)unittests/tools/llvm-exegesis/X86/TargetTest.cpp
302 const MCInst CopySt0ToSt1 = MCInstBuilder(X86::ST_Frr).addReg(X86::ST1);