reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
 4833     Inst.getOperand(OperandIdx[2]).setReg(AMDGPU::NoRegister);
 4834     Inst.getOperand(OperandIdx[3]).setReg(AMDGPU::NoRegister);
lib/Target/ARM/Disassembler/ARMDisassembler.cpp
  898         I->setReg(0);
  900         I->setReg(ARM::CPSR);
lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp
 1383     MO.setReg(matchRegister(Reg1));
 1398     MO.setReg(matchRegister(Reg1));
 1414     MO.setReg(matchRegister(Reg1));
 1430     MO.setReg(MatchRegisterName(R1));
 1746       Rss.setReg(matchRegister(Reg1));
 1772       Rs.setReg(matchRegister(RegPair));
 1777       Rs.setReg(matchRegister(RegPair));
 1789       Rs.setReg(matchRegister(RegPair));
 1794       Rs.setReg(matchRegister(RegPair));
 1806       Rt.setReg(matchRegister(RegPair));
 1811       Rt.setReg(matchRegister(RegPair));
 1826       Rt.setReg(matchRegister(RegPair));
 1831       Rt.setReg(matchRegister(RegPair));
 1849       Rt.setReg(matchRegister(RegPair));
 1854       Rt.setReg(matchRegister(RegPair));
 1890       Rss.setReg(matchRegister(Reg1));
lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp
  495       MCO.setReg(Producer);
  506       MCO.setReg(Producer);
lib/Target/Hexagon/HexagonAsmPrinter.cpp
  381     Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
  392     Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
  404     Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
  416     Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI));
  542     MO.setReg(High);
  554     MO.setReg(High);
  568     MO.setReg(High);
  601     Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI));
lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp
  113         Instr.getOperand(2).setReg(Lanai::R0);
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp
  116   Inst.getOperand(0).setReg(RegOp1);
  117   Inst.getOperand(1).setReg(RegOp0);