|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenAsmWriter.inc11739 Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0;
11740 Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32;
14803 switch (MI->getOpcode()) {
gen/lib/Target/AArch64/AArch64GenAsmWriter1.inc12736 Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0;
12737 Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32;
15519 switch (MI->getOpcode()) {
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc29742 switch(MI.getOpcode()) {
29803 switch(MI.getOpcode()) {
29829 switch(MI.getOpcode()) {
29886 switch(MI.getOpcode()) {
29937 switch(MI.getOpcode()) {
29963 switch(MI.getOpcode()) {
30019 switch(MI.getOpcode()) {
30050 switch(MI.getOpcode()) {
30070 switch(MI.getOpcode()) {
30087 switch(MI.getOpcode()) {
30107 switch(MI.getOpcode()) {
30139 switch(MI.getOpcode()) {
gen/lib/Target/AArch64/AArch64GenMCCodeEmitter.inc 5399 const unsigned opcode = MI.getOpcode();
21325 assert(Inst.getOpcode() < 5384);
21326 const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]];
21332 Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str()
gen/lib/Target/AArch64/AArch64GenSubtargetInfo.inc13043 MI->getOpcode() == AArch64::EXTRWrri
13044 || MI->getOpcode() == AArch64::EXTRXrri
13054 MI->getOpcode() == AArch64::EXTRWrri
13055 || MI->getOpcode() == AArch64::EXTRXrri
13450 ( MI->getOpcode() == AArch64::BLR )
13458 ( MI->getOpcode() == AArch64::BLR )
13466 ( MI->getOpcode() == AArch64::BLR )
13518 MI->getOpcode() == AArch64::EXTRWrri
13519 || MI->getOpcode() == AArch64::EXTRXrri
13529 MI->getOpcode() == AArch64::EXTRWrri
13530 || MI->getOpcode() == AArch64::EXTRXrri
13542 MI->getOpcode() == AArch64::EXTRWrri
13543 || MI->getOpcode() == AArch64::EXTRXrri
13553 MI->getOpcode() == AArch64::EXTRWrri
13554 || MI->getOpcode() == AArch64::EXTRXrri
gen/lib/Target/AMDGPU/AMDGPUGenAsmWriter.inc32457 Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0;
32458 Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32;
33743 switch (MI->getOpcode()) {
gen/lib/Target/AMDGPU/AMDGPUGenMCCodeEmitter.inc15278 const unsigned opcode = MI.getOpcode();
50357 assert(Inst.getOpcode() < 15263);
50358 const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]];
50364 Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str()
gen/lib/Target/AMDGPU/R600GenAsmWriter.inc 794 Bits |= OpInfo0[MI->getOpcode()] << 0;
gen/lib/Target/AMDGPU/R600GenMCCodeEmitter.inc 529 const unsigned opcode = MI.getOpcode();
2314 assert(Inst.getOpcode() < 514);
2315 const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]];
2321 Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str()
gen/lib/Target/ARC/ARCGenAsmWriter.inc 758 Bits |= OpInfo0[MI->getOpcode()] << 0;
gen/lib/Target/ARM/ARMGenAsmMatcher.inc15303 MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) {
gen/lib/Target/ARM/ARMGenAsmWriter.inc 9140 Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0;
9141 Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32;
11355 switch (MI->getOpcode()) {
11492 switch (MI->getOpcode()) {
12061 switch (MI->getOpcode()) {
gen/lib/Target/ARM/ARMGenMCCodeEmitter.inc 4228 const unsigned opcode = MI.getOpcode();
gen/lib/Target/AVR/AVRGenAsmWriter.inc 853 Bits |= OpInfo0[MI->getOpcode()] << 0;
854 Bits |= OpInfo1[MI->getOpcode()] << 16;
1056 switch (MI->getOpcode()) {
gen/lib/Target/AVR/AVRGenMCCodeEmitter.inc 357 const unsigned opcode = MI.getOpcode();
gen/lib/Target/BPF/BPFGenAsmWriter.inc 674 Bits |= OpInfo0[MI->getOpcode()] << 0;
675 Bits |= OpInfo1[MI->getOpcode()] << 16;
gen/lib/Target/BPF/BPFGenMCCodeEmitter.inc 324 const unsigned opcode = MI.getOpcode();
973 assert(Inst.getOpcode() < 309);
974 const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]];
980 Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str()
gen/lib/Target/Hexagon/HexagonGenAsmWriter.inc 9074 Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0;
9075 Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32;
9076 Bits |= (uint64_t)OpInfo2[MI->getOpcode()] << 48;
gen/lib/Target/Hexagon/HexagonGenMCCodeEmitter.inc 2993 const unsigned opcode = MI.getOpcode();
14636 assert(Inst.getOpcode() < 2978);
14637 const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]];
14643 Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str()
gen/lib/Target/Lanai/LanaiGenAsmWriter.inc 638 Bits |= OpInfo0[MI->getOpcode()] << 0;
639 Bits |= OpInfo1[MI->getOpcode()] << 16;
901 switch (MI->getOpcode()) {
gen/lib/Target/Lanai/LanaiGenMCCodeEmitter.inc 288 const unsigned opcode = MI.getOpcode();
gen/lib/Target/MSP430/MSP430GenAsmWriter.inc 599 Bits |= OpInfo0[MI->getOpcode()] << 0;
769 switch (MI->getOpcode()) {
gen/lib/Target/MSP430/MSP430GenMCCodeEmitter.inc 532 const unsigned opcode = MI.getOpcode();
gen/lib/Target/Mips/MipsGenAsmWriter.inc 6672 Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0;
6673 Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32;
7481 switch (MI->getOpcode()) {
gen/lib/Target/Mips/MipsGenMCCodeEmitter.inc 2727 const unsigned opcode = MI.getOpcode();
gen/lib/Target/NVPTX/NVPTXGenAsmWriter.inc12834 Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0;
12835 Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32;
25110 switch (MI->getOpcode()) {
25294 switch (MI->getOpcode()) {
25479 switch (MI->getOpcode()) {
25579 switch (MI->getOpcode()) {
25800 switch (MI->getOpcode()) {
26027 switch (MI->getOpcode()) {
26627 switch (MI->getOpcode()) {
gen/lib/Target/PowerPC/PPCGenAsmMatcher.inc 7185 MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) {
gen/lib/Target/PowerPC/PPCGenAsmWriter.inc 6071 Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0;
6072 Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32;
6916 switch (MI->getOpcode()) {
gen/lib/Target/PowerPC/PPCGenMCCodeEmitter.inc 2234 const unsigned opcode = MI.getOpcode();
8503 assert(Inst.getOpcode() < 2219);
8504 const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]];
8510 Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str()
gen/lib/Target/RISCV/RISCVGenAsmWriter.inc 1303 Bits |= OpInfo0[MI->getOpcode()] << 0;
1304 Bits |= OpInfo1[MI->getOpcode()] << 16;
1606 switch (MI->getOpcode()) {
gen/lib/Target/RISCV/RISCVGenCompressInstEmitter.inc 128 switch (MI.getOpcode()) {
960 switch (MI.getOpcode()) {
gen/lib/Target/RISCV/RISCVGenMCCodeEmitter.inc 523 const unsigned opcode = MI.getOpcode();
gen/lib/Target/Sparc/SparcGenAsmWriter.inc 1073 Bits |= OpInfo0[MI->getOpcode()] << 0;
1569 switch (MI->getOpcode()) {
gen/lib/Target/Sparc/SparcGenMCCodeEmitter.inc 719 const unsigned opcode = MI.getOpcode();
2456 assert(Inst.getOpcode() < 704);
2457 const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]];
2463 Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str()
gen/lib/Target/SystemZ/SystemZGenAsmWriter.inc11370 Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0;
11371 Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32;
11372 Bits |= (uint64_t)OpInfo2[MI->getOpcode()] << 48;
gen/lib/Target/SystemZ/SystemZGenMCCodeEmitter.inc 3019 const unsigned opcode = MI.getOpcode();
11984 assert(Inst.getOpcode() < 3004);
11985 const FeatureBitset &RequiredFeatures = FeatureBitsets[RequiredFeaturesRefs[Inst.getOpcode()]];
11991 Msg << "Attempting to emit " << MCII.getName(Inst.getOpcode()).str()
gen/lib/Target/WebAssembly/WebAssemblyGenAsmWriter.inc 2093 Bits |= OpInfo0[MI->getOpcode()] << 0;
gen/lib/Target/WebAssembly/WebAssemblyGenMCCodeEmitter.inc 1331 const unsigned opcode = MI.getOpcode();
gen/lib/Target/X86/X86GenAsmWriter.inc47414 Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0;
47415 Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32;
47416 Bits |= (uint64_t)OpInfo2[MI->getOpcode()] << 48;
48848 switch (MI->getOpcode()) {
gen/lib/Target/X86/X86GenAsmWriter1.inc31875 Bits |= (uint64_t)OpInfo0[MI->getOpcode()] << 0;
31876 Bits |= (uint64_t)OpInfo1[MI->getOpcode()] << 32;
33174 switch (MI->getOpcode()) {
gen/lib/Target/X86/X86GenInstrInfo.inc80116 switch(MI.getOpcode()) {
gen/lib/Target/X86/X86GenSubtargetInfo.inc19939 MI->getOpcode() == X86::CMPXCHG8B
19940 || MI->getOpcode() == X86::LCMPXCHG8B
19947 MI->getOpcode() == X86::CMPXCHG16B
19948 || MI->getOpcode() == X86::LCMPXCHG16B
19955 MI->getOpcode() == X86::LCMPXCHG8
19956 || MI->getOpcode() == X86::CMPXCHG8rm
19963 MI->getOpcode() == X86::LCMPXCHG8
19964 || MI->getOpcode() == X86::CMPXCHG8rm
19965 || MI->getOpcode() == X86::CMPXCHG16rm
19966 || MI->getOpcode() == X86::CMPXCHG32rm
19967 || MI->getOpcode() == X86::CMPXCHG64rm
19968 || MI->getOpcode() == X86::LCMPXCHG16
19969 || MI->getOpcode() == X86::LCMPXCHG32
19970 || MI->getOpcode() == X86::LCMPXCHG64
19971 || MI->getOpcode() == X86::LCMPXCHG8B
19972 || MI->getOpcode() == X86::LCMPXCHG16B
19977 MI->getOpcode() == X86::CMPXCHG8B
19978 || MI->getOpcode() == X86::LCMPXCHG8B
19982 MI->getOpcode() == X86::CMPXCHG16B
19983 || MI->getOpcode() == X86::LCMPXCHG16B
19987 MI->getOpcode() == X86::LCMPXCHG8
19988 || MI->getOpcode() == X86::CMPXCHG8rm
19992 MI->getOpcode() == X86::LCMPXCHG8
19993 || MI->getOpcode() == X86::CMPXCHG8rm
19994 || MI->getOpcode() == X86::CMPXCHG16rm
19995 || MI->getOpcode() == X86::CMPXCHG32rm
19996 || MI->getOpcode() == X86::CMPXCHG64rm
19997 || MI->getOpcode() == X86::LCMPXCHG16
19998 || MI->getOpcode() == X86::LCMPXCHG32
19999 || MI->getOpcode() == X86::LCMPXCHG64
20000 || MI->getOpcode() == X86::LCMPXCHG8B
20001 || MI->getOpcode() == X86::LCMPXCHG16B
20004 if (( MI->getOpcode() == X86::CMPXCHG8rr ))
20014 MI->getOpcode() == X86::CMPXCHG8B
20015 || MI->getOpcode() == X86::LCMPXCHG8B
20022 MI->getOpcode() == X86::CMPXCHG16B
20023 || MI->getOpcode() == X86::LCMPXCHG16B
20030 MI->getOpcode() == X86::LCMPXCHG8
20031 || MI->getOpcode() == X86::CMPXCHG8rm
20038 MI->getOpcode() == X86::LCMPXCHG8
20039 || MI->getOpcode() == X86::CMPXCHG8rm
20040 || MI->getOpcode() == X86::CMPXCHG16rm
20041 || MI->getOpcode() == X86::CMPXCHG32rm
20042 || MI->getOpcode() == X86::CMPXCHG64rm
20043 || MI->getOpcode() == X86::LCMPXCHG16
20044 || MI->getOpcode() == X86::LCMPXCHG32
20045 || MI->getOpcode() == X86::LCMPXCHG64
20046 || MI->getOpcode() == X86::LCMPXCHG8B
20047 || MI->getOpcode() == X86::LCMPXCHG16B
20052 MI->getOpcode() == X86::CMPXCHG8B
20053 || MI->getOpcode() == X86::LCMPXCHG8B
20057 MI->getOpcode() == X86::CMPXCHG16B
20058 || MI->getOpcode() == X86::LCMPXCHG16B
20062 MI->getOpcode() == X86::LCMPXCHG8
20063 || MI->getOpcode() == X86::CMPXCHG8rm
20067 MI->getOpcode() == X86::LCMPXCHG8
20068 || MI->getOpcode() == X86::CMPXCHG8rm
20069 || MI->getOpcode() == X86::CMPXCHG16rm
20070 || MI->getOpcode() == X86::CMPXCHG32rm
20071 || MI->getOpcode() == X86::CMPXCHG64rm
20072 || MI->getOpcode() == X86::LCMPXCHG16
20073 || MI->getOpcode() == X86::LCMPXCHG32
20074 || MI->getOpcode() == X86::LCMPXCHG64
20075 || MI->getOpcode() == X86::LCMPXCHG8B
20076 || MI->getOpcode() == X86::LCMPXCHG16B
20079 if (( MI->getOpcode() == X86::CMPXCHG8rr ))
20089 MI->getOpcode() == X86::CMPXCHG8B
20090 || MI->getOpcode() == X86::LCMPXCHG8B
20097 MI->getOpcode() == X86::CMPXCHG16B
20098 || MI->getOpcode() == X86::LCMPXCHG16B
20105 MI->getOpcode() == X86::LCMPXCHG8
20106 || MI->getOpcode() == X86::CMPXCHG8rm
20113 MI->getOpcode() == X86::LCMPXCHG8
20114 || MI->getOpcode() == X86::CMPXCHG8rm
20115 || MI->getOpcode() == X86::CMPXCHG16rm
20116 || MI->getOpcode() == X86::CMPXCHG32rm
20117 || MI->getOpcode() == X86::CMPXCHG64rm
20118 || MI->getOpcode() == X86::LCMPXCHG16
20119 || MI->getOpcode() == X86::LCMPXCHG32
20120 || MI->getOpcode() == X86::LCMPXCHG64
20121 || MI->getOpcode() == X86::LCMPXCHG8B
20122 || MI->getOpcode() == X86::LCMPXCHG16B
20127 MI->getOpcode() == X86::CMPXCHG8B
20128 || MI->getOpcode() == X86::LCMPXCHG8B
20132 MI->getOpcode() == X86::CMPXCHG16B
20133 || MI->getOpcode() == X86::LCMPXCHG16B
20137 MI->getOpcode() == X86::LCMPXCHG8
20138 || MI->getOpcode() == X86::CMPXCHG8rm
20142 MI->getOpcode() == X86::LCMPXCHG8
20143 || MI->getOpcode() == X86::CMPXCHG8rm
20144 || MI->getOpcode() == X86::CMPXCHG16rm
20145 || MI->getOpcode() == X86::CMPXCHG32rm
20146 || MI->getOpcode() == X86::CMPXCHG64rm
20147 || MI->getOpcode() == X86::LCMPXCHG16
20148 || MI->getOpcode() == X86::LCMPXCHG32
20149 || MI->getOpcode() == X86::LCMPXCHG64
20150 || MI->getOpcode() == X86::LCMPXCHG8B
20151 || MI->getOpcode() == X86::LCMPXCHG16B
20154 if (( MI->getOpcode() == X86::CMPXCHG8rr ))
20164 MI->getOpcode() == X86::CMPXCHG8B
20165 || MI->getOpcode() == X86::LCMPXCHG8B
20172 MI->getOpcode() == X86::CMPXCHG16B
20173 || MI->getOpcode() == X86::LCMPXCHG16B
20180 MI->getOpcode() == X86::LCMPXCHG8
20181 || MI->getOpcode() == X86::CMPXCHG8rm
20188 MI->getOpcode() == X86::LCMPXCHG8
20189 || MI->getOpcode() == X86::CMPXCHG8rm
20190 || MI->getOpcode() == X86::CMPXCHG16rm
20191 || MI->getOpcode() == X86::CMPXCHG32rm
20192 || MI->getOpcode() == X86::CMPXCHG64rm
20193 || MI->getOpcode() == X86::LCMPXCHG16
20194 || MI->getOpcode() == X86::LCMPXCHG32
20195 || MI->getOpcode() == X86::LCMPXCHG64
20196 || MI->getOpcode() == X86::LCMPXCHG8B
20197 || MI->getOpcode() == X86::LCMPXCHG16B
20202 MI->getOpcode() == X86::CMPXCHG8B
20203 || MI->getOpcode() == X86::LCMPXCHG8B
20207 MI->getOpcode() == X86::CMPXCHG16B
20208 || MI->getOpcode() == X86::LCMPXCHG16B
20212 MI->getOpcode() == X86::LCMPXCHG8
20213 || MI->getOpcode() == X86::CMPXCHG8rm
20217 MI->getOpcode() == X86::LCMPXCHG8
20218 || MI->getOpcode() == X86::CMPXCHG8rm
20219 || MI->getOpcode() == X86::CMPXCHG16rm
20220 || MI->getOpcode() == X86::CMPXCHG32rm
20221 || MI->getOpcode() == X86::CMPXCHG64rm
20222 || MI->getOpcode() == X86::LCMPXCHG16
20223 || MI->getOpcode() == X86::LCMPXCHG32
20224 || MI->getOpcode() == X86::LCMPXCHG64
20225 || MI->getOpcode() == X86::LCMPXCHG8B
20226 || MI->getOpcode() == X86::LCMPXCHG16B
20229 if (( MI->getOpcode() == X86::CMPXCHG8rr ))
20239 MI->getOpcode() == X86::CMPXCHG8B
20240 || MI->getOpcode() == X86::LCMPXCHG8B
20247 MI->getOpcode() == X86::CMPXCHG16B
20248 || MI->getOpcode() == X86::LCMPXCHG16B
20255 MI->getOpcode() == X86::LCMPXCHG8
20256 || MI->getOpcode() == X86::CMPXCHG8rm
20263 MI->getOpcode() == X86::LCMPXCHG8
20264 || MI->getOpcode() == X86::CMPXCHG8rm
20265 || MI->getOpcode() == X86::CMPXCHG16rm
20266 || MI->getOpcode() == X86::CMPXCHG32rm
20267 || MI->getOpcode() == X86::CMPXCHG64rm
20268 || MI->getOpcode() == X86::LCMPXCHG16
20269 || MI->getOpcode() == X86::LCMPXCHG32
20270 || MI->getOpcode() == X86::LCMPXCHG64
20271 || MI->getOpcode() == X86::LCMPXCHG8B
20272 || MI->getOpcode() == X86::LCMPXCHG16B
20277 MI->getOpcode() == X86::CMPXCHG8B
20278 || MI->getOpcode() == X86::LCMPXCHG8B
20282 MI->getOpcode() == X86::CMPXCHG16B
20283 || MI->getOpcode() == X86::LCMPXCHG16B
20287 MI->getOpcode() == X86::LCMPXCHG8
20288 || MI->getOpcode() == X86::CMPXCHG8rm
20292 MI->getOpcode() == X86::LCMPXCHG8
20293 || MI->getOpcode() == X86::CMPXCHG8rm
20294 || MI->getOpcode() == X86::CMPXCHG16rm
20295 || MI->getOpcode() == X86::CMPXCHG32rm
20296 || MI->getOpcode() == X86::CMPXCHG64rm
20297 || MI->getOpcode() == X86::LCMPXCHG16
20298 || MI->getOpcode() == X86::LCMPXCHG32
20299 || MI->getOpcode() == X86::LCMPXCHG64
20300 || MI->getOpcode() == X86::LCMPXCHG8B
20301 || MI->getOpcode() == X86::LCMPXCHG16B
20304 if (( MI->getOpcode() == X86::CMPXCHG8rr ))
20914 MI->getOpcode() == X86::CMPXCHG8B
20915 || MI->getOpcode() == X86::LCMPXCHG8B
20922 MI->getOpcode() == X86::CMPXCHG16B
20923 || MI->getOpcode() == X86::LCMPXCHG16B
20930 MI->getOpcode() == X86::LCMPXCHG8
20931 || MI->getOpcode() == X86::CMPXCHG8rm
20938 MI->getOpcode() == X86::LCMPXCHG8
20939 || MI->getOpcode() == X86::CMPXCHG8rm
20940 || MI->getOpcode() == X86::CMPXCHG16rm
20941 || MI->getOpcode() == X86::CMPXCHG32rm
20942 || MI->getOpcode() == X86::CMPXCHG64rm
20943 || MI->getOpcode() == X86::LCMPXCHG16
20944 || MI->getOpcode() == X86::LCMPXCHG32
20945 || MI->getOpcode() == X86::LCMPXCHG64
20946 || MI->getOpcode() == X86::LCMPXCHG8B
20947 || MI->getOpcode() == X86::LCMPXCHG16B
20952 MI->getOpcode() == X86::CMPXCHG8B
20953 || MI->getOpcode() == X86::LCMPXCHG8B
20957 MI->getOpcode() == X86::CMPXCHG16B
20958 || MI->getOpcode() == X86::LCMPXCHG16B
20962 MI->getOpcode() == X86::LCMPXCHG8
20963 || MI->getOpcode() == X86::CMPXCHG8rm
20967 MI->getOpcode() == X86::LCMPXCHG8
20968 || MI->getOpcode() == X86::CMPXCHG8rm
20969 || MI->getOpcode() == X86::CMPXCHG16rm
20970 || MI->getOpcode() == X86::CMPXCHG32rm
20971 || MI->getOpcode() == X86::CMPXCHG64rm
20972 || MI->getOpcode() == X86::LCMPXCHG16
20973 || MI->getOpcode() == X86::LCMPXCHG32
20974 || MI->getOpcode() == X86::LCMPXCHG64
20975 || MI->getOpcode() == X86::LCMPXCHG8B
20976 || MI->getOpcode() == X86::LCMPXCHG16B
20979 if (( MI->getOpcode() == X86::CMPXCHG8rr ))
20989 MI->getOpcode() == X86::CMPXCHG8B
20990 || MI->getOpcode() == X86::LCMPXCHG8B
20997 MI->getOpcode() == X86::CMPXCHG16B
20998 || MI->getOpcode() == X86::LCMPXCHG16B
21005 MI->getOpcode() == X86::LCMPXCHG8
21006 || MI->getOpcode() == X86::CMPXCHG8rm
21013 MI->getOpcode() == X86::LCMPXCHG8
21014 || MI->getOpcode() == X86::CMPXCHG8rm
21015 || MI->getOpcode() == X86::CMPXCHG16rm
21016 || MI->getOpcode() == X86::CMPXCHG32rm
21017 || MI->getOpcode() == X86::CMPXCHG64rm
21018 || MI->getOpcode() == X86::LCMPXCHG16
21019 || MI->getOpcode() == X86::LCMPXCHG32
21020 || MI->getOpcode() == X86::LCMPXCHG64
21021 || MI->getOpcode() == X86::LCMPXCHG8B
21022 || MI->getOpcode() == X86::LCMPXCHG16B
21027 MI->getOpcode() == X86::CMPXCHG8B
21028 || MI->getOpcode() == X86::LCMPXCHG8B
21032 MI->getOpcode() == X86::CMPXCHG16B
21033 || MI->getOpcode() == X86::LCMPXCHG16B
21037 MI->getOpcode() == X86::LCMPXCHG8
21038 || MI->getOpcode() == X86::CMPXCHG8rm
21042 MI->getOpcode() == X86::LCMPXCHG8
21043 || MI->getOpcode() == X86::CMPXCHG8rm
21044 || MI->getOpcode() == X86::CMPXCHG16rm
21045 || MI->getOpcode() == X86::CMPXCHG32rm
21046 || MI->getOpcode() == X86::CMPXCHG64rm
21047 || MI->getOpcode() == X86::LCMPXCHG16
21048 || MI->getOpcode() == X86::LCMPXCHG32
21049 || MI->getOpcode() == X86::LCMPXCHG64
21050 || MI->getOpcode() == X86::LCMPXCHG8B
21051 || MI->getOpcode() == X86::LCMPXCHG16B
21054 if (( MI->getOpcode() == X86::CMPXCHG8rr ))
21064 MI->getOpcode() == X86::CMPXCHG8B
21065 || MI->getOpcode() == X86::LCMPXCHG8B
21072 MI->getOpcode() == X86::CMPXCHG16B
21073 || MI->getOpcode() == X86::LCMPXCHG16B
21080 MI->getOpcode() == X86::LCMPXCHG8
21081 || MI->getOpcode() == X86::CMPXCHG8rm
21088 MI->getOpcode() == X86::LCMPXCHG8
21089 || MI->getOpcode() == X86::CMPXCHG8rm
21090 || MI->getOpcode() == X86::CMPXCHG16rm
21091 || MI->getOpcode() == X86::CMPXCHG32rm
21092 || MI->getOpcode() == X86::CMPXCHG64rm
21093 || MI->getOpcode() == X86::LCMPXCHG16
21094 || MI->getOpcode() == X86::LCMPXCHG32
21095 || MI->getOpcode() == X86::LCMPXCHG64
21096 || MI->getOpcode() == X86::LCMPXCHG8B
21097 || MI->getOpcode() == X86::LCMPXCHG16B
21102 MI->getOpcode() == X86::CMPXCHG8B
21103 || MI->getOpcode() == X86::LCMPXCHG8B
21107 MI->getOpcode() == X86::CMPXCHG16B
21108 || MI->getOpcode() == X86::LCMPXCHG16B
21112 MI->getOpcode() == X86::LCMPXCHG8
21113 || MI->getOpcode() == X86::CMPXCHG8rm
21117 MI->getOpcode() == X86::LCMPXCHG8
21118 || MI->getOpcode() == X86::CMPXCHG8rm
21119 || MI->getOpcode() == X86::CMPXCHG16rm
21120 || MI->getOpcode() == X86::CMPXCHG32rm
21121 || MI->getOpcode() == X86::CMPXCHG64rm
21122 || MI->getOpcode() == X86::LCMPXCHG16
21123 || MI->getOpcode() == X86::LCMPXCHG32
21124 || MI->getOpcode() == X86::LCMPXCHG64
21125 || MI->getOpcode() == X86::LCMPXCHG8B
21126 || MI->getOpcode() == X86::LCMPXCHG16B
21129 if (( MI->getOpcode() == X86::CMPXCHG8rr ))
23097 switch(MI.getOpcode()) {
23187 switch(MI.getOpcode()) {
23228 switch(MI.getOpcode()) {
gen/lib/Target/XCore/XCoreGenAsmWriter.inc 574 Bits |= OpInfo0[MI->getOpcode()] << 0;
include/llvm/MC/MCInstrAnalysis.h 38 return Info->get(Inst.getOpcode()).isBranch();
42 return Info->get(Inst.getOpcode()).isConditionalBranch();
46 return Info->get(Inst.getOpcode()).isUnconditionalBranch();
50 return Info->get(Inst.getOpcode()).isIndirectBranch();
54 return Info->get(Inst.getOpcode()).isCall();
58 return Info->get(Inst.getOpcode()).isReturn();
62 return Info->get(Inst.getOpcode()).isTerminator();
lib/CodeGen/AsmPrinter/AsmPrinter.cpp 1159 if (Noop.getOpcode()) {
lib/CodeGen/TargetSchedule.cpp 269 return computeInstrLatency(Inst.getOpcode());
357 return computeReciprocalThroughput(MI.getOpcode());
lib/MC/MCDisassembler/Disassembler.cpp 180 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
207 const MCInstrDesc& Desc = DC->getInstrInfo()->get(Inst.getOpcode());
lib/MC/MCInst.cpp 64 OS << "<MCInst " << getOpcode();
74 StringRef InstName = Printer ? Printer->getOpcodeName(getOpcode()) : "";
80 OS << "<MCInst #" << getOpcode();
lib/MC/MCInstrAnalysis.cpp 29 Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
lib/MC/MCSchedule.cpp 70 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
113 unsigned SchedClass = MCII.get(Inst.getOpcode()).getSchedClass();
lib/MCA/InstrBuilder.cpp 249 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode());
419 const MCInstrDesc &MCDesc = MCII.get(MCI.getOpcode());
514 unsigned short Opcode = MCI.getOpcode();
590 Descriptors[MCI.getOpcode()] = std::move(ID);
591 return *Descriptors[MCI.getOpcode()];
600 if (Descriptors.find_as(MCI.getOpcode()) != Descriptors.end())
601 return *Descriptors[MCI.getOpcode()];
lib/Target/AArch64/AArch64MCInstLower.cpp 305 switch (OutMI.getOpcode()) {
lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp 88 switch (Inst.getOpcode()) {
3891 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
3904 (Inst.getOpcode() != AArch64::BRK) &&
3905 (Inst.getOpcode() != AArch64::HLT)) {
3961 switch (Inst.getOpcode()) {
4109 switch (Inst.getOpcode()) {
4130 Inst.getOpcode() == AArch64::ADDXri)
4144 (Inst.getOpcode() == AArch64::ADDXri ||
4145 Inst.getOpcode() == AArch64::ADDWri))
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp 811 Inst.getOpcode() != AArch64::LDRXl, 0, 4))
943 switch (Inst.getOpcode()) {
1003 switch (Inst.getOpcode()) {
1020 if (Inst.getOpcode() == AArch64::MOVKWi ||
1021 Inst.getOpcode() == AArch64::MOVKXi)
1038 switch (Inst.getOpcode()) {
1103 switch (Inst.getOpcode()) {
1156 switch (Inst.getOpcode()) {
1296 unsigned Opcode = Inst.getOpcode();
1385 unsigned Opcode = Inst.getOpcode();
1517 switch (Inst.getOpcode()) {
1571 if (Inst.getOpcode() == AArch64::ANDSXri)
1580 if (Inst.getOpcode() == AArch64::ANDSWri)
1601 if (Inst.getOpcode() == AArch64::MOVID)
1608 switch (Inst.getOpcode()) {
1819 if (Inst.getOpcode() != AArch64::DUPM_ZI)
lib/Target/AArch64/Disassembler/AArch64ExternalSymbolizer.cpp 92 } else if (MI.getOpcode() == AArch64::ADRP) {
105 } else if (MI.getOpcode() == AArch64::ADDXri ||
106 MI.getOpcode() == AArch64::LDRXui ||
107 MI.getOpcode() == AArch64::LDRXl ||
108 MI.getOpcode() == AArch64::ADR) {
109 if (MI.getOpcode() == AArch64::ADDXri)
111 else if (MI.getOpcode() == AArch64::LDRXui)
113 if (MI.getOpcode() == AArch64::LDRXl) {
117 } else if (MI.getOpcode() == AArch64::ADR) {
126 MI.getOpcode() == AArch64::ADDXri ? 0x91000000: 0xF9400000;
lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp 64 unsigned Opcode = MI->getOpcode();
704 unsigned Opcode = MI->getOpcode();
708 if (isTblTbxInstruction(MI->getOpcode(), Layout, IsTbx)) {
758 unsigned Opcode = MI->getOpcode();
1375 unsigned Opcode = MI->getOpcode();
lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp 244 MCFixupKind Kind = MI.getOpcode() == AArch64::ADR
397 MCFixupKind Kind = MI.getOpcode() == AArch64::BL
597 if (MI.getOpcode() == AArch64::TLSDESCCALL) {
604 } else if (MI.getOpcode() == AArch64::CompilerBarrier) {
lib/Target/AArch64/MCTargetDesc/AArch64MCTargetDesc.cpp 317 const auto &Desc = Info->get(Inst.getOpcode());
lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp 1688 if (AMDGPU::isSISrcOperand(AsmParser->getMII()->get(Inst.getOpcode()),
1700 const auto& InstDesc = AsmParser->getMII()->get(Inst.getOpcode());
2659 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
2672 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi ||
2673 Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) {
2676 AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::dst_sel);
2718 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
2742 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
2811 const unsigned Opcode = Inst.getOpcode();
2890 const unsigned Opcode = Inst.getOpcode();
2928 const unsigned Opc = Inst.getOpcode();
2942 const unsigned Opc = Inst.getOpcode();
2974 const unsigned Opc = Inst.getOpcode();
3015 const unsigned Opc = Inst.getOpcode();
3035 const unsigned Opc = Inst.getOpcode();
3054 const unsigned Opc = Inst.getOpcode();
3070 const unsigned Opc = Inst.getOpcode();
3219 const unsigned Opcode = Inst.getOpcode();
3264 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
3268 auto Opcode = Inst.getOpcode();
3303 unsigned Opcode = Inst.getOpcode();
3339 const unsigned Opc = Inst.getOpcode();
3360 unsigned Opcode = Inst.getOpcode();
4775 (Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_gfx10 ||
4776 Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_gfx6_gfx7 ||
4777 Inst.getOpcode() == AMDGPU::DS_SWIZZLE_B32_vi) ? AMDGPUOperand::ImmTySwizzle :
5845 int NoLdsOpcode = AMDGPU::getMUBUFNoLdsInst(Inst.getOpcode());
5913 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
6162 int Opc = Inst.getOpcode();
6197 unsigned Opc = Inst.getOpcode();
6200 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
6235 unsigned Opc = Inst.getOpcode();
6238 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
6304 const int Opc = Inst.getOpcode();
6682 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
6737 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::fi) != -1) {
6841 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
6877 if (Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx10 &&
6878 Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx9 &&
6879 Inst.getOpcode() != AMDGPU::V_NOP_sdwa_vi) {
6884 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::omod) != -1) {
6894 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::omod) != -1) {
6904 if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::clamp) != -1)
6917 if (Inst.getOpcode() == AMDGPU::V_MAC_F32_sdwa_vi ||
6918 Inst.getOpcode() == AMDGPU::V_MAC_F16_sdwa_vi) {
6921 it, AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::src2));
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp 81 int OpIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), NameIdx);
245 assert(MI.getOpcode() == 0);
260 int FiIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::fi);
365 !(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3))) {
371 if (Res && (MI.getOpcode() == AMDGPU::V_MAC_F32_e64_vi ||
372 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
373 MI.getOpcode() == AMDGPU::V_MAC_F32_e64_gfx10 ||
374 MI.getOpcode() == AMDGPU::V_MAC_F16_e64_vi ||
375 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_vi ||
376 MI.getOpcode() == AMDGPU::V_FMAC_F32_e64_gfx10 ||
377 MI.getOpcode() == AMDGPU::V_FMAC_F16_e64_gfx10)) {
383 if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::MIMG)) {
385 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
387 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::srsrc);
409 int VDstIn_Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
412 int Tied = MCII->get(MI.getOpcode()).getOperandConstraint(VDstIn_Idx,
435 if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
439 int SDst = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst);
453 unsigned Opc = MI.getOpcode();
475 int VDstIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
478 int VDataIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
481 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vaddr0);
482 int DMaskIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
485 int TFEIdx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
487 int D16Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
494 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo(MI.getOpcode());
496 bool IsGather4 = MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::Gather4;
503 AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::dim);
lib/Target/AMDGPU/MCTargetDesc/AMDGPUAsmBackend.cpp 59 unsigned RelaxedOpcode = AMDGPU::getSOPPWithRelaxation(Inst.getOpcode());
80 if (AMDGPU::getSOPPWithRelaxation(Inst.getOpcode()) >= 0)
lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp 127 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
305 if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3)
307 else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::DPP)
309 else if (MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::SDWA)
318 switch (MI->getOpcode()) {
505 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
577 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
595 switch (MI->getOpcode()) {
613 if ((int)OpNo == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
667 switch (MI->getOpcode()) {
674 if ((int)OpNo + 1 == AMDGPU::getNamedOperandIdx(MI->getOpcode(),
870 unsigned Opc = MI->getOpcode();
957 unsigned Opc = MI->getOpcode();
974 MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::VOP3_OPSEL;
977 MII.get(MI->getOpcode()).TSFlags & SIInstrFlags::IsPacked;
1000 unsigned Opc = MI->getOpcode();
lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCTargetDesc.cpp 118 Info->get(Inst.getOpcode()).OpInfo[0].OperandType !=
lib/Target/AMDGPU/MCTargetDesc/R600MCCodeEmitter.cpp 105 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
106 if (MI.getOpcode() == R600::RETURN ||
107 MI.getOpcode() == R600::FETCH_CLAUSE ||
108 MI.getOpcode() == R600::ALU_CLAUSE ||
109 MI.getOpcode() == R600::BUNDLE ||
110 MI.getOpcode() == R600::KILL) {
176 if (HAS_NATIVE_OPERANDS(MCII.get(MI.getOpcode()).TSFlags))
lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp 286 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
295 int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
297 int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
381 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
475 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
490 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
lib/Target/ARM/ARMFeatures.h 25 switch (Instr->getOpcode()) {
lib/Target/ARM/AsmParser/ARMAsmParser.cpp 2364 const MCInstrDesc &MCID = ARMInsts[Inst.getOpcode()];
3270 assert((Inst.getOpcode() == ARM::VMOVv8i8 ||
3271 Inst.getOpcode() == ARM::VMOVv16i8) &&
3313 assert((Inst.getOpcode() == ARM::VMOVv4i16 ||
3314 Inst.getOpcode() == ARM::VMOVv8i16 ||
3315 Inst.getOpcode() == ARM::VMVNv4i16 ||
3316 Inst.getOpcode() == ARM::VMVNv8i16) &&
3337 assert((Inst.getOpcode() == ARM::VMOVv2i32 ||
3338 Inst.getOpcode() == ARM::VMOVv4i32 ||
3339 Inst.getOpcode() == ARM::VMVNv2i32 ||
3340 Inst.getOpcode() == ARM::VMVNv4i32) &&
5570 switch(Inst.getOpcode()) {
5584 switch(Inst.getOpcode()) {
5592 switch(Inst.getOpcode()) {
5605 switch(Inst.getOpcode()) {
7179 return Inst.getOpcode() == ARM::tBKPT ||
7180 Inst.getOpcode() == ARM::BKPT ||
7181 Inst.getOpcode() == ARM::tHLT ||
7182 Inst.getOpcode() == ARM::HLT;
7298 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
7324 ARMCC::AL && Inst.getOpcode() != ARM::tBcc &&
7325 Inst.getOpcode() != ARM::t2Bcc &&
7326 Inst.getOpcode() != ARM::t2BFic) {
7374 const unsigned Opcode = Inst.getOpcode();
8203 switch (Inst.getOpcode()) {
8218 switch(Inst.getOpcode()) {
8252 (Inst.getOpcode() == ARM::LDRT_POST) ? ARM::LDRT_POST_IMM
8270 (Inst.getOpcode() == ARM::STRT_POST) ? ARM::STRT_POST_IMM
8350 if (Inst.getOpcode() == ARM::LDRConstPool)
8352 else if (Inst.getOpcode() == ARM::tLDRConstPool)
8354 else if (Inst.getOpcode() == ARM::t2LDRConstPool)
8369 if (Inst.getOpcode() == ARM::LDRConstPool) {
8422 if (TmpInst.getOpcode() == ARM::LDRi12)
8437 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8459 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8483 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8509 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8535 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8557 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8581 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8607 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8633 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8653 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8675 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8699 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
8724 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8747 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8774 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8805 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8838 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8861 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8888 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8919 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8952 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8973 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
8998 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9027 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9060 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9082 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9106 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9131 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9153 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9177 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9202 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9226 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9252 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9279 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9303 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9329 TmpInst.setOpcode(getRealVLDOpcode(Inst.getOpcode(), Spacing));
9356 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9378 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9402 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9427 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9451 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9477 TmpInst.setOpcode(getRealVSTOpcode(Inst.getOpcode(), Spacing));
9504 switch (Inst.getOpcode()) {
9535 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsr) &&
9551 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
9558 Inst.getOpcode() == ARM::t2MOVSsr ? ARM::CPSR : 0));
9570 inITBlock() == (Inst.getOpcode() == ARM::t2MOVsi) &&
9604 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
9612 Inst.getOpcode() == ARM::t2MOVSsi ? ARM::CPSR : 0));
9622 switch(Inst.getOpcode()) {
9647 switch(Inst.getOpcode()) {
9804 TmpInst.setOpcode(Inst.getOpcode() == ARM::t2ADDri ?
9995 switch (Inst.getOpcode()) {
10042 switch (Inst.getOpcode()) {
10090 switch (Inst.getOpcode()) {
10126 switch (Inst.getOpcode()) {
10186 unsigned Opc = Inst.getOpcode();
10243 switch (Inst.getOpcode()) {
10304 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10308 if (MCID.isTerminator() || (MCID.isCall() && Inst.getOpcode() != ARM::tSVC) ||
10337 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10361 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10368 if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) {
10368 if (Inst.getOpcode() == ARM::tBcc || Inst.getOpcode() == ARM::t2Bcc) {
10388 const MCInstrDesc &MCID = MII.get(Inst.getOpcode());
10424 Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));
10446 Inst.dump_pretty(dbgs(), MII.getName(Inst.getOpcode()));
10464 if (Inst.getOpcode() == ARM::ITasm)
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 583 switch (MI.getOpcode()) {
730 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
731 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
767 switch (MI.getOpcode()) {
808 if ((!isVectorPredicable(MI.getOpcode()) && VPTBlock.instrInVPTBlock()) ||
809 (isVectorPredicable(MI.getOpcode()) && ITBlock.instrInITBlock()))
824 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
825 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
832 if (ARMInsts[MI.getOpcode()].isPredicable()) {
849 if (isVectorPredicable(MI.getOpcode())) {
857 int TiedOp = ARMInsts[MI.getOpcode()].getOperandConstraint(
888 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
890 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
893 if (CC != ARMCC::AL && !ARMInsts[MI.getOpcode()].isPredicable())
948 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
956 if (MI.getOpcode() == ARM::t2IT) {
985 if (isVPTOpcode(MI.getOpcode()) && VPTBlock.instrInVPTBlock())
990 if (isVPTOpcode(MI.getOpcode())) {
1417 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
1419 if (Val != ARMCC::AL && !ARMInsts[Inst.getOpcode()].isPredicable())
1517 switch (Inst.getOpcode()) {
1646 switch (Inst.getOpcode()) {
1723 switch (Inst.getOpcode()) {
1784 switch (Inst.getOpcode()) {
1826 switch (Inst.getOpcode()) {
1846 switch (Inst.getOpcode()) {
1979 switch (Inst.getOpcode()) {
1991 switch (Inst.getOpcode()) {
2078 switch (Inst.getOpcode()) {
2095 switch (Inst.getOpcode()) {
2111 switch (Inst.getOpcode()) {
2215 switch (Inst.getOpcode()) {
2419 if (Inst.getOpcode() == ARM::t2MOVTi16)
2442 if (Inst.getOpcode() == ARM::MOVTi16)
2682 switch (Inst.getOpcode()) {
2713 switch (Inst.getOpcode()) {
2749 switch(Inst.getOpcode()) {
2785 switch (Inst.getOpcode()) {
2809 switch (Inst.getOpcode()) {
2886 switch (Inst.getOpcode()) {
3009 switch (Inst.getOpcode()) {
3088 switch (Inst.getOpcode()) {
3126 switch (Inst.getOpcode()) {
3169 switch (Inst.getOpcode()) {
3205 switch (Inst.getOpcode()) {
3241 switch (Inst.getOpcode()) {
3282 switch (Inst.getOpcode()) {
3326 switch (Inst.getOpcode()) {
3473 switch (Inst.getOpcode()) {
3509 if (cmode == 0xF && Inst.getOpcode() == ARM::MVE_VMVNimmi32)
3611 switch (Inst.getOpcode()) {
3638 switch(Inst.getOpcode()) {
3732 switch (Inst.getOpcode()) {
3766 switch (Inst.getOpcode()) {
3796 switch (Inst.getOpcode()) {
3810 switch (Inst.getOpcode()) {
3854 switch (Inst.getOpcode()) {
3883 switch (Inst.getOpcode()) {
3898 switch (Inst.getOpcode()) {
3935 switch (Inst.getOpcode()) {
3964 switch (Inst.getOpcode()) {
3978 switch (Inst.getOpcode()) {
4009 switch (Inst.getOpcode()) {
4052 switch (Inst.getOpcode()) {
4067 switch(Inst.getOpcode()) {
4201 switch (Inst.getOpcode()) {
4216 switch (Inst.getOpcode()) {
4287 switch (Inst.getOpcode()) {
4344 switch (Inst.getOpcode()) {
4377 if (Inst.getOpcode() == ARM::tADDrSP) {
4386 } else if (Inst.getOpcode() == ARM::tADDspr) {
4692 if (Inst.getOpcode() == ARM::t2MSR_M) {
5843 if (Inst.getOpcode() == ARM::MRRC2) {
5851 if (Inst.getOpcode() == ARM::MCRR2) {
5871 switch (Inst.getOpcode()) {
5880 if (Inst.getOpcode() != ARM::FMSTAT) {
5892 switch (Inst.getOpcode()) {
5958 if (Inst.getOpcode() == ARM::MVE_LCTP)
5963 switch (Inst.getOpcode()) {
6055 if (Inst.getOpcode() == ARM::VSCCLRMD) {
6237 switch (Inst.getOpcode()) {
6277 switch (Inst.getOpcode()) {
6298 if (unsigned Sysreg = FixedRegForVSTRVLDR_SYSREG(Inst.getOpcode()))
6461 switch (Inst.getOpcode()) {
6514 if (Inst.getOpcode() == ARM::MVE_SQRSHRL ||
6515 Inst.getOpcode() == ARM::MVE_UQRSHLL) {
lib/Target/ARM/MCTargetDesc/ARMAsmBackend.cpp 222 if (getRelaxedOpcode(Inst.getOpcode(), STI) != Inst.getOpcode())
222 if (getRelaxedOpcode(Inst.getOpcode(), STI) != Inst.getOpcode())
322 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode(), STI);
325 if (RelaxedOp == Inst.getOpcode()) {
335 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
335 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) &&
lib/Target/ARM/MCTargetDesc/ARMInstPrinter.cpp 93 unsigned Opcode = MI->getOpcode();
808 if (MI->getOpcode() != ARM::t2CLRM) {
870 unsigned Opcode = MI->getOpcode();
1378 switch (MI->getOpcode()) {
lib/Target/ARM/MCTargetDesc/ARMMCCodeEmitter.cpp 958 switch(MI.getOpcode()) {
1733 if (MI.getOpcode() == ARM::VSCCLRMD || MI.getOpcode() == ARM::VSCCLRMS)
1733 if (MI.getOpcode() == ARM::VSCCLRMD || MI.getOpcode() == ARM::VSCCLRMS)
1871 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
lib/Target/ARM/MCTargetDesc/ARMMCTargetDesc.cpp 253 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
260 if (Inst.getOpcode() == ARM::Bcc && Inst.getOperand(1).getImm()==ARMCC::AL)
268 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType!=MCOI::OPERAND_PCREL)
284 switch (Inst.getOpcode()) {
298 if (Info->get(Inst.getOpcode()).OpInfo[OpId].OperandType !=
lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp 37 unsigned Opcode = MI->getOpcode();
103 const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).OpInfo[OpNo];
lib/Target/AVR/MCTargetDesc/AVRMCCodeEmitter.cpp 73 unsigned Opcode = MI.getOpcode();
285 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
lib/Target/BPF/Disassembler/BPFDisassembler.cpp 188 switch (Instr.getOpcode()) {
lib/Target/BPF/MCTargetDesc/BPFMCCodeEmitter.cpp 101 if (MI.getOpcode() == BPF::JAL)
104 else if (MI.getOpcode() == BPF::LD_imm64)
124 unsigned Opcode = MI.getOpcode();
lib/Target/Hexagon/AsmParser/HexagonAsmParser.cpp 533 NewInst.setOpcode(MCI.getOpcode());
1291 switch (Inst.getOpcode()) {
1403 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
1419 Inst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrptnew)
lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp 202 switch (MI.getOpcode()) {
279 switch (MI.getOpcode()) {
426 switch (MI.getOpcode()) {
lib/Target/Hexagon/HexagonAsmPrinter.cpp 249 T.setOpcode(Inst.getOpcode());
273 switch (Inst.getOpcode()) {
472 if (Inst.getOpcode() == Hexagon::S2_asr_i_p_rnd_goodsyntax)
557 MappedInst.setOpcode((Inst.getOpcode() == Hexagon::A2_tfrpt)
571 MappedInst.setOpcode(Inst.getOpcode() == Hexagon::A2_tfrptnew
lib/Target/Hexagon/HexagonMCInstLower.cpp 109 assert(MCI->getOpcode() == static_cast<unsigned>(MI->getOpcode()) &&
lib/Target/Hexagon/MCTargetDesc/HexagonAsmBackend.cpp 545 HMI.getOpcode() != Hexagon::C4_addipc))
lib/Target/Hexagon/MCTargetDesc/HexagonMCChecker.cpp 264 unsigned subInst0Opcode = ID.getOperand(0).getInst()->getOpcode();
265 unsigned subInst1Opcode = ID.getOperand(1).getInst()->getOpcode();
lib/Target/Hexagon/MCTargetDesc/HexagonMCCodeEmitter.cpp 420 unsigned Opc = MI.getOpcode();
435 unsigned DupIClass = MI.getOpcode() - Hexagon::DuplexIClass0;
lib/Target/Hexagon/MCTargetDesc/HexagonMCCompound.cpp 82 switch (MI.getOpcode()) {
181 switch (HMCI.getOpcode()) {
204 switch (L.getOpcode()) {
340 unsigned Opca = MIa.getOpcode();
373 LLVM_DEBUG(dbgs() << "J,B: " << JumpInst->getOpcode() << ","
374 << Inst->getOpcode() << "\n");
378 LLVM_DEBUG(dbgs() << "B: " << Inst->getOpcode() << ","
379 << JumpInst->getOpcode() << " Compounds to "
380 << CompoundInsn->getOpcode() << "\n");
lib/Target/Hexagon/MCTargetDesc/HexagonMCDuplexInfo.cpp 193 switch (MCI.getOpcode()) {
543 switch (potentialDuplex.getOpcode()) {
588 unsigned Opcode = MIb.getOpcode();
605 subinstOpcodeMap.find(SubInst0.getOpcode())->second;
607 subinstOpcodeMap.find(SubInst1.getOpcode())->second;
616 if (MIb.getOpcode() == Hexagon::S2_allocframe)
706 switch (Inst.getOpcode()) {
1050 if (isStoreInst(MCB.getOperand(j).getInst()->getOpcode()) &&
1051 isStoreInst(MCB.getOperand(k).getInst()->getOpcode())) {
1074 << MCB.getOperand(j).getInst()->getOpcode() << ","
1075 << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1079 << MCB.getOperand(j).getInst()->getOpcode() << ","
1080 << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1100 << MCB.getOperand(j).getInst()->getOpcode() << ","
1101 << MCB.getOperand(k).getInst()->getOpcode() << "\n");
1105 << MCB.getOperand(j).getInst()->getOpcode() << ","
1106 << MCB.getOperand(k).getInst()->getOpcode() << "\n");
lib/Target/Hexagon/MCTargetDesc/HexagonMCELFStreamer.cpp 63 assert(MCB.getOpcode() == Hexagon::BUNDLE);
lib/Target/Hexagon/MCTargetDesc/HexagonMCInstrInfo.cpp 225 return MCII.get(MCI.getOpcode());
344 return MCII.getName(MCI.getOpcode());
393 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
488 auto Result = Hexagon::BUNDLE == MCI.getOpcode();
512 (MCI.getOpcode() != Hexagon::C4_addipc))
591 return MCI.getOpcode() == Hexagon::A4_ext;
685 const uint64_t F = MCII.get(MCI.getOpcode()).TSFlags;
696 switch (MCI.getOpcode()) {
lib/Target/Hexagon/MCTargetDesc/HexagonMCShuffler.cpp 39 LLVM_DEBUG(dbgs() << "Shuffling: " << MCII.getName(MI.getOpcode())
lib/Target/Hexagon/MCTargetDesc/HexagonShuffler.cpp 441 switch (ID.getOpcode()) {
lib/Target/Lanai/AsmParser/LanaiAsmParser.cpp 661 Opcode = Inst.getOpcode();
lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp 94 if (isRMOpcode(Instr.getOpcode()))
96 else if (isSPLSOpcode(Instr.getOpcode()))
98 else if (isRRMOpcode(Instr.getOpcode())) {
lib/Target/Lanai/MCTargetDesc/LanaiInstPrinter.cpp 110 switch (MI->getOpcode()) {
lib/Target/Lanai/MCTargetDesc/LanaiMCTargetDesc.cpp 101 if (Info->get(Inst.getOpcode()).OpInfo[0].OperandType ==
lib/Target/MSP430/MCTargetDesc/MSP430MCCodeEmitter.cpp 85 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
lib/Target/Mips/AsmParser/MipsAsmParser.cpp 1721 switch (Inst.getOpcode()) {
1784 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
1790 const unsigned Opcode = Inst.getOpcode();
1904 if (hasMips32r6() && Inst.getOpcode() == Mips::SSNOP) {
1911 const unsigned Opcode = Inst.getOpcode();
1961 switch (Inst.getOpcode()) {
2007 if ((Inst.getOpcode() == Mips::J || Inst.getOpcode() == Mips::J_MM) &&
2007 if ((Inst.getOpcode() == Mips::J || Inst.getOpcode() == Mips::J_MM) &&
2019 if ((Inst.getOpcode() == Mips::JAL || Inst.getOpcode() == Mips::JAL_MM) &&
2019 if ((Inst.getOpcode() == Mips::JAL || Inst.getOpcode() == Mips::JAL_MM) &&
2104 if (MCID.mayLoad() && Inst.getOpcode() != Mips::LWP_MM) {
2135 switch (Inst.getOpcode()) {
2283 if ((Inst.getOpcode() == Mips::JalOneReg ||
2284 Inst.getOpcode() == Mips::JalTwoReg || ExpandedJalSym) &&
2306 switch (Inst.getOpcode()) {
2321 Inst.getOpcode() == Mips::LoadAddrImm32, IDLoc,
2334 Inst.getOpcode() == Mips::LoadAddrReg32, IDLoc,
2527 Inst.getOpcode() == Mips::LDMacro)
2560 const unsigned Opcode = Inst.getOpcode();
2589 const MCInstrDesc &MCID = getInstDesc(JalrInst.getOpcode());
3490 assert(getInstDesc(Inst.getOpcode()).getNumOperands() == 1 &&
3523 const MCInstrDesc &MCID = getInstDesc(Inst.getOpcode());
3546 switch(Inst.getOpcode()) {
3608 const MCInstrDesc &Desc = getInstDesc(Inst.getOpcode());
3636 TOut.emitSCWithSymOffset(Inst.getOpcode(), DstReg, BaseReg, HiOperand,
3664 TOut.emitRRI(Inst.getOpcode(), DstReg, TmpReg, LoOffset, IDLoc, STI);
3688 TOut.emitRRI(Inst.getOpcode(), DstReg, TmpReg, Res.getConstant(), IDLoc,
3707 TOut.emitRRX(Inst.getOpcode(), DstReg, TmpReg, LoOperand, IDLoc, STI);
3719 unsigned Opcode = Inst.getOpcode();
3749 unsigned PseudoOpcode = Inst.getOpcode();
4057 unsigned Opcode = Inst.getOpcode();
4353 bool IsLoadInst = (Inst.getOpcode() == Mips::Ulw);
4399 switch (Inst.getOpcode()) {
4433 switch (Inst.getOpcode()) {
4490 switch (Inst.getOpcode()) {
4538 unsigned FinalOpcode = Inst.getOpcode();
4646 if (Inst.getOpcode() == Mips::ROL) {
4652 if (Inst.getOpcode() == Mips::ROR) {
4661 switch (Inst.getOpcode()) {
4702 if (Inst.getOpcode() == Mips::ROLImm) {
4711 if (Inst.getOpcode() == Mips::RORImm) {
4725 switch (Inst.getOpcode()) {
4771 if (Inst.getOpcode() == Mips::DROL) {
4777 if (Inst.getOpcode() == Mips::DROR) {
4786 switch (Inst.getOpcode()) {
4835 if (Inst.getOpcode() == Mips::DROLImm)
4840 if (Inst.getOpcode() == Mips::DROLImm)
4847 if (Inst.getOpcode() == Mips::DROLImm)
4861 switch (Inst.getOpcode()) {
4940 TOut.emitRR(Inst.getOpcode() == Mips::MULImmMacro ? Mips::MULT : Mips::DMULT,
4960 TOut.emitRR(Inst.getOpcode() == Mips::MULOMacro ? Mips::MULT : Mips::DMULT,
4965 TOut.emitRRI(Inst.getOpcode() == Mips::MULOMacro ? Mips::SRA : Mips::DSRA32,
5002 TOut.emitRR(Inst.getOpcode() == Mips::MULOUMacro ? Mips::MULTu : Mips::DMULTu,
5213 switch (Inst.getOpcode()) {
5353 switch (Inst.getOpcode()) {
5407 : (Inst.getOpcode() != Mips::MTTDSP ? Inst.getOperand(1).getReg()
5418 switch (Inst.getOpcode()) {
5431 switch (Inst.getOpcode()) {
5561 uint64_t TSFlags = getInstDesc(Inst.getOpcode()).TSFlags;
5794 (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) &&
5794 (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM) &&
lib/Target/Mips/Disassembler/MipsDisassembler.cpp 1072 switch (MI.getOpcode()) {
1112 switch (MI.getOpcode()) {
1531 if (Inst.getOpcode() == Mips::SC ||
1532 Inst.getOpcode() == Mips::SCD)
1553 if (Inst.getOpcode() == Mips::SCE)
1711 switch(Inst.getOpcode())
1746 switch (Inst.getOpcode()) {
1770 switch (Inst.getOpcode()) {
1833 switch (Inst.getOpcode()) {
1864 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
1864 if (Inst.getOpcode() == Mips::SCE_MM || Inst.getOpcode() == Mips::SC_MMR6)
1885 switch (Inst.getOpcode()) {
1899 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
1899 if (Inst.getOpcode() == Mips::LWP_MM || Inst.getOpcode() == Mips::SWP_MM)
2044 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
2044 if(Inst.getOpcode() == Mips::SC_R6 || Inst.getOpcode() == Mips::SCD_R6){
2444 switch(Inst.getOpcode()) {
lib/Target/Mips/MCTargetDesc/MipsInstPrinter.cpp 80 switch (MI->getOpcode()) {
115 switch (MI->getOpcode()) {
164 switch (MI->getOpcode()) {
220 switch (MI.getOpcode()) {
lib/Target/Mips/MCTargetDesc/MipsMCCodeEmitter.cpp 72 switch (Inst.getOpcode()) {
101 if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC ||
101 if (Inst.getOpcode() == Mips::BNEC || Inst.getOpcode() == Mips::BEQC ||
102 Inst.getOpcode() == Mips::BNEC64 || Inst.getOpcode() == Mips::BEQC64) {
102 Inst.getOpcode() == Mips::BNEC64 || Inst.getOpcode() == Mips::BEQC64) {
106 } else if (Inst.getOpcode() == Mips::BNVC || Inst.getOpcode() == Mips::BOVC) {
106 } else if (Inst.getOpcode() == Mips::BNVC || Inst.getOpcode() == Mips::BOVC) {
109 } else if (Inst.getOpcode() == Mips::BNVC_MMR6 ||
110 Inst.getOpcode() == Mips::BOVC_MMR6) {
162 switch (MI.getOpcode()) {
188 const unsigned Opcode = TmpInst.getOpcode();
215 if (((MI.getOpcode() == Mips::MOVEP_MM) ||
216 (MI.getOpcode() == Mips::MOVEP_MMR6))) {
222 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
884 switch (MI.getOpcode()) {
920 switch (MI.getOpcode()) {
lib/Target/Mips/MCTargetDesc/MipsMCTargetDesc.cpp 145 switch (Info->get(Inst.getOpcode()).OpInfo[NumOps - 1].OperandType) {
lib/Target/Mips/MCTargetDesc/MipsNaClELFStreamer.cpp 59 if (MI.getOpcode() == Mips::JALR) {
65 return MI.getOpcode() == Mips::JR;
74 unsigned Opcode = MI.getOpcode();
159 bool IsMemAccess = isBasePlusOffsetMemoryAccess(Inst.getOpcode(), &AddrIdx,
lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp 714 int Opcode = Inst.getOpcode();
lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp 205 switch (Inst.getOpcode()) {
240 if (Inst.getOpcode() == PPC::LDU)
243 else if (Inst.getOpcode() == PPC::STDU)
lib/Target/PowerPC/MCTargetDesc/PPCInstPrinter.cpp 74 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
74 (MI->getOpcode() == PPC::ADDIS8 || MI->getOpcode() == PPC::ADDIS) &&
95 if (MI->getOpcode() == PPC::RLWINM) {
118 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
118 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) &&
128 if (MI->getOpcode() == PPC::RLDICR ||
129 MI->getOpcode() == PPC::RLDICR_32) {
152 if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
152 if (MI->getOpcode() == PPC::DCBT || MI->getOpcode() == PPC::DCBTST) {
155 if (MI->getOpcode() == PPC::DCBTST)
176 if (MI->getOpcode() == PPC::DCBF) {
544 Reg = PPCInstrInfo::getRegNumForOperand(MII.get(MI->getOpcode()),
lib/Target/PowerPC/MCTargetDesc/PPCMCCodeEmitter.cpp 240 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
240 assert((MI.getOpcode() == PPC::MTOCRF || MI.getOpcode() == PPC::MTOCRF8 ||
241 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
241 MI.getOpcode() == PPC::MFOCRF || MI.getOpcode() == PPC::MFOCRF8) &&
267 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
267 assert((MI.getOpcode() != PPC::MTOCRF && MI.getOpcode() != PPC::MTOCRF8 &&
268 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
268 MI.getOpcode() != PPC::MFOCRF && MI.getOpcode() != PPC::MFOCRF8) ||
272 PPCInstrInfo::getRegNumForOperand(MCII.get(MI.getOpcode()),
314 unsigned Opcode = MI.getOpcode();
lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp 1733 assert(Inst.getOpcode() == RISCV::PseudoAddTPRel && "Invalid instruction");
1749 switch (Inst.getOpcode()) {
lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 155 if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
155 if (Inst.getOpcode() == RISCV::C_LWSP || Inst.getOpcode() == RISCV::C_SWSP ||
156 Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
156 Inst.getOpcode() == RISCV::C_LDSP || Inst.getOpcode() == RISCV::C_SDSP ||
157 Inst.getOpcode() == RISCV::C_FLWSP ||
158 Inst.getOpcode() == RISCV::C_FSWSP ||
159 Inst.getOpcode() == RISCV::C_FLDSP ||
160 Inst.getOpcode() == RISCV::C_FSDSP ||
161 Inst.getOpcode() == RISCV::C_ADDI4SPN) {
164 if (Inst.getOpcode() == RISCV::C_ADDI16SP) {
lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp 111 switch (Inst.getOpcode()) {
161 return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
161 return getRelaxedOpcode(Inst.getOpcode()) != Inst.getOpcode();
lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp 105 if (MI.getOpcode() == RISCV::PseudoTAIL) {
108 } else if (MI.getOpcode() == RISCV::PseudoCALLReg) {
128 if (MI.getOpcode() == RISCV::PseudoTAIL)
179 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
183 if (MI.getOpcode() == RISCV::PseudoCALLReg ||
184 MI.getOpcode() == RISCV::PseudoCALL ||
185 MI.getOpcode() == RISCV::PseudoTAIL) {
191 if (MI.getOpcode() == RISCV::PseudoAddTPRel) {
251 MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
lib/Target/Sparc/AsmParser/SparcAsmParser.cpp 591 switch (Inst.getOpcode()) {
lib/Target/Sparc/MCTargetDesc/SparcInstPrinter.cpp 56 switch (MI->getOpcode()) {
90 switch(MI->getOpcode()) {
118 switch (MI->getOpcode()) {
166 switch (MI->getOpcode()) {
lib/Target/Sparc/MCTargetDesc/SparcMCCodeEmitter.cpp 105 switch (MI.getOpcode()) {
157 if (MI.getOpcode() == SP::TLS_CALL) {
lib/Target/SystemZ/MCTargetDesc/SystemZMCCodeEmitter.cpp 162 unsigned Size = MCII.get(MI.getOpcode()).getSize();
lib/Target/WebAssembly/AsmParser/WebAssemblyAsmParser.cpp 795 auto Align = WebAssembly::GetDefaultP2AlignAny(Inst.getOpcode());
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyInstPrinter.cpp 54 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
62 if (I != 0 && ((MI->getOpcode() != WebAssembly::CALL_INDIRECT_VOID &&
63 MI->getOpcode() != WebAssembly::CALL_INDIRECT_VOID_S) ||
76 unsigned Opc = MI->getOpcode();
215 else if (OpNo >= MII.get(MI->getOpcode()).getNumDefs())
222 if (OpNo < MII.get(MI->getOpcode()).getNumDefs())
227 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
267 if (Imm == WebAssembly::GetDefaultP2Align(MI->getOpcode()))
lib/Target/WebAssembly/MCTargetDesc/WebAssemblyMCCodeEmitter.cpp 76 if (MI.getOpcode() == WebAssembly::BR_TABLE_I32_S ||
77 MI.getOpcode() == WebAssembly::BR_TABLE_I64_S)
79 if (MI.getOpcode() == WebAssembly::BR_TABLE_I32 ||
80 MI.getOpcode() == WebAssembly::BR_TABLE_I64)
83 const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp 329 auto RegOpcode = OutMI.getOpcode();
lib/Target/X86/AsmParser/X86AsmParser.cpp 2876 switch (Inst.getOpcode()) {
2899 switch (Inst.getOpcode()) {
2928 switch (Inst.getOpcode()) {
2942 switch (Inst.getOpcode()) {
3107 unsigned Opc = Inst.getOpcode();
3184 Opcode = Inst.getOpcode();
3253 Opcode = Inst.getOpcode();
3432 unsigned LastOpcode = Inst.getOpcode();
3436 if (Match.empty() || LastOpcode != Inst.getOpcode())
3506 Opcode = Inst.getOpcode();
lib/Target/X86/Disassembler/X86Disassembler.cpp 821 if(mcInst.getOpcode() == X86::REP_PREFIX)
823 else if(mcInst.getOpcode() == X86::REPNE_PREFIX)
lib/Target/X86/MCTargetDesc/X86ATTInstPrinter.cpp 55 if (MI->getOpcode() == X86::CALLpcrel32 &&
65 else if (MI->getOpcode() == X86::DATA16_PREFIX &&
86 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
90 switch (MI->getOpcode()) {
lib/Target/X86/MCTargetDesc/X86AsmBackend.cpp 143 unsigned Op = Inst.getOpcode();
155 unsigned Op = Inst.getOpcode();
241 if (R != Inst.getOpcode())
268 if (getRelaxedOpcodeBranch(Inst, false) != Inst.getOpcode())
272 if (getRelaxedOpcodeArith(Inst) == Inst.getOpcode())
302 if (RelaxedOp == Inst.getOpcode()) {
lib/Target/X86/MCTargetDesc/X86InstComments.cpp 228 const MCInstrDesc &Desc = MCII.get(MI->getOpcode());
265 switch (MI->getOpcode()) {
510 switch (MI->getOpcode()) {
lib/Target/X86/MCTargetDesc/X86InstPrinterCommon.cpp 108 switch (MI->getOpcode()) {
127 switch (MI->getOpcode()) {
214 switch (MI->getOpcode()) {
323 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
lib/Target/X86/MCTargetDesc/X86IntelInstPrinter.cpp 45 if (MI->getOpcode() == X86::DATA16_PREFIX &&
67 const MCInstrDesc &Desc = MII.get(MI->getOpcode());
71 switch (MI->getOpcode()) {
lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp 283 unsigned Opcode = MI.getOpcode();
396 unsigned Opcode = MI.getOpcode();
566 unsigned Opcode = MI.getOpcode();
1215 unsigned Opcode = MI.getOpcode();
lib/Target/X86/MCTargetDesc/X86MCTargetDesc.cpp 418 const MCInstrDesc &Desc = Info->get(Inst.getOpcode());
527 const MCInstrDesc &MCID = Info->get(Inst.getOpcode());
lib/Target/X86/X86MCInstLower.cpp 318 switch (Inst.getOpcode()) {
473 switch (OutMI.getOpcode()) {
503 switch (OutMI.getOpcode()) {
528 switch (OutMI.getOpcode()) {
571 switch (OutMI.getOpcode()) {
642 switch (OutMI.getOpcode()) {
754 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode()));
760 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode()));
768 OutMI.setOpcode(convertTailJumpOpcode(OutMI.getOpcode()));
778 switch (OutMI.getOpcode()) {
805 switch (OutMI.getOpcode()) {
830 switch (OutMI.getOpcode()) {
tools/lldb/source/Plugins/Disassembler/llvm/DisassemblerLLVMC.cpp 1068 return m_instr_info_up->get(mc_inst.getOpcode())
1074 return m_instr_info_up->get(mc_inst.getOpcode()).hasDelaySlot();
1078 return m_instr_info_up->get(mc_inst.getOpcode()).isCall();
tools/lldb/source/Plugins/Instruction/MIPS/EmulateInstructionMIPS.cpp 995 return m_insn_info->get(mc_insn.getOpcode()).getSize();
1087 const char *op_name = m_insn_info->getName(mc_insn.getOpcode()).data();
1354 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
1806 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
1855 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
1856 uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
1935 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
2004 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
2054 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
2107 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
2108 uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
2165 uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
2192 uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
2193 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
2293 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
2332 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
2680 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
2796 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
tools/lldb/source/Plugins/Instruction/MIPS64/EmulateInstructionMIPS64.cpp 978 const char *op_name = m_insn_info->getName(mc_insn.getOpcode()).data();
1267 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
1346 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
1398 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
1508 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
1576 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
1661 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
1662 uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
1741 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
1742 uint32_t current_inst_size = m_insn_info->get(insn.getOpcode()).getSize();
1981 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
2106 const char *op_name = m_insn_info->getName(insn.getOpcode()).data();
tools/llvm-cfi-verify/lib/FileAnalysis.cpp 170 const auto &InstrDesc = MII->get(InstrMeta.Instruction.getOpcode());
175 const auto &InstrDesc = MII->get(InstrMeta.Instruction.getOpcode());
192 const auto &InstrDesc = MII->get(InstrMeta.Instruction.getOpcode());
207 const auto &InstrDesc = MII->get(InstrMeta.Instruction.getOpcode());
286 const auto &InstrDesc = MII->get(InstrMetaPtr->Instruction.getOpcode());
329 bool canLoad = !MII->get(IndirectCF.Instruction.getOpcode()).mayLoad();
338 const auto &InstrDesc = MII->get(NodeInstr.Instruction.getOpcode());
499 const auto &InstrDesc = MII->get(Instruction.getOpcode());
tools/llvm-cfi-verify/lib/GraphBuilder.cpp 235 Analysis.getMCInstrInfo()->get(ParentMeta.Instruction.getOpcode());
tools/llvm-exegesis/lib/Analysis.cpp 254 writeEscaped<kEscapeHtml>(OS, InstrInfo.getName(Instructions[0].getOpcode()));
270 writeEscaped<kEscapeHtml>(OS, InstrInfo.getName(Instr.getOpcode()));
tools/llvm-exegesis/lib/Assembler.cpp 94 const unsigned Opcode = Inst.getOpcode();
tools/llvm-exegesis/lib/BenchmarkResult.cpp 62 OS << getInstrName(MCInst.getOpcode());
tools/llvm-exegesis/lib/Clustering.cpp 192 const unsigned Opcode = Point.keyInstruction().getOpcode();
243 : Opcode(IB.keyInstruction().getOpcode()), Config(&IB.Key.Config) {}
tools/llvm-exegesis/lib/MCInstrDescView.cpp 364 OS << MCInstrInfo.getName(MCInst.getOpcode());
tools/llvm-exegesis/lib/SchedClassResolution.cpp 233 unsigned SchedClassId = InstrInfo.get(MCI.getOpcode()).getSchedClass();
tools/llvm-mca/Views/InstructionInfoView.cpp 41 const MCInstrDesc &MCDesc = MCII.get(Inst.getOpcode());
unittests/tools/llvm-exegesis/Common/AssemblerUtils.h 48 (Inst.getOpcode() == 0)
unittests/tools/llvm-exegesis/Mips/TargetTest.cpp 44 return Property(&MCInst::getOpcode, Eq(Opcode));
unittests/tools/llvm-exegesis/X86/SnippetFileTest.cpp 57 return Property(&MCInst::getOpcode, Eq(Opcode));
unittests/tools/llvm-exegesis/X86/TargetTest.cpp 33 if (a.getOpcode() != b.getOpcode())
33 if (a.getOpcode() != b.getOpcode())
74 return Property(&MCInst::getOpcode, Eq(Opcode));