|
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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
include/llvm/MC/MCDisassembler/MCDisassembler.h 123 const MCSubtargetInfo& getSubtargetInfo() const { return STI; }
lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp 269 return decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp 250 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
311 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
316 if (STI.getFeatureBits()[AMDGPU::FeatureUnpackedD16VMem]) {
325 if (STI.getFeatureBits()[AMDGPU::FeatureFmaMixInsts]) {
433 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
434 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
438 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
501 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
532 if (D16 && AMDGPU::hasPackedD16(STI)) {
568 if (STI.getFeatureBits()[AMDGPU::FeatureGFX10] && !IsNSA &&
620 return MCOperand::createReg(AMDGPU::getMCReg(RegId, STI));
1118 if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1119 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
1148 } else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
1165 assert((STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
1166 STI.getFeatureBits()[AMDGPU::FeatureGFX10]) &&
1169 bool IsWave64 = STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64];
1190 return STI.getFeatureBits()[AMDGPU::FeatureWavefrontSize64] ?
1195 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
1199 return STI.getFeatureBits()[AMDGPU::FeatureGFX9];
1203 return STI.getFeatureBits()[AMDGPU::FeatureGFX10];
lib/Target/ARC/Disassembler/ARCDisassembler.cpp 323 decodeInstruction(DecoderTable64, Instr, Insn64, Address, this, STI);
335 return decodeInstruction(DecoderTable32, Instr, Insn32, Address, this, STI);
343 decodeInstruction(DecoderTable48, Instr, Insn48, Address, this, STI);
358 return decodeInstruction(DecoderTable16, Instr, Insn16, Address, this, STI);
lib/Target/ARM/Disassembler/ARMDisassembler.cpp 614 if (STI.getFeatureBits()[ARM::ModeThumb])
626 assert(!STI.getFeatureBits()[ARM::ModeThumb] &&
642 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI);
661 Result = decodeInstruction(Table.P, MI, Insn, Address, this, STI);
673 decodeInstruction(DecoderTableCoProc32, MI, Insn, Address, this, STI);
913 assert(STI.getFeatureBits()[ARM::ModeThumb] &&
924 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI);
932 STI);
942 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI);
979 decodeInstruction(DecoderTableMVE32, MI, Insn32, Address, this, STI);
999 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI);
1009 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI);
1018 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI);
1027 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI);
1035 STI);
1048 Address, this, STI);
1062 Address, this, STI);
1074 Address, this, STI);
1083 this, STI);
1091 decodeInstruction(DecoderTableThumb2CoProc32, MI, Insn32, Address, this, STI);
lib/Target/AVR/Disassembler/AVRDisassembler.cpp 131 Insn, Address, this, STI);
144 Address, this, STI);
lib/Target/BPF/Disassembler/BPFDisassembler.cpp 179 STI.getFeatureBits()[BPF::ALU32])
181 this, STI);
184 STI);
lib/Target/Hexagon/Disassembler/HexagonDisassembler.cpp 191 HexagonMCChecker Checker(getContext(), *MCII, STI, MI,
391 this, STI);
397 DecodeHigh, *MIHigh, (Instruction >> 16) & 0x1fff, Address, this, STI);
413 Address, this, STI);
417 STI);
420 STI.getFeatureBits()[Hexagon::ExtensionHVX])
422 Address, this, STI);
lib/Target/Lanai/Disassembler/LanaiDisassembler.cpp 143 decodeInstruction(DecoderTableLanai32, Instr, Insn, Address, this, STI);
lib/Target/MSP430/Disassembler/MSP430Disassembler.cpp 279 Insn, Address, this, STI);
320 this, STI);
lib/Target/Mips/Disassembler/MipsDisassembler.cpp 50 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
51 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
52 bool hasMips32() const { return STI.getFeatureBits()[Mips::FeatureMips32]; }
55 return STI.getFeatureBits()[Mips::FeatureMips32r6];
58 bool isFP64() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
60 bool isGP64() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
62 bool isPTR64() const { return STI.getFeatureBits()[Mips::FeaturePTR64Bit]; }
64 bool hasCnMips() const { return STI.getFeatureBits()[Mips::FeatureCnMips]; }
1234 Address, this, STI);
1245 this, STI);
1260 this, STI);
1270 this, STI);
1279 Address, this, STI);
1308 decodeInstruction(DecoderTableCOP3_32, Instr, Insn, Address, this, STI);
1317 Address, this, STI);
1326 Address, this, STI);
1334 Address, this, STI);
1343 Address, this, STI);
1351 Address, this, STI);
1359 Address, this, STI);
1368 Address, this, STI);
1376 decodeInstruction(DecoderTableMips32, Instr, Insn, Address, this, STI);
lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp 339 if (STI.getFeatureBits()[PPC::FeatureQPX]) {
341 decodeInstruction(DecoderTableQPX32, MI, Inst, Address, this, STI);
344 } else if (STI.getFeatureBits()[PPC::FeatureSPE]) {
346 decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
351 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp 333 Result = decodeInstruction(DecoderTable32, MI, Insn, Address, this, STI);
342 if (!STI.getFeatureBits()[RISCV::Feature64Bit]) {
347 this, STI);
356 Result = decodeInstruction(DecoderTable16, MI, Insn, Address, this, STI);
lib/Target/Sparc/Disassembler/SparcDisassembler.cpp 346 if (STI.getFeatureBits()[Sparc::FeatureV9])
348 Result = decodeInstruction(DecoderTableSparcV932, Instr, Insn, Address, this, STI);
352 Result = decodeInstruction(DecoderTableSparcV832, Instr, Insn, Address, this, STI);
358 decodeInstruction(DecoderTableSparc32, Instr, Insn, Address, this, STI);
lib/Target/SystemZ/Disassembler/SystemZDisassembler.cpp 481 return decodeInstruction(Table, MI, Inst, Address, this, STI);
lib/Target/XCore/Disassembler/XCoreDisassembler.cpp 749 Address, this, STI);
762 Result = decodeInstruction(DecoderTable32, instr, insn32, Address, this, STI);