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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/CalcSpillWeights.h 22 class VirtRegMap;
include/llvm/CodeGen/LiveIntervals.h 52 class VirtRegMap;
include/llvm/CodeGen/LiveRangeEdit.h 43 class VirtRegMap;
include/llvm/CodeGen/LiveRegMatrix.h 38 class VirtRegMap;
include/llvm/CodeGen/TargetRegisterInfo.h 41 class VirtRegMap;
lib/CodeGen/AllocationOrder.h 26 class VirtRegMap;
lib/CodeGen/LiveDebugVariables.h 30 class VirtRegMap;
lib/CodeGen/RegAllocBase.h 52 class VirtRegMap;
lib/CodeGen/Spiller.h 17 class VirtRegMap;
lib/CodeGen/SplitKit.h 45 class VirtRegMap;
References
include/llvm/CodeGen/CalcSpillWeights.h 53 VirtRegMap *VRM;
61 VirtRegMap *vrm, const MachineLoopInfo &loops,
99 VirtRegMap *VRM,
include/llvm/CodeGen/LiveIntervals.h 304 void addKillFlags(const VirtRegMap*);
include/llvm/CodeGen/LiveRangeEdit.h 74 VirtRegMap *VRM;
139 MachineFunction &MF, LiveIntervals &lis, VirtRegMap *vrm,
include/llvm/CodeGen/LiveRegMatrix.h 43 VirtRegMap *VRM;
include/llvm/CodeGen/TargetInstrInfo.h 1005 VirtRegMap *VRM = nullptr) const;
include/llvm/CodeGen/TargetRegisterInfo.h 784 const VirtRegMap *VRM = nullptr,
include/llvm/CodeGen/VirtRegMap.h 74 VirtRegMap(const VirtRegMap &) = delete;
75 VirtRegMap &operator=(const VirtRegMap &) = delete;
75 VirtRegMap &operator=(const VirtRegMap &) = delete;
183 inline raw_ostream &operator<<(raw_ostream &OS, const VirtRegMap &VRM) {
include/llvm/Pass.h 213 AnalysisType &getAnalysisID(AnalysisID PI) const;
include/llvm/PassAnalysisSupport.h 66 return addRequiredID(PassClass::ID);
72 return addRequiredTransitiveID(PassClass::ID);
89 Preserved.push_back(&PassClass::ID);
201 AnalysisType *Pass::getAnalysisIfAvailable() const {
204 const void *PI = &AnalysisType::ID;
220 AnalysisType &Pass::getAnalysis() const {
222 return getAnalysisID<AnalysisType>(&AnalysisType::ID);
222 return getAnalysisID<AnalysisType>(&AnalysisType::ID);
include/llvm/PassSupport.h 76 template <typename PassName> Pass *callDefaultCtor() { return new PassName(); }
lib/CodeGen/AllocationOrder.cpp 30 const VirtRegMap &VRM,
lib/CodeGen/AllocationOrder.h 44 const VirtRegMap &VRM,
lib/CodeGen/CalcSpillWeights.cpp 33 VirtRegMap *VRM,
87 VirtRegMap *VRM,
lib/CodeGen/InlineSpiller.cpp 92 VirtRegMap &VRM;
140 VirtRegMap &vrm)
165 VirtRegMap &VRM;
196 InlineSpiller(MachineFunctionPass &pass, MachineFunction &mf, VirtRegMap &vrm)
243 VirtRegMap &vrm) {
1065 if (StackSlot == VirtRegMap::NO_STACK_SLOT) {
1536 else if (VRM.getStackSlot(Old) != VirtRegMap::NO_STACK_SLOT)
lib/CodeGen/LiveDebugVariables.cpp 314 void rewriteLocations(VirtRegMap &VRM, const MachineFunction &MF,
320 void emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
473 void emitDebugValues(VirtRegMap *VRM);
1152 void UserValue::rewriteLocations(VirtRegMap &VRM, const MachineFunction &MF,
1180 } else if (VRM.getStackSlot(VirtReg) != VirtRegMap::NO_STACK_SLOT) {
1337 void UserValue::emitDebugValues(VirtRegMap *VRM, LiveIntervals &LIS,
1389 void LDVImpl::emitDebugValues(VirtRegMap *VRM) {
1408 void LiveDebugVariables::emitDebugValues(VirtRegMap *VRM) {
lib/CodeGen/LiveDebugVariables.h 50 void emitDebugValues(VirtRegMap *VRM);
lib/CodeGen/LiveIntervals.cpp 683 void LiveIntervals::addKillFlags(const VirtRegMap *VRM) {
lib/CodeGen/LiveRegMatrix.cpp 50 AU.addRequiredTransitive<VirtRegMap>();
57 VRM = &getAnalysis<VirtRegMap>();
lib/CodeGen/RegAllocBase.cpp 57 void RegAllocBase::init(VirtRegMap &vrm,
lib/CodeGen/RegAllocBase.h 66 VirtRegMap *VRM = nullptr;
81 void init(VirtRegMap &vrm, LiveIntervals &lis, LiveRegMatrix &mat);
lib/CodeGen/RegAllocBasic.cpp 189 AU.addRequired<VirtRegMap>();
190 AU.addPreserved<VirtRegMap>();
310 RegAllocBase::init(getAnalysis<VirtRegMap>(),
lib/CodeGen/RegAllocGreedy.cpp 622 AU.addRequired<VirtRegMap>();
623 AU.addPreserved<VirtRegMap>();
3229 RegAllocBase::init(getAnalysis<VirtRegMap>(),
lib/CodeGen/RegAllocPBQP.cpp 166 void initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM, Spiller &VRegSpiller);
170 MachineFunction &MF, LiveIntervals &LIS, VirtRegMap &VRM,
177 VirtRegMap &VRM,
183 VirtRegMap &VRM) const;
550 au.addRequired<VirtRegMap>();
551 au.addPreserved<VirtRegMap>();
577 void RegAllocPBQP::initializeGraph(PBQPRAGraph &G, VirtRegMap &VRM,
679 VirtRegMap &VRM, Spiller &VRegSpiller) {
705 VirtRegMap &VRM,
744 VirtRegMap &VRM) const {
794 VirtRegMap &VRM = getAnalysis<VirtRegMap>();
794 VirtRegMap &VRM = getAnalysis<VirtRegMap>();
lib/CodeGen/Spiller.h 39 VirtRegMap &vrm);
lib/CodeGen/SplitKit.cpp 151 SplitAnalysis::SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
366 LiveIntervals &lis, VirtRegMap &vrm,
lib/CodeGen/SplitKit.h 98 const VirtRegMap &VRM;
168 SplitAnalysis(const VirtRegMap &vrm, const LiveIntervals &lis,
261 VirtRegMap &VRM;
446 VirtRegMap &vrm, MachineDominatorTree &mdt,
lib/CodeGen/TargetInstrInfo.cpp 534 VirtRegMap *VRM) const {
lib/CodeGen/TargetRegisterInfo.cpp 387 const VirtRegMap *VRM,
lib/CodeGen/VirtRegMap.cpp 141 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
150 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
182 VirtRegMap *VRM;
231 AU.addRequired<VirtRegMap>();
242 VRM = &getAnalysis<VirtRegMap>();
lib/Target/AMDGPU/GCNNSAReassign.cpp 54 AU.addRequired<VirtRegMap>();
75 VirtRegMap *VRM;
230 VRM = &getAnalysis<VirtRegMap>();
lib/Target/AMDGPU/GCNRegBankReassign.cpp 130 AU.addRequired<VirtRegMap>();
145 VirtRegMap *VRM;
735 VRM = &getAnalysis<VirtRegMap>();
lib/Target/AMDGPU/SILowerSGPRSpills.cpp 50 VirtRegMap *VRM = nullptr;
235 VRM = getAnalysisIfAvailable<VirtRegMap>();
lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp 42 VirtRegMap *VRM;
59 AU.addRequired<VirtRegMap>();
174 VRM = &getAnalysis<VirtRegMap>();
lib/Target/ARM/ARMBaseRegisterInfo.cpp 305 const VirtRegMap *VRM,
lib/Target/ARM/ARMBaseRegisterInfo.h 156 const VirtRegMap *VRM,
lib/Target/SystemZ/SystemZRegisterInfo.cpp 30 const VirtRegMap *VRM,
81 const VirtRegMap *VRM,
lib/Target/SystemZ/SystemZRegisterInfo.h 65 const VirtRegMap *VRM,