reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
1806 if (!RC->hasSuperClassEq(DRC)) {
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp109 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass); 116 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) && 118 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
104 return RC->hasSuperClassEq(TRI.getBoolRC()) &&
lib/Target/AMDGPU/SIInstrInfo.cpp 3935 return RC->hasSuperClassEq(DRC);
lib/Target/ARM/A15SDOptimizer.cpp139 return MRI->getRegClass(Reg)->hasSuperClassEq(TRC); 273 if (TRC->hasSuperClassEq(MRI->getRegClass(FullReg))) { 518 if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::QPRRegClass) || 519 MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPairRegClass)) { 535 } else if (MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::DPRRegClass)) { 541 assert(MRI->getRegClass(Reg)->hasSuperClassEq(&ARM::SPRRegClass) &&lib/Target/ARM/Thumb1InstrInfo.cpp
111 (RC->hasSuperClassEq(&ARM::tGPRRegClass) || 115 if (RC->hasSuperClassEq(&ARM::tGPRRegClass) ||lib/Target/PowerPC/PPCFastISel.cpp
476 bool Is32BitInt = UseRC->hasSuperClassEq(&PPC::GPRCRegClass); 496 assert(UseRC->hasSuperClassEq(&PPC::G8RCRegClass) && 630 bool Is32BitInt = RC->hasSuperClassEq(&PPC::GPRCRegClass); 1284 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass); 2117 bool IsGPRC = RC->hasSuperClassEq(&PPC::GPRCRegClass);lib/Target/PowerPC/PPCInstrInfo.cpp
192 IsRegCR = MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRRCRegClass) || 193 MRI->getRegClass(Reg)->hasSuperClassEq(&PPC::CRBITRCRegClass); 3839 MRI.getRegClass(RegToModify)->hasSuperClassEq(&PPC::GPRCRegClass) ?lib/Target/SystemZ/SystemZRegisterInfo.cpp
346 if (!(NewRC->hasSuperClassEq(&SystemZ::GR128BitRegClass) &&
lib/Target/X86/X86ISelLowering.cpp45758 return RC.hasSuperClassEq(&X86::GR8RegClass) || 45759 RC.hasSuperClassEq(&X86::GR16RegClass) || 45760 RC.hasSuperClassEq(&X86::GR32RegClass) || 45761 RC.hasSuperClassEq(&X86::GR64RegClass) || 45762 RC.hasSuperClassEq(&X86::LOW32_ADDR_ACCESS_RBPRegClass); 45768 return RC.hasSuperClassEq(&X86::FR32XRegClass) || 45769 RC.hasSuperClassEq(&X86::FR64XRegClass) || 45770 RC.hasSuperClassEq(&X86::VR128XRegClass) || 45771 RC.hasSuperClassEq(&X86::VR256XRegClass) || 45772 RC.hasSuperClassEq(&X86::VR512RegClass); 45778 return RC.hasSuperClassEq(&X86::VK1RegClass) || 45779 RC.hasSuperClassEq(&X86::VK2RegClass) || 45780 RC.hasSuperClassEq(&X86::VK4RegClass) || 45781 RC.hasSuperClassEq(&X86::VK8RegClass) || 45782 RC.hasSuperClassEq(&X86::VK16RegClass) || 45783 RC.hasSuperClassEq(&X86::VK32RegClass) || 45784 RC.hasSuperClassEq(&X86::VK64RegClass);lib/Target/X86/X86RegisterInfo.cpp
226 if (DefRC->hasSuperClassEq(&X86::GR64RegClass) && DefSubReg == 0 && 227 SrcRC->hasSuperClassEq(&X86::GR64RegClass) && SrcSubReg == X86::sub_32bit)lib/Target/X86/X86SpeculativeLoadHardening.cpp
2040 if (!Subtarget->hasVLX() && (OpRC->hasSuperClassEq(&X86::VR128RegClass) || 2041 OpRC->hasSuperClassEq(&X86::VR256RegClass))) { 2043 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128RegClass); 2077 } else if (OpRC->hasSuperClassEq(&X86::VR128XRegClass) || 2078 OpRC->hasSuperClassEq(&X86::VR256XRegClass) || 2079 OpRC->hasSuperClassEq(&X86::VR512RegClass)) { 2081 bool Is128Bit = OpRC->hasSuperClassEq(&X86::VR128XRegClass); 2082 bool Is256Bit = OpRC->hasSuperClassEq(&X86::VR256XRegClass); 2110 assert(OpRC->hasSuperClassEq(&X86::GR64RegClass) && 2263 return RC->hasSuperClassEq(GPRRegClasses[RegIdx]);