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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/CodeGen/AggressiveAntiDepBreaker.cpp 668 NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
lib/CodeGen/CalcSpillWeights.cpp 73 Register CopiedPReg = (hsub ? tri.getSubReg(hreg, hsub) : hreg);
lib/CodeGen/ExpandPostRAPseudos.cpp 88 Register DstSubReg = TRI->getSubReg(DstReg, SubIdx);
lib/CodeGen/MachineInstr.cpp 1144 ToReg = RegInfo.getSubReg(ToReg, SubIdx);
lib/CodeGen/MachineOperand.cpp 87 Reg = TRI.getSubReg(Reg, getSubReg());
lib/CodeGen/RegAllocFast.cpp 769 PhysReg = TRI->getSubReg(PhysReg, SubRegIdx);
865 MO.setReg(PhysReg ? TRI->getSubReg(PhysReg, MO.getSubReg()) : Register());
lib/CodeGen/RegisterCoalescer.cpp 422 Dst = TRI.getSubReg(Dst, DstSub);
516 Dst = TRI.getSubReg(Dst, DstSub);
521 return TRI.getSubReg(DstReg, SrcSub) == Dst;
1263 NewDstReg = TRI->getSubReg(DstReg, NewDstIdx);
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 546 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
lib/CodeGen/VirtRegMap.cpp 563 PhysReg = TRI->getSubReg(PhysReg, SubReg);
lib/Target/AArch64/AArch64AsmPrinter.cpp 760 STI->getRegisterInfo()->getSubReg(ScratchReg, AArch64::sub_32);
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 506 unsigned Reg32 = TRI->getSubReg(DstReg, AArch64::sub_32);
lib/Target/AArch64/AArch64InstrInfo.cpp 1512 unsigned Reg32 = TRI->getSubReg(Reg, AArch64::sub_32);
1554 unsigned Reg32 = TRI->getSubReg(Reg, AArch64::sub_32);
2399 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
2792 SrcReg0 = TRI.getSubReg(SrcReg, SubIdx0);
2794 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1);
2922 DestReg0 = TRI.getSubReg(DestReg, SubIdx0);
2924 DestReg1 = TRI.getSubReg(DestReg, SubIdx1);
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 906 Register DstRegW = TRI->getSubReg(DstRegX, AArch64::sub_32);
lib/Target/AMDGPU/GCNRegBankReassign.cpp 283 Reg = TRI->getSubReg(Reg, AMDGPU::sub0);
304 Reg = TRI->getSubReg(Reg, SubReg);
310 Reg = TRI->getSubReg(Reg, AMDGPU::sub0);
447 PhysReg = TRI->getSubReg(PhysReg, AMDGPU::sub0);
lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp 223 Src0 = TRI.getSubReg(Src0, SubRegIndex);
224 Src1 = TRI.getSubReg(Src1, SubRegIndex);
229 Src1 = TRI.getSubReg(Src0, SubRegIndex1);
230 Src0 = TRI.getSubReg(Src0, SubRegIndex0);
238 DstReg = TRI.getSubReg(DstReg, SubRegIndex);
lib/Target/AMDGPU/R600InstrInfo.cpp 82 RI.getSubReg(DestReg, SubRegIndex),
83 RI.getSubReg(SrcReg, SubRegIndex))
lib/Target/AMDGPU/SIFrameLowering.cpp 216 Register FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0);
217 Register FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1);
546 Register RsrcLo = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
547 Register RsrcHi = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
548 Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
608 Register Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
609 Register Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
615 Register Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
647 Register Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
648 Register Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
lib/Target/AMDGPU/SIInstrInfo.cpp 715 copyPhysReg(MBB, MI, DL, RI.getSubReg(DestReg, SubIdx),
716 RI.getSubReg(SrcReg, SubIdx), KillSrc);
721 get(Opcode), RI.getSubReg(DestReg, SubIdx));
723 Builder.addReg(RI.getSubReg(SrcReg, SubIdx));
802 get(Opcode), RI.getSubReg(DestReg, Idx));
1420 Register DstLo = RI.getSubReg(Dst, AMDGPU::sub0);
1421 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1);
1437 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
1440 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
1489 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
1506 Register RegLo = RI.getSubReg(Reg, AMDGPU::sub0);
1507 Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1);
1579 MovDPP.addDef(RI.getSubReg(Dst, Sub));
1597 MovDPP.addReg(RI.getSubReg(Src, Sub));
lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp 137 PhysReg = TRI->getSubReg(PhysReg, SubReg);
lib/Target/AMDGPU/SIRegisterInfo.cpp 689 : getSubReg(ValueReg, getSubRegFromChannel(i));
790 NumSubRegs == 1 ? SuperReg : getSubReg(SuperReg, SplitParts[i]);
898 NumSubRegs == 1 ? SuperReg : getSubReg(SuperReg, SplitParts[i]);
lib/Target/AMDGPU/SIShrinkInstructions.cpp 427 Reg = TRI.getSubReg(Reg, TRI.getSubRegFromChannel(I));
lib/Target/ARM/ARMAsmPrinter.cpp 212 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
285 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
312 Register Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
314 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
382 TRI->getSubReg(MO.getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1);
408 TRI->getSubReg(Reg, ExtraCode[0] == 'e' ? ARM::dsub_0 : ARM::dsub_1);
425 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
lib/Target/ARM/ARMBaseInstrInfo.cpp 961 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
969 Register Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
970 Register Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
1023 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
4912 ImplicitSReg = TRI->getSubReg(DReg,
lib/Target/ARM/ARMExpandPseudoInsts.cpp 439 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
440 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
441 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
442 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
444 D0 = TRI->getSubReg(Reg, ARM::dsub_4);
445 D1 = TRI->getSubReg(Reg, ARM::dsub_5);
446 D2 = TRI->getSubReg(Reg, ARM::dsub_6);
447 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
449 D0 = TRI->getSubReg(Reg, ARM::dsub_3);
450 D1 = TRI->getSubReg(Reg, ARM::dsub_4);
451 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
452 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
454 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
455 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
456 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
457 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
460 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
461 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
462 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
463 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
495 Register SubReg = TRI->getSubReg(DstReg, SubRegIndex);
1039 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
1040 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1);
1064 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);
1065 Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);
1066 Register DesiredLo = TRI->getSubReg(DesiredReg, ARM::gsub_0);
1067 Register DesiredHi = TRI->getSubReg(DesiredReg, ARM::gsub_1);
1604 Register D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1605 Register D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1636 Register D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1637 Register D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
lib/Target/AVR/AVRAsmPrinter.cpp 121 Reg = TRI.getSubReg(Reg, ByteNumber % BytesPerReg ? AVR::sub_hi
lib/Target/AVR/AVRFrameLowering.cpp 334 .addReg(TRI.getSubReg(SrcReg, AVR::sub_hi),
337 .addReg(TRI.getSubReg(SrcReg, AVR::sub_lo),
lib/Target/AVR/AVRRegisterInfo.cpp 272 LoReg = getSubReg(Reg, AVR::sub_lo);
273 HiReg = getSubReg(Reg, AVR::sub_hi);
lib/Target/BPF/BPFMIPeephole.cpp 265 dst = TRI->getSubReg(dst, BPF::sub_32);
lib/Target/Hexagon/BitTracker.cpp 344 (RR.Sub == 0) ? Register(RR.Reg) : TRI.getSubReg(RR.Reg, RR.Sub);
lib/Target/Hexagon/HexagonAsmPrinter.cpp 136 RegNumber = TRI->getSubReg(RegNumber, ExtraCode[0] == 'L' ?
lib/Target/Hexagon/HexagonExpandCondsets.cpp 592 Register PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
lib/Target/Hexagon/HexagonFrameLowering.cpp 976 Register HiReg = HRI.getSubReg(Reg, Hexagon::isub_hi);
977 Register LoReg = HRI.getSubReg(Reg, Hexagon::isub_lo);
1749 Register SrcLo = HRI.getSubReg(SrcR, Hexagon::vsub_lo);
1750 Register SrcHi = HRI.getSubReg(SrcR, Hexagon::vsub_hi);
1797 Register DstHi = HRI.getSubReg(DstR, Hexagon::vsub_hi);
1798 Register DstLo = HRI.getSubReg(DstR, Hexagon::vsub_lo);
2284 SrcOp.setReg(HRI.getSubReg(FoundR, SR));
lib/Target/Hexagon/HexagonInstrInfo.cpp 127 return isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_lo)) &&
128 isIntRegForSubInst(HRI.getSubReg(Reg, Hexagon::isub_hi));
852 Register LoSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
853 Register HiSrc = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1066 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
1067 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
1074 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1083 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1093 Register SrcSubHi = HRI.getSubReg(SrcReg, Hexagon::vsub_hi);
1094 Register SrcSubLo = HRI.getSubReg(SrcReg, Hexagon::vsub_lo);
1121 HRI.getSubReg(DstReg, Hexagon::vsub_lo))
1126 BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1177 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1178 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1179 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1180 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1182 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1186 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1202 Register Src1SubHi = HRI.getSubReg(Src1Reg, Hexagon::isub_hi);
1203 Register Src1SubLo = HRI.getSubReg(Src1Reg, Hexagon::isub_lo);
1204 Register Src2SubHi = HRI.getSubReg(Src2Reg, Hexagon::isub_hi);
1205 Register Src2SubLo = HRI.getSubReg(Src2Reg, Hexagon::isub_lo);
1206 Register Src3SubHi = HRI.getSubReg(Src3Reg, Hexagon::isub_hi);
1207 Register Src3SubLo = HRI.getSubReg(Src3Reg, Hexagon::isub_lo);
1209 HRI.getSubReg(DstReg, Hexagon::isub_hi))
1214 HRI.getSubReg(DstReg, Hexagon::isub_lo))
1300 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1301 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1312 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1313 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp 89 Register DestLo = TRI->getSubReg(DestReg, Hexagon::isub_lo);
90 Register DestHi = TRI->getSubReg(DestReg, Hexagon::isub_hi);
lib/Target/Hexagon/RDFGraph.cpp 969 Reg = TRI.getSubReg(Reg, Sub);
lib/Target/Mips/MipsSEFrameLowering.cpp 210 Register Lo = RegInfo.getSubReg(Dst, Mips::sub_lo);
211 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi);
268 Register DstLo = RegInfo.getSubReg(Dst, Mips::sub_lo);
269 Register DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi);
464 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_lo), true);
466 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true);
lib/Target/Mips/MipsSEInstrInfo.cpp 738 Register DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
739 Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
763 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
766 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
783 Register SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
847 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
871 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
lib/Target/PowerPC/PPCQPXLoadSplat.cpp 105 Register SplatSubReg = TRI->getSubReg(SplatReg, SubRegIndex);
lib/Target/Sparc/SparcInstrInfo.cpp 378 Register Dst = TRI->getSubReg(DestReg, subRegIdx[i]);
379 Register Src = TRI->getSubReg(SrcReg, subRegIdx[i]);
lib/Target/Sparc/SparcRegisterInfo.cpp 186 Register SrcEvenReg = getSubReg(SrcReg, SP::sub_even64);
187 Register SrcOddReg = getSubReg(SrcReg, SP::sub_odd64);
198 Register DestEvenReg = getSubReg(DestReg, SP::sub_even64);
199 Register DestOddReg = getSubReg(DestReg, SP::sub_odd64);
lib/Target/SystemZ/SystemZFrameLowering.cpp 121 Register GPR32 = RI->getSubReg(GPR64, SystemZ::subreg_l32);
lib/Target/SystemZ/SystemZInstrInfo.cpp 81 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
82 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
215 const Register Reg32 = RI.getSubReg(Reg64, SystemZ::subreg_l32);
774 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
775 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
778 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
779 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
795 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_h64),
798 RI.getMatchingSuperReg(RI.getSubReg(SrcReg, SystemZ::subreg_l64),
809 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_h64),
812 RI.getMatchingSuperReg(RI.getSubReg(DestReg, SystemZ::subreg_l64),
lib/Target/SystemZ/SystemZRegisterInfo.cpp 176 PhysReg = getSubReg(PhysReg, MO->getSubReg());
lib/Target/SystemZ/SystemZShortenInst.cpp 89 Register OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx);
lib/Target/X86/X86FixupLEAs.cpp 378 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
380 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit);
553 BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
555 IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit);
lib/Target/X86/X86InstrInfo.cpp 4109 Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4137 Register XReg = TRI->getSubReg(SrcReg, X86::sub_xmm);
4213 Register Reg32 = RI.getSubReg(Reg, X86::sub_32bit);
4585 Register XReg = TRI->getSubReg(Reg, X86::sub_xmm);
4594 Register XReg = TRI->getSubReg(Reg, X86::sub_32bit);
4930 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
lib/Target/X86/X86MCInstLower.cpp 1902 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0);
1903 Register Reg1 = RI->getSubReg(Reg, X86::sub_mask_1);
1933 Register Reg0 = RI->getSubReg(Reg, X86::sub_mask_0);
1934 Register Reg1 = RI->getSubReg(Reg, X86::sub_mask_1);