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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Derived Classes
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 5027 struct AArch64GenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc17300 struct AMDGPUGenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/AMDGPU/R600GenRegisterInfo.inc 8787 struct R600GenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/ARC/ARCGenRegisterInfo.inc 510 struct ARCGenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 3579 struct ARMGenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/AVR/AVRGenRegisterInfo.inc 854 struct AVRGenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/BPF/BPFGenRegisterInfo.inc 384 struct BPFGenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 2269 struct HexagonGenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/Lanai/LanaiGenRegisterInfo.inc 565 struct LanaiGenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/MSP430/MSP430GenRegisterInfo.inc 309 struct MSP430GenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 3807 struct MipsGenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc 756 struct NVPTXGenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 3841 struct PPCGenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc 1112 struct RISCVGenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/Sparc/SparcGenRegisterInfo.inc 1885 struct SparcGenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc 1779 struct SystemZGenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc 255 struct WebAssemblyGenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/X86/X86GenRegisterInfo.inc 4309 struct X86GenRegisterInfo : public TargetRegisterInfo {
gen/lib/Target/XCore/XCoreGenRegisterInfo.inc 331 struct XCoreGenRegisterInfo : public TargetRegisterInfo {
unittests/CodeGen/MachineInstrTest.cpp 52 class BogusRegisterInfo : public TargetRegisterInfo {
Declarations
include/llvm/CodeGen/CallingConvLower.h 30 class TargetRegisterInfo;
include/llvm/CodeGen/DbgEntityHistoryCalculator.h 23 class TargetRegisterInfo;
include/llvm/CodeGen/FastISel.h 58 class TargetRegisterInfo;
include/llvm/CodeGen/GlobalISel/InstructionSelector.h 43 class TargetRegisterInfo;
include/llvm/CodeGen/GlobalISel/RegBankSelect.h 86 class TargetRegisterInfo;
include/llvm/CodeGen/GlobalISel/RegisterBank.h 23 class TargetRegisterInfo;
include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h 35 class TargetRegisterInfo;
include/llvm/CodeGen/GlobalISel/Utils.h 35 class TargetRegisterInfo;
include/llvm/CodeGen/LiveIntervalUnion.h 29 class TargetRegisterInfo;
include/llvm/CodeGen/LiveRangeEdit.h 42 class TargetRegisterInfo;
include/llvm/CodeGen/LiveRegMatrix.h 37 class TargetRegisterInfo;
include/llvm/CodeGen/LiveStacks.h 28 class TargetRegisterInfo;
include/llvm/CodeGen/MachineBasicBlock.h 46 class TargetRegisterInfo;
include/llvm/CodeGen/MachineInstr.h 54 class TargetRegisterInfo;
include/llvm/CodeGen/MachineOperand.h 38 class TargetRegisterInfo;
include/llvm/CodeGen/MachineScheduler.h 115 class TargetRegisterInfo;
include/llvm/CodeGen/MachineTraceMetrics.h 69 class TargetRegisterInfo;
include/llvm/CodeGen/RegisterScavenging.h 32 class TargetRegisterInfo;
include/llvm/CodeGen/ScheduleDAG.h 45 class TargetRegisterInfo;
include/llvm/CodeGen/StackMaps.h 29 class TargetRegisterInfo;
include/llvm/CodeGen/TailDuplicator.h 33 class TargetRegisterInfo;
include/llvm/CodeGen/TargetInstrInfo.h 59 class TargetRegisterInfo;
include/llvm/CodeGen/TargetLowering.h 91 class TargetRegisterInfo;
include/llvm/CodeGen/TargetSubtargetInfo.h 52 class TargetRegisterInfo;
lib/CodeGen/AggressiveAntiDepBreaker.h 37 class TargetRegisterInfo;
lib/CodeGen/AsmPrinter/DwarfExpression.h 32 class TargetRegisterInfo;
lib/CodeGen/BranchFolding.h 32 class TargetRegisterInfo;
lib/CodeGen/CriticalAntiDepBreaker.h 34 class TargetRegisterInfo;
lib/CodeGen/InterferenceCache.h 30 class TargetRegisterInfo;
lib/CodeGen/RegAllocBase.h 51 class TargetRegisterInfo;
lib/CodeGen/RegisterCoalescer.h 21 class TargetRegisterInfo;
lib/CodeGen/SplitKit.h 44 class TargetRegisterInfo;
lib/Target/AArch64/AArch64PBQPRegAlloc.h 17 class TargetRegisterInfo;
lib/Target/AArch64/AArch64RegisterBankInfo.h 23 class TargetRegisterInfo;
lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h 24 class TargetRegisterInfo;
lib/Target/AMDGPU/AMDGPURegisterBankInfo.h 32 class TargetRegisterInfo;
lib/Target/ARM/ARMISelLowering.h 49 class TargetRegisterInfo;
lib/Target/ARM/ARMRegisterBankInfo.h 23 class TargetRegisterInfo;
lib/Target/Hexagon/BitTracker.h 33 class TargetRegisterInfo;
lib/Target/Hexagon/HexagonBlockRanges.h 28 class TargetRegisterInfo;
lib/Target/Hexagon/HexagonInstrInfo.h 36 class TargetRegisterInfo;
lib/Target/Hexagon/RDFGraph.h 256 class TargetRegisterInfo;
lib/Target/Hexagon/RDFLiveness.h 29 class TargetRegisterInfo;
lib/Target/Mips/MipsInstrInfo.h 39 class TargetRegisterInfo;
lib/Target/Mips/MipsRegisterBankInfo.h 23 class TargetRegisterInfo;
lib/Target/RISCV/RISCVRegisterBankInfo.h 23 class TargetRegisterInfo;
lib/Target/X86/X86RegisterBankInfo.h 40 class TargetRegisterInfo;
References
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 5027 struct AArch64GenRegisterInfo : public TargetRegisterInfo {
5299 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc17300 struct AMDGPUGenRegisterInfo : public TargetRegisterInfo {
17682 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/AMDGPU/R600GenRegisterInfo.inc 8787 struct R600GenRegisterInfo : public TargetRegisterInfo {
8900 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/ARC/ARCGenRegisterInfo.inc 510 struct ARCGenRegisterInfo : public TargetRegisterInfo {
567 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 3579 struct ARMGenRegisterInfo : public TargetRegisterInfo {
3824 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/AVR/AVRGenRegisterInfo.inc 854 struct AVRGenRegisterInfo : public TargetRegisterInfo {
932 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/BPF/BPFGenRegisterInfo.inc 384 struct BPFGenRegisterInfo : public TargetRegisterInfo {
445 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 2269 struct HexagonGenRegisterInfo : public TargetRegisterInfo {
2370 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/Lanai/LanaiGenRegisterInfo.inc 565 struct LanaiGenRegisterInfo : public TargetRegisterInfo {
626 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/MSP430/MSP430GenRegisterInfo.inc 309 struct MSP430GenRegisterInfo : public TargetRegisterInfo {
370 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 3807 struct MipsGenRegisterInfo : public TargetRegisterInfo {
3955 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc 756 struct NVPTXGenRegisterInfo : public TargetRegisterInfo {
829 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 3841 struct PPCGenRegisterInfo : public TargetRegisterInfo {
3947 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc 1112 struct RISCVGenRegisterInfo : public TargetRegisterInfo {
1185 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/Sparc/SparcGenRegisterInfo.inc 1885 struct SparcGenRegisterInfo : public TargetRegisterInfo {
1967 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc 1779 struct SystemZGenRegisterInfo : public TargetRegisterInfo {
1872 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc 255 struct WebAssemblyGenRegisterInfo : public TargetRegisterInfo {
319 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/X86/X86GenRegisterInfo.inc 4309 struct X86GenRegisterInfo : public TargetRegisterInfo {
4513 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
gen/lib/Target/XCore/XCoreGenRegisterInfo.inc 331 struct XCoreGenRegisterInfo : public TargetRegisterInfo {
386 static const TargetRegisterInfo::RegClassInfo RegClassInfos[] = {
include/llvm/CodeGen/CallingConvLower.h 197 const TargetRegisterInfo &TRI;
include/llvm/CodeGen/DbgEntityHistoryCalculator.h 122 const TargetRegisterInfo *TRI,
include/llvm/CodeGen/ExecutionDomainFix.h 114 const TargetRegisterInfo *TRI;
include/llvm/CodeGen/FastISel.h 213 const TargetRegisterInfo &TRI;
include/llvm/CodeGen/GlobalISel/InstructionSelector.h 452 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
484 const TargetRegisterInfo &TRI,
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h 53 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
include/llvm/CodeGen/GlobalISel/RegBankSelect.h 356 const TargetRegisterInfo &TRI, Pass &P,
493 const TargetRegisterInfo *TRI = nullptr;
include/llvm/CodeGen/GlobalISel/RegisterBank.h 65 bool verify(const TargetRegisterInfo &TRI) const;
81 void dump(const TargetRegisterInfo *TRI = nullptr) const;
89 const TargetRegisterInfo *TRI = nullptr) const;
include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h 438 getMinimalPhysRegClass(Register Reg, const TargetRegisterInfo &TRI) const;
546 const TargetRegisterInfo &TRI) const;
584 const TargetRegisterInfo &TRI) const;
730 const TargetRegisterInfo &TRI) const;
738 bool verify(const TargetRegisterInfo &TRI) const;
include/llvm/CodeGen/GlobalISel/Utils.h 58 const TargetRegisterInfo &TRI,
76 const TargetRegisterInfo &TRI,
94 const TargetRegisterInfo &TRI,
include/llvm/CodeGen/LiveInterval.h 842 const TargetRegisterInfo &TRI);
include/llvm/CodeGen/LiveIntervalUnion.h 100 void print(raw_ostream &OS, const TargetRegisterInfo *TRI) const;
include/llvm/CodeGen/LiveIntervals.h 57 const TargetRegisterInfo* TRI;
include/llvm/CodeGen/LivePhysRegs.h 49 const TargetRegisterInfo *TRI = nullptr;
58 LivePhysRegs(const TargetRegisterInfo &TRI) : TRI(&TRI) {
66 void init(const TargetRegisterInfo &TRI) {
include/llvm/CodeGen/LiveRegMatrix.h 41 const TargetRegisterInfo *TRI;
include/llvm/CodeGen/LiveRegUnits.h 31 const TargetRegisterInfo *TRI = nullptr;
39 LiveRegUnits(const TargetRegisterInfo &TRI) {
50 const TargetRegisterInfo *TRI) {
74 void init(const TargetRegisterInfo &TRI) {
include/llvm/CodeGen/LiveStacks.h 31 const TargetRegisterInfo *TRI;
include/llvm/CodeGen/LiveVariables.h 130 const TargetRegisterInfo *TRI;
include/llvm/CodeGen/MachineBasicBlock.h 369 const uint32_t *getBeginClobberMask(const TargetRegisterInfo *TRI) const;
373 const uint32_t *getEndClobberMask(const TargetRegisterInfo *TRI) const;
783 LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI,
include/llvm/CodeGen/MachineInstr.h 1189 const TargetRegisterInfo *TRI = nullptr) const {
1210 const TargetRegisterInfo *TRI = nullptr) const {
1219 const TargetRegisterInfo *TRI = nullptr) const {
1226 bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const {
1234 const TargetRegisterInfo *TRI = nullptr) const {
1246 const TargetRegisterInfo *TRI = nullptr) const;
1251 const TargetRegisterInfo *TRI = nullptr) {
1258 const TargetRegisterInfo *TRI = nullptr) const {
1271 const TargetRegisterInfo *TRI = nullptr) const;
1278 const TargetRegisterInfo *TRI = nullptr) {
1286 const TargetRegisterInfo *TRI = nullptr) const {
1316 const TargetRegisterInfo *TRI) const;
1332 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
1347 const TargetRegisterInfo *TRI) const;
1395 const TargetRegisterInfo &RegInfo);
1402 const TargetRegisterInfo *RegInfo,
1407 void clearRegisterKills(Register Reg, const TargetRegisterInfo *RegInfo);
1413 bool addRegisterDead(Register Reg, const TargetRegisterInfo *RegInfo,
1427 const TargetRegisterInfo *RegInfo = nullptr);
1435 const TargetRegisterInfo &TRI);
1691 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const;
include/llvm/CodeGen/MachineInstrBuilder.h 309 const TargetRegisterInfo &TRI,
include/llvm/CodeGen/MachineInstrBundle.h 217 PhysRegInfo analyzePhysReg(unsigned Reg, const TargetRegisterInfo *TRI);
include/llvm/CodeGen/MachineOperand.h 253 const TargetRegisterInfo *TRI);
275 void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr,
298 unsigned TiedOperandIdx, const TargetRegisterInfo *TRI,
304 const TargetRegisterInfo *TRI = nullptr,
475 void substVirtReg(Register Reg, unsigned SubIdx, const TargetRegisterInfo&);
481 void substPhysReg(MCRegister Reg, const TargetRegisterInfo&);
include/llvm/CodeGen/MachineOutliner.h 138 void initLRU(const TargetRegisterInfo &TRI) {
include/llvm/CodeGen/MachineRegisterInfo.h 153 const TargetRegisterInfo *getTargetRegisterInfo() const {
955 const TargetRegisterInfo &TRI,
1178 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
include/llvm/CodeGen/MachineScheduler.h 886 const TargetRegisterInfo *TRI = nullptr;
921 const TargetRegisterInfo *TRI,
1070 const TargetRegisterInfo *TRI);
1074 const TargetRegisterInfo *TRI);
1078 const TargetRegisterInfo *TRI);
include/llvm/CodeGen/MachineTraceMetrics.h 90 const TargetRegisterInfo *TRI = nullptr;
include/llvm/CodeGen/ReachingDefAnalysis.h 38 const TargetRegisterInfo *TRI;
include/llvm/CodeGen/RegisterClassInfo.h 54 const TargetRegisterInfo *TRI = nullptr;
include/llvm/CodeGen/RegisterPressure.h 56 void dump(const TargetRegisterInfo *TRI) const;
163 void dump(const TargetRegisterInfo &TRI) const;
180 void collect(const MachineInstr &MI, const TargetRegisterInfo &TRI,
360 const TargetRegisterInfo *TRI = nullptr;
570 const TargetRegisterInfo *TRI);
include/llvm/CodeGen/RegisterScavenging.h 35 const TargetRegisterInfo *TRI;
include/llvm/CodeGen/ResourcePriorityQueue.h 59 const TargetRegisterInfo *TRI;
include/llvm/CodeGen/ScheduleDAG.h 238 void dump(const TargetRegisterInfo *TRI = nullptr) const;
559 const TargetRegisterInfo *TRI; ///< Target processor register info
include/llvm/CodeGen/StackMaps.h 303 const TargetRegisterInfo *TRI) const;
include/llvm/CodeGen/TailDuplicator.h 38 const TargetRegisterInfo *TRI;
include/llvm/CodeGen/TargetFrameLowering.h 131 const TargetRegisterInfo *TRI,
include/llvm/CodeGen/TargetInstrInfo.h 90 const TargetRegisterInfo *TRI,
1219 const TargetRegisterInfo *TRI) const {
1559 const TargetRegisterInfo *TRI) const {
1579 const TargetRegisterInfo *TRI) const {
1602 const TargetRegisterInfo *TRI) const {}
include/llvm/CodeGen/TargetLowering.h 2027 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT) const;
2031 void computeRegisterProperties(const TargetRegisterInfo *TRI);
2919 bool isLegalRC(const TargetRegisterInfo &TRI,
3906 const TargetRegisterInfo *TRI,
3940 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
include/llvm/CodeGen/TargetRegisterInfo.h 602 const TargetRegisterInfo* TRI = nullptr);
1010 const TargetRegisterInfo *TRI,
1110 BitMaskClassIterator(const uint32_t *Mask, const TargetRegisterInfo &TRI)
1147 Printable printReg(Register Reg, const TargetRegisterInfo *TRI = nullptr,
1159 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI);
1163 Printable printVRegOrUnit(unsigned VRegOrUnit, const TargetRegisterInfo *TRI);
1168 const TargetRegisterInfo *TRI);
include/llvm/CodeGen/TargetSubtargetInfo.h 123 virtual const TargetRegisterInfo *getRegisterInfo() const { return nullptr; }
include/llvm/CodeGen/VirtRegMap.h 44 const TargetRegisterInfo *TRI;
90 const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; }
lib/CodeGen/AggressiveAntiDepBreaker.h 121 const TargetRegisterInfo *TRI;
lib/CodeGen/AllocationOrder.cpp 35 const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp 532 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
lib/CodeGen/AsmPrinter/CodeViewDebug.cpp 1147 const TargetRegisterInfo *TRI = TSI.getRegisterInfo();
1211 const TargetRegisterInfo *TRI = Asm->MF->getSubtarget().getRegisterInfo();
1330 const TargetRegisterInfo *TRI = TSI.getRegisterInfo();
lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp 232 const TargetRegisterInfo *TRI,
lib/CodeGen/AsmPrinter/DwarfCompileUnit.cpp 399 const TargetRegisterInfo *RI = Asm->MF->getSubtarget().getRegisterInfo();
1181 const TargetRegisterInfo &TRI = *Asm->MF->getSubtarget().getRegisterInfo();
1211 const TargetRegisterInfo &TRI = *Asm->MF->getSubtarget().getRegisterInfo();
lib/CodeGen/AsmPrinter/DwarfDebug.cpp 195 bool DebugLocDwarfExpression::isFrameRegister(const TargetRegisterInfo &TRI,
2207 const TargetRegisterInfo &TRI = *AP.MF->getSubtarget().getRegisterInfo();
lib/CodeGen/AsmPrinter/DwarfExpression.cpp 99 bool DwarfExpression::addMachineReg(const TargetRegisterInfo &TRI,
220 bool DwarfExpression::addMachineRegExpression(const TargetRegisterInfo &TRI,
lib/CodeGen/AsmPrinter/DwarfExpression.h 212 virtual bool isFrameRegister(const TargetRegisterInfo &TRI, unsigned MachineReg) = 0;
239 bool addMachineReg(const TargetRegisterInfo &TRI, unsigned MachineReg,
316 bool addMachineRegExpression(const TargetRegisterInfo &TRI,
371 bool isFrameRegister(const TargetRegisterInfo &TRI,
400 bool isFrameRegister(const TargetRegisterInfo &TRI,
lib/CodeGen/AsmPrinter/DwarfUnit.cpp 86 bool DIEDwarfExpression::isFrameRegister(const TargetRegisterInfo &TRI,
lib/CodeGen/BranchFolding.cpp 179 const TargetRegisterInfo *tri,
1852 static void addRegAndItsAliases(unsigned Reg, const TargetRegisterInfo *TRI,
lib/CodeGen/BranchFolding.h 50 const TargetRegisterInfo *tri, MachineModuleInfo *mmi,
128 const TargetRegisterInfo *TRI;
lib/CodeGen/BranchRelaxation.cpp 87 const TargetRegisterInfo *TRI;
lib/CodeGen/BreakFalseDeps.cpp 37 const TargetRegisterInfo *TRI;
lib/CodeGen/CalcSpillWeights.cpp 52 const TargetRegisterInfo &tri,
154 const TargetRegisterInfo &tri = *MF.getSubtarget().getRegisterInfo();
lib/CodeGen/CodeGenPrepare.cpp 248 const TargetRegisterInfo *TRI;
2751 const TargetRegisterInfo &TRI;
2782 const TargetRegisterInfo &TRI, Type *AT, unsigned AS, Instruction *MI,
2804 const TargetLowering &TLI, const TargetRegisterInfo &TRI,
4389 const TargetRegisterInfo &TRI) {
4423 const TargetRegisterInfo &TRI, int SeenInsts = 0) {
5034 const TargetRegisterInfo *TRI =
lib/CodeGen/CriticalAntiDepBreaker.h 40 const TargetRegisterInfo *TRI;
lib/CodeGen/DeadMachineInstructionElim.cpp 32 const TargetRegisterInfo *TRI;
lib/CodeGen/DetectDeadLanes.cpp 110 const TargetRegisterInfo *TRI;
164 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
lib/CodeGen/EarlyIfConversion.cpp 83 const TargetRegisterInfo *TRI;
702 const TargetRegisterInfo *TRI;
939 const TargetRegisterInfo *TRI;
lib/CodeGen/ExpandPostRAPseudos.cpp 32 const TargetRegisterInfo *TRI;
lib/CodeGen/GCRootLowering.cpp 319 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/GlobalISel/CombinerHelper.cpp 1080 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1187 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/GlobalISel/IRTranslator.cpp 1167 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
lib/CodeGen/GlobalISel/InstructionSelect.cpp 185 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/CodeGen/GlobalISel/InstructionSelector.cpp 38 const TargetInstrInfo &TII, const TargetRegisterInfo &TRI,
lib/CodeGen/GlobalISel/RegBankSelect.cpp 723 MachineInstr &MI, unsigned OpIdx, const TargetRegisterInfo &TRI, Pass &P,
lib/CodeGen/GlobalISel/RegisterBank.cpp 31 bool RegisterBank::verify(const TargetRegisterInfo &TRI) const {
81 LLVM_DUMP_METHOD void RegisterBank::dump(const TargetRegisterInfo *TRI) const {
87 const TargetRegisterInfo *TRI) const {
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 69 bool RegisterBankInfo::verify(const TargetRegisterInfo &TRI) const {
84 const TargetRegisterInfo &TRI) const {
99 const TargetRegisterInfo &TRI) const {
111 const TargetRegisterInfo &TRI) const {
167 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
490 const TargetRegisterInfo &TRI) const {
779 const TargetRegisterInfo *TRI =
lib/CodeGen/GlobalISel/Utils.cpp 41 const MachineFunction &MF, const TargetRegisterInfo &TRI,
71 const MachineFunction &MF, const TargetRegisterInfo &TRI,
113 const TargetRegisterInfo &TRI,
lib/CodeGen/IfConversion.cpp 192 const TargetRegisterInfo *TRI;
1475 const TargetRegisterInfo *TRI = MI.getMF()->getSubtarget().getRegisterInfo();
lib/CodeGen/ImplicitNullChecks.cpp 164 const TargetRegisterInfo *TRI = nullptr;
314 static bool AnyAliasLiveIn(const TargetRegisterInfo *TRI,
lib/CodeGen/InlineSpiller.cpp 95 const TargetRegisterInfo &TRI;
168 const TargetRegisterInfo &TRI;
lib/CodeGen/InterferenceCache.cpp 58 const TargetRegisterInfo *tri) {
94 const TargetRegisterInfo *TRI) {
106 const TargetRegisterInfo *TRI,
124 const TargetRegisterInfo *TRI) {
lib/CodeGen/InterferenceCache.h 117 void revalidate(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
120 bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
125 const TargetRegisterInfo *TRI,
141 const TargetRegisterInfo *TRI = nullptr;
173 const TargetRegisterInfo *tri);
lib/CodeGen/LiveDebugValues.cpp 96 const TargetRegisterInfo *TRI;
334 void dump(const TargetRegisterInfo *TRI, raw_ostream &Out = dbgs()) const {
lib/CodeGen/LiveDebugVariables.cpp 202 const TargetRegisterInfo &TRI);
303 void computeIntervals(MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
316 const TargetRegisterInfo &TRI,
322 const TargetRegisterInfo &TRI,
328 void print(raw_ostream &, const TargetRegisterInfo *);
381 void print(raw_ostream &, const TargetRegisterInfo *);
390 const TargetRegisterInfo *TRI;
527 void UserValue::print(raw_ostream &OS, const TargetRegisterInfo *TRI) {
547 void UserLabel::print(raw_ostream &OS, const TargetRegisterInfo *TRI) {
834 const TargetRegisterInfo &TRI,
1154 const TargetRegisterInfo &TRI,
1288 const TargetRegisterInfo &TRI) {
1339 const TargetRegisterInfo &TRI,
lib/CodeGen/LiveInterval.cpp 886 const TargetRegisterInfo &TRI) {
927 const SlotIndexes &Indexes, const TargetRegisterInfo &TRI) {
974 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
lib/CodeGen/LiveIntervalUnion.cpp 82 LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const {
lib/CodeGen/LiveIntervals.cpp 947 const TargetRegisterInfo& TRI;
955 const TargetRegisterInfo& TRI,
lib/CodeGen/LivePhysRegs.cpp 250 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
261 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
282 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
lib/CodeGen/LiveRangeCalc.cpp 80 const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
164 const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
377 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
lib/CodeGen/LiveRangeEdit.cpp 249 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
369 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
lib/CodeGen/LiveRegMatrix.cpp 79 static bool foreachUnit(const TargetRegisterInfo *TRI,
lib/CodeGen/LocalStackSlotAllocation.cpp 114 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
273 const TargetRegisterInfo *TRI) {
290 const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
lib/CodeGen/MIRParser/MIParser.cpp 111 const auto *TRI = Subtarget.getRegisterInfo();
155 const auto *TRI = Subtarget.getRegisterInfo();
176 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
278 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1080 static std::string getRegisterName(const TargetRegisterInfo *TRI,
1114 const auto *TRI = MF.getSubtarget().getRegisterInfo();
1244 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
2023 const auto *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/MIRPrinter.cpp 123 const TargetRegisterInfo *TRI);
165 const TargetRegisterInfo *TRI, bool ShouldPrintRegisterTies,
190 const TargetRegisterInfo *TRI) {
245 const TargetRegisterInfo *TRI) {
265 const TargetRegisterInfo *TRI) {
288 const TargetRegisterInfo *TRI) {
361 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
470 const auto *TRI = MF.getSubtarget().getRegisterInfo();
543 const auto *TRI = MF.getSubtarget().getRegisterInfo();
669 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
709 const auto *TRI = SubTarget.getRegisterInfo();
819 const TargetRegisterInfo *TRI,
lib/CodeGen/MachineBasicBlock.cpp 338 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
991 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
1385 MachineBasicBlock::computeRegisterLiveness(const TargetRegisterInfo *TRI,
1480 MachineBasicBlock::getBeginClobberMask(const TargetRegisterInfo *TRI) const {
1486 MachineBasicBlock::getEndClobberMask(const TargetRegisterInfo *TRI) const {
lib/CodeGen/MachineCSE.cpp 66 const TargetRegisterInfo *TRI;
259 const TargetRegisterInfo &TRI) {
lib/CodeGen/MachineCombiner.cpp 63 const TargetRegisterInfo *TRI;
lib/CodeGen/MachineCopyPropagation.cpp 89 const TargetRegisterInfo &TRI) {
101 void clobberRegister(unsigned Reg, const TargetRegisterInfo &TRI) {
119 void trackCopy(MachineInstr *MI, const TargetRegisterInfo &TRI) {
143 MachineInstr *findCopyForUnit(unsigned RegUnit, const TargetRegisterInfo &TRI,
154 const TargetRegisterInfo &TRI) {
184 const TargetRegisterInfo *TRI;
264 unsigned Def, const TargetRegisterInfo *TRI) {
lib/CodeGen/MachineFrameInfo.cpp 115 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
138 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/MachineFunction.cpp 497 const TargetRegisterInfo *TRI = getSubtarget().getRegisterInfo();
lib/CodeGen/MachineInstr.cpp 89 const TargetRegisterInfo *&TRI,
833 const TargetRegisterInfo *TRI) const {
872 const TargetRegisterInfo *TRI, bool ExploreBundle) const {
889 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
901 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI) const {
944 Register Reg, bool isKill, const TargetRegisterInfo *TRI) const {
993 const TargetRegisterInfo *TRI) const {
1141 const TargetRegisterInfo &RegInfo) {
1477 const TargetRegisterInfo *TRI = nullptr;
1785 const TargetRegisterInfo *RegInfo,
1851 const TargetRegisterInfo *RegInfo) {
1864 const TargetRegisterInfo *RegInfo,
1933 const TargetRegisterInfo *RegInfo) {
1951 const TargetRegisterInfo &TRI) {
lib/CodeGen/MachineInstrBundle.cpp 132 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
315 const TargetRegisterInfo *TRI) {
lib/CodeGen/MachineLICM.cpp 96 const TargetRegisterInfo *TRI;
913 const TargetRegisterInfo *TRI,
948 const TargetRegisterInfo *TRI) {
lib/CodeGen/MachineOperand.cpp 75 const TargetRegisterInfo &TRI) {
84 void MachineOperand::substPhysReg(MCRegister Reg, const TargetRegisterInfo &TRI) {
316 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
395 const TargetRegisterInfo *&TRI,
426 const TargetRegisterInfo *TRI) {
526 const TargetRegisterInfo *TRI) {
621 const TargetRegisterInfo *TRI) {
727 void MachineOperand::print(raw_ostream &OS, const TargetRegisterInfo *TRI,
733 const TargetRegisterInfo *TRI,
746 const TargetRegisterInfo *TRI,
lib/CodeGen/MachinePipeliner.cpp 1546 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
2057 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
2238 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/MachineRegisterInfo.cpp 383 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
471 const TargetRegisterInfo &TRI,
522 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
537 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
590 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
604 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
615 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
658 const TargetRegisterInfo *TRI = getTargetRegisterInfo();
lib/CodeGen/MachineScheduler.cpp 1509 const TargetRegisterInfo *TRI;
1514 const TargetRegisterInfo *tri, bool IsLoad)
1526 const TargetRegisterInfo *tri)
1532 LoadClusterMutation(const TargetInstrInfo *tii, const TargetRegisterInfo *tri)
1542 const TargetRegisterInfo *TRI) {
1549 const TargetRegisterInfo *TRI) {
1647 CopyConstrain(const TargetInstrInfo *, const TargetRegisterInfo *) {}
1661 const TargetRegisterInfo *TRI) {
2866 const TargetRegisterInfo *TRI,
lib/CodeGen/MachineSink.cpp 86 const TargetRegisterInfo *TRI;
723 const TargetRegisterInfo *TRI) {
1083 const TargetRegisterInfo *TRI, const TargetInstrInfo *TII);
1094 const TargetRegisterInfo *TRI) {
1103 unsigned Reg, const TargetRegisterInfo *TRI) {
1131 const TargetRegisterInfo *TRI) {
1146 const TargetRegisterInfo *TRI) {
1167 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1214 const TargetRegisterInfo *TRI) {
1223 const TargetRegisterInfo *TRI,
1341 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/MachineTraceMetrics.cpp 702 const TargetRegisterInfo *TRI) {
896 const TargetRegisterInfo *TRI) {
lib/CodeGen/MachineVerifier.cpp 96 const TargetRegisterInfo *TRI;
lib/CodeGen/ModuloSchedule.cpp 787 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
912 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/PeepholeOptimizer.cpp 155 const TargetRegisterInfo *TRI;
1965 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
lib/CodeGen/ProcessImplicitDefs.cpp 29 const TargetRegisterInfo *TRI;
lib/CodeGen/PrologEpilogInserter.cpp 217 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
387 const TargetRegisterInfo *RegInfo = F.getSubtarget().getRegisterInfo();
538 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
565 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
883 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1137 const TargetRegisterInfo *TRI = ST.getRegisterInfo();
1179 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/CodeGen/RegAllocBase.h 64 const TargetRegisterInfo *TRI = nullptr;
lib/CodeGen/RegAllocFast.cpp 72 const TargetRegisterInfo *TRI;
lib/CodeGen/RegAllocGreedy.cpp 163 const TargetRegisterInfo *TRI;
2066 const TargetInstrInfo *TII, const TargetRegisterInfo *TRI,
lib/CodeGen/RegAllocPBQP.cpp 400 const TargetRegisterInfo &TRI =
568 static bool isACalleeSavedRegister(unsigned reg, const TargetRegisterInfo &TRI,
583 const TargetRegisterInfo &TRI =
685 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
709 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
880 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
lib/CodeGen/RegUsageInfoCollector.cpp 103 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
198 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/CodeGen/RegisterCoalescer.cpp 126 const TargetRegisterInfo* TRI;
361 LLVM_NODISCARD static bool isMoveInstr(const TargetRegisterInfo &tri,
2192 const TargetRegisterInfo *TRI;
2338 LiveIntervals *lis, const TargetRegisterInfo *TRI, bool SubRangeJoin,
lib/CodeGen/RegisterCoalescer.h 27 const TargetRegisterInfo &TRI;
58 CoalescerPair(const TargetRegisterInfo &tri) : TRI(tri) {}
63 const TargetRegisterInfo &tri)
lib/CodeGen/RegisterPressure.cpp 82 const TargetRegisterInfo *TRI) {
95 void RegisterPressure::dump(const TargetRegisterInfo *TRI) const {
126 void PressureDiff::dump(const TargetRegisterInfo &TRI) const {
226 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
471 const TargetRegisterInfo &TRI;
476 const TargetRegisterInfo &TRI,
569 const TargetRegisterInfo &TRI,
1226 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
lib/CodeGen/RegisterScavenging.cpp 388 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
625 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
680 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
lib/CodeGen/RegisterUsageInfo.cpp 91 const TargetRegisterInfo *TRI
lib/CodeGen/RenameIndependentSubregs.cpp 175 const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
213 const TargetRegisterInfo &TRI = *MRI->getTargetRegisterInfo();
lib/CodeGen/ScheduleDAG.cpp 75 LLVM_DUMP_METHOD void SDep::dump(const TargetRegisterInfo *TRI) const {
lib/CodeGen/SelectionDAG/DAGCombiner.cpp14436 const TargetRegisterInfo *TRI = DAG->getSubtarget().getRegisterInfo();
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp 184 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
lib/CodeGen/SelectionDAG/InstrEmitter.h 32 const TargetRegisterInfo *TRI;
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp 450 const TargetRegisterInfo *TRI) {
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 312 const TargetRegisterInfo *TRI,
1301 const TargetRegisterInfo *TRI) {
1737 const TargetRegisterInfo *TRI;
1757 const TargetRegisterInfo *tri,
1880 const TargetRegisterInfo *tri,
2840 const TargetRegisterInfo *TRI) {
2875 const TargetRegisterInfo *TRI) {
3136 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
3150 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
3164 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
3180 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp 111 const TargetRegisterInfo *TRI,
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 5817 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 7812 const TargetRegisterInfo *TRI = DAG.getSubtarget().getRegisterInfo();
7889 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 543 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo();
lib/CodeGen/SelectionDAG/TargetLowering.cpp 4116 TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *RI,
4180 const TargetRegisterInfo *TRI,
lib/CodeGen/ShrinkWrap.cpp 483 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/SplitKit.h 265 const TargetRegisterInfo &TRI;
lib/CodeGen/StackMapLivenessAnalysis.cpp 50 const TargetRegisterInfo *TRI;
lib/CodeGen/StackMaps.cpp 92 static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) {
105 const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo();
175 const TargetRegisterInfo *TRI =
247 StackMaps::createLiveOutReg(unsigned Reg, const TargetRegisterInfo *TRI) const {
258 const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo();
351 const TargetRegisterInfo *RegInfo = AP.MF->getSubtarget().getRegisterInfo();
lib/CodeGen/TargetFrameLoweringImpl.cpp 47 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
65 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
79 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/CodeGen/TargetInstrInfo.cpp 46 const TargetRegisterInfo *TRI,
382 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
549 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
780 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
999 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/TargetLoweringBase.cpp 1008 bool TargetLoweringBase::isLegalRC(const TargetRegisterInfo &TRI,
1136 TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1164 const TargetRegisterInfo *TRI) {
lib/CodeGen/TargetRegisterInfo.cpp 89 Printable printReg(Register Reg, const TargetRegisterInfo *TRI,
120 Printable printRegUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
143 Printable printVRegOrUnit(unsigned Unit, const TargetRegisterInfo *TRI) {
154 const TargetRegisterInfo *TRI) {
241 const TargetRegisterInfo *TRI) {
342 static bool shareSameRegisterFile(const TargetRegisterInfo &TRI,
520 const TargetRegisterInfo *TRI) {
lib/CodeGen/TargetSchedule.cpp 305 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/CodeGen/TwoAddressInstructionPass.cpp 95 const TargetRegisterInfo *TRI;
561 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) {
571 const TargetRegisterInfo *TRI) {
lib/CodeGen/VirtRegMap.cpp 177 const TargetRegisterInfo *TRI;
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 111 const TargetRegisterInfo *TRI;
lib/Target/AArch64/AArch64AsmPrinter.cpp 552 const TargetRegisterInfo *RI = STI->getRegisterInfo();
lib/Target/AArch64/AArch64CondBrTuning.cpp 49 const TargetRegisterInfo *TRI;
lib/Target/AArch64/AArch64ConditionalCompares.cpp 140 const TargetRegisterInfo *TRI;
764 const TargetRegisterInfo *TRI;
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp 37 const TargetRegisterInfo *TRI;
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 206 const TargetRegisterInfo *TRI;
658 static Optional<unsigned> getTag(const TargetRegisterInfo *TRI,
lib/Target/AArch64/AArch64FrameLowering.cpp 235 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1827 const TargetRegisterInfo *TRI, SmallVectorImpl<RegPairInfo> &RegPairs,
2229 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
2290 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 279 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
lib/Target/AArch64/AArch64ISelLowering.cpp 5976 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
lib/Target/AArch64/AArch64ISelLowering.h 726 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/AArch64/AArch64InstrInfo.cpp 933 const TargetRegisterInfo *TRI = &getRegisterInfo();
1053 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
1396 const TargetRegisterInfo *TRI) {
1449 const TargetRegisterInfo *TRI = &getRegisterInfo();
1943 const TargetRegisterInfo *TRI = &getRegisterInfo();
1983 const TargetRegisterInfo *TRI) const {
1990 unsigned &Width, const TargetRegisterInfo *TRI) const {
2394 const TargetRegisterInfo *TRI) {
2417 const TargetRegisterInfo *TRI = &getRegisterInfo();
2443 const TargetRegisterInfo *TRI = &getRegisterInfo();
2468 const TargetRegisterInfo *TRI = &getRegisterInfo();
2782 static void storeRegPairToStackSlot(const TargetRegisterInfo &TRI,
2911 static void loadRegPairFromStackSlot(const TargetRegisterInfo &TRI,
3236 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5054 const TargetRegisterInfo &TRI = getRegisterInfo();
lib/Target/AArch64/AArch64InstrInfo.h 112 const TargetRegisterInfo *TRI) const override;
117 const TargetRegisterInfo *TRI) const;
lib/Target/AArch64/AArch64InstructionSelector.cpp 370 const TargetRegisterInfo &TRI, unsigned &SubReg) {
557 const TargetRegisterInfo &TRI,
618 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
643 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
833 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
3381 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
3583 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 97 const TargetRegisterInfo *TRI;
lib/Target/AArch64/AArch64PBQPRegAlloc.h 27 const TargetRegisterInfo *TRI;
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 71 const TargetRegisterInfo *TRI;
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 39 AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI)
272 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
462 const TargetRegisterInfo &TRI) const {
481 const TargetRegisterInfo &TRI) const {
495 const TargetRegisterInfo &TRI) const {
525 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
lib/Target/AArch64/AArch64RegisterBankInfo.h 119 const TargetRegisterInfo &TRI) const;
123 const TargetRegisterInfo &TRI) const;
127 const TargetRegisterInfo &TRI) const;
130 AArch64RegisterBankInfo(const TargetRegisterInfo &TRI);
lib/Target/AArch64/AArch64SpeculationHardening.cpp 128 const TargetRegisterInfo *TRI;
lib/Target/AArch64/AArch64StorePairSuppress.cpp 32 const TargetRegisterInfo *TRI;
lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp 23 const TargetRegisterInfo *TRI) const {
lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h 89 void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const;
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 266 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
346 const TargetRegisterInfo *TRI, PHILinearize &PHIInfo);
351 const TargetRegisterInfo *TRI,
355 const TargetRegisterInfo *TRI, PHILinearize &PHIInfo,
359 const TargetRegisterInfo *TRI, PHILinearize &PHIInfo);
362 const TargetRegisterInfo *TRI, PHILinearize &PHIInfo,
368 const TargetRegisterInfo *TRI, PHILinearize &PHIInfo);
379 void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr);
434 const TargetRegisterInfo *TRI, PHILinearize &PHIInfo);
477 virtual void dump(const TargetRegisterInfo *TRI, int depth = 0) = 0;
500 void dump(const TargetRegisterInfo *TRI, int depth = 0) override {
550 void dump(const TargetRegisterInfo *TRI, int depth = 0) override {
695 const TargetRegisterInfo *TRI,
735 const TargetRegisterInfo *TRI,
752 const TargetRegisterInfo *TRI,
795 const TargetRegisterInfo *TRI,
814 const TargetRegisterInfo *TRI,
861 void LinearizedRegion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) {
1018 const TargetRegisterInfo *TRI = MRI->getTargetRegisterInfo();
1063 const TargetRegisterInfo *TRI,
1070 const TargetRegisterInfo *TRI,
1091 const TargetRegisterInfo *TRI;
lib/Target/AMDGPU/AMDGPUMacroFusion.cpp 46 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 2073 const TargetRegisterInfo &TRI,
2089 const TargetRegisterInfo &TRI) const {
2100 const TargetRegisterInfo &TRI) const {
lib/Target/AMDGPU/AMDGPURegisterBankInfo.h 93 const TargetRegisterInfo &TRI,
99 const TargetRegisterInfo &TRI) const;
104 const TargetRegisterInfo &TRI) const;
lib/Target/AMDGPU/GCNRegPressure.cpp 446 const TargetRegisterInfo *TRI) {
499 const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 423 const TargetRegisterInfo *TRI,
lib/Target/AMDGPU/SIFoldOperands.cpp 187 const TargetRegisterInfo &TRI,
lib/Target/AMDGPU/SIFrameLowering.cpp 1077 MachineFunction &MF, const TargetRegisterInfo *TRI,
lib/Target/AMDGPU/SIFrameLowering.h 43 const TargetRegisterInfo *TRI,
lib/Target/AMDGPU/SIISelLowering.cpp10540 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/AMDGPU/SIISelLowering.h 372 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/AMDGPU/SIInstrInfo.cpp 262 const TargetRegisterInfo *TRI) const {
lib/Target/AMDGPU/SIInstrInfo.h 185 const TargetRegisterInfo *TRI) const final;
1021 const TargetRegisterInfo *TRI,
lib/Target/AMDGPU/SILowerSGPRSpills.cpp 93 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
125 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/AMDGPU/SIMachineFunctionInfo.cpp 419 const TargetRegisterInfo &TRI) {
430 const TargetRegisterInfo &TRI) {
481 const TargetRegisterInfo &TRI)
lib/Target/AMDGPU/SIMachineFunctionInfo.h 280 const TargetRegisterInfo &TRI);
lib/Target/AMDGPU/SIMachineScheduler.h 460 const TargetRegisterInfo *getTRI() { return TRI; }
lib/Target/ARC/ARCFrameLowering.cpp 347 MachineFunction &MF, const TargetRegisterInfo *TRI,
437 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
494 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
lib/Target/ARC/ARCFrameLowering.h 64 llvm::MachineFunction &, const llvm::TargetRegisterInfo *,
lib/Target/ARC/ARCISelLowering.cpp 344 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
lib/Target/ARC/ARCRegisterInfo.cpp 64 const TargetRegisterInfo *TRI =
lib/Target/ARM/A15SDOptimizer.cpp 58 const TargetRegisterInfo *TRI;
lib/Target/ARM/ARMAsmPrinter.cpp 211 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
279 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
311 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
372 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
380 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
406 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
421 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1071 const TargetRegisterInfo *TargetRegInfo =
lib/Target/ARM/ARMBaseInstrInfo.cpp 957 const TargetRegisterInfo *TRI = &getRegisterInfo();
1018 const TargetRegisterInfo *TRI) const {
1549 const TargetRegisterInfo &TRI = getRegisterInfo();
1595 const TargetRegisterInfo *TRI = &getRegisterInfo();
2007 const TargetRegisterInfo *TRI = &getRegisterInfo();
2454 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();
2975 const TargetRegisterInfo *TRI = &getRegisterInfo();
4020 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
4043 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
4871 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
4901 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
4933 const TargetRegisterInfo *TRI = &getRegisterInfo();
5138 const TargetRegisterInfo *TRI) const {
5198 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
5364 const TargetRegisterInfo *TRI) {
lib/Target/ARM/ARMBaseInstrInfo.h 236 const TargetRegisterInfo *TRI) const;
333 const TargetRegisterInfo *) const override;
335 const TargetRegisterInfo *TRI) const override;
609 const TargetRegisterInfo *TRI);
619 const TargetRegisterInfo *TRI);
lib/Target/ARM/ARMCallLowering.cpp 508 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
lib/Target/ARM/ARMExpandPseudoInsts.cpp 45 const TargetRegisterInfo *TRI;
436 const TargetRegisterInfo *TRI, unsigned &D0,
1037 const TargetRegisterInfo *TRI) {
lib/Target/ARM/ARMFrameLowering.cpp 105 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
774 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
980 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
1057 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
1511 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
1655 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/ARM/ARMHazardRecognizer.cpp 19 const TargetRegisterInfo &TRI) {
lib/Target/ARM/ARMISelLowering.cpp 1473 ARMTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
10498 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
15676 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
lib/Target/ARM/ARMISelLowering.h 429 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
633 findRepresentativeClass(const TargetRegisterInfo *TRI,
641 const TargetRegisterInfo *RegInfo;
lib/Target/ARM/ARMInstructionSelector.cpp 186 const TargetRegisterInfo &TRI,
211 MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI,
233 const TargetRegisterInfo &TRI,
264 const TargetRegisterInfo &TRI,
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 104 const TargetRegisterInfo *TRI;
2039 const TargetRegisterInfo *TRI;
lib/Target/ARM/ARMLowOverheadLoops.cpp 195 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
lib/Target/ARM/ARMRegisterBankInfo.cpp 132 ARMRegisterBankInfo::ARMRegisterBankInfo(const TargetRegisterInfo &TRI)
lib/Target/ARM/ARMRegisterBankInfo.h 33 ARMRegisterBankInfo(const TargetRegisterInfo &TRI);
lib/Target/ARM/MLxExpansionPass.cpp 51 const TargetRegisterInfo *TRI;
lib/Target/ARM/MVEVPTBlockPass.cpp 41 const TargetRegisterInfo *TRI;
lib/Target/ARM/Thumb1FrameLowering.cpp 652 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
lib/Target/ARM/Thumb1InstrInfo.cpp 58 const TargetRegisterInfo *RegInfo = st.getRegisterInfo();
lib/Target/ARM/Thumb2ITBlockPass.cpp 49 const TargetRegisterInfo *TRI;
82 const TargetRegisterInfo *TRI) {
lib/Target/ARM/Thumb2InstrInfo.cpp 467 const TargetRegisterInfo *TRI) {
lib/Target/AVR/AVRAsmPrinter.cpp 109 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
lib/Target/AVR/AVRFrameLowering.cpp 309 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
lib/Target/AVR/AVRISelLowering.cpp 1281 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1852 AVRTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/AVR/AVRISelLowering.h 119 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/AVR/AVRRegisterInfo.cpp 85 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/BPF/BPFISelLowering.cpp 175 BPFTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/BPF/BPFISelLowering.h 50 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/BPF/BPFMIChecking.cpp 34 const TargetRegisterInfo *TRI;
106 static bool hasLiveDefs(const MachineInstr &MI, const TargetRegisterInfo *TRI) {
lib/Target/BPF/BPFMIPeephole.cpp 204 const TargetRegisterInfo *TRI;
lib/Target/BPF/BPFSubtarget.h 86 const TargetRegisterInfo *getRegisterInfo() const override {
lib/Target/Hexagon/BitTracker.h 392 MachineEvaluator(const TargetRegisterInfo &T, MachineRegisterInfo &M)
489 const TargetRegisterInfo &TRI;
lib/Target/Hexagon/HexagonAsmPrinter.cpp 130 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/Hexagon/HexagonBitSimplify.cpp 159 PrintRegSet(const RegisterSet &S, const TargetRegisterInfo *RI)
167 const TargetRegisterInfo *TRI;
lib/Target/Hexagon/HexagonBlockRanges.cpp 234 const TargetRegisterInfo &TRI) {
263 const TargetRegisterInfo &TRI) {
lib/Target/Hexagon/HexagonBlockRanges.h 147 const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI);
150 PrintRangeMap(const RegToRangeMap &M, const TargetRegisterInfo &I)
157 const TargetRegisterInfo &TRI;
162 const MachineRegisterInfo &MRI, const TargetRegisterInfo &TRI);
170 const TargetRegisterInfo &TRI;
lib/Target/Hexagon/HexagonConstPropagation.cpp 92 void print(const TargetRegisterInfo *TRI = nullptr) const {
231 void print(raw_ostream &os, const TargetRegisterInfo &TRI) const;
313 const TargetRegisterInfo &TRI;
613 const TargetRegisterInfo &TRI) const {
lib/Target/Hexagon/HexagonCopyToCombine.cpp 61 const TargetRegisterInfo *TRI;
183 static bool areCombinableOperations(const TargetRegisterInfo *TRI,
250 const TargetRegisterInfo *TRI) {
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 135 PrintFP(const FlowPattern &P, const TargetRegisterInfo &T)
139 const TargetRegisterInfo &TRI;
214 const TargetRegisterInfo *TRI = nullptr;
lib/Target/Hexagon/HexagonExpandCondsets.cpp 165 const TargetRegisterInfo *TRI = nullptr;
lib/Target/Hexagon/HexagonFrameLowering.cpp 245 const TargetRegisterInfo &TRI,
265 const TargetRegisterInfo &TRI) {
1417 static void dump_registers(BitVector &Regs, const TargetRegisterInfo &TRI) {
1428 const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI) const {
lib/Target/Hexagon/HexagonFrameLowering.h 99 const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI)
lib/Target/Hexagon/HexagonGenInsert.cpp 175 PrintRegSet(const RegisterSet &S, const TargetRegisterInfo *RI)
183 const TargetRegisterInfo *TRI;
414 PrintORL(const OrderedRegisterList &L, const TargetRegisterInfo *RI)
421 const TargetRegisterInfo *TRI;
471 PrintIFR(const IFRecord &R, const TargetRegisterInfo *RI)
478 const TargetRegisterInfo *TRI;
lib/Target/Hexagon/HexagonGenPredicate.cpp 68 PrintRegister(RegisterSubReg R, const TargetRegisterInfo &I) : Reg(R), TRI(I) {}
72 const TargetRegisterInfo &TRI;
lib/Target/Hexagon/HexagonHardwareLoops.cpp 358 void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const {
lib/Target/Hexagon/HexagonISelLowering.cpp 2996 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
3203 HexagonTargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
lib/Target/Hexagon/HexagonISelLowering.h 269 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
461 findRepresentativeClass(const TargetRegisterInfo *TRI, MVT VT)
lib/Target/Hexagon/HexagonInstrInfo.cpp 2675 const TargetRegisterInfo *TRI, bool Extend) const {
2941 const TargetRegisterInfo *TRI) const {
lib/Target/Hexagon/HexagonInstrInfo.h 210 const TargetRegisterInfo *TRI) const override;
403 const TargetRegisterInfo *TRI, bool Extend = true) const;
lib/Target/Hexagon/HexagonNewValueJump.cpp 117 const TargetRegisterInfo *TRI,
238 const TargetRegisterInfo *TRI,
lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp 69 const TargetRegisterInfo *TRI = HST.getRegisterInfo();
lib/Target/Hexagon/HexagonSplitDouble.cpp 122 const TargetRegisterInfo&);
137 const USet &Part, const TargetRegisterInfo &TRI) {
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 148 const TargetRegisterInfo *TRI) {
342 const TargetRegisterInfo *TRI) {
lib/Target/Hexagon/RDFCopy.cpp 50 const TargetRegisterInfo &TRI = DFG.getTRI();
122 const TargetRegisterInfo &TRI = DFG.getTRI();
lib/Target/Hexagon/RDFGraph.cpp 652 const TargetRegisterInfo &tri, const MachineDominatorTree &mdt,
lib/Target/Hexagon/RDFGraph.h 646 const TargetRegisterInfo &tri, const MachineDominatorTree &mdt,
663 const TargetRegisterInfo &getTRI() const { return TRI; }
871 const TargetRegisterInfo &TRI;
lib/Target/Hexagon/RDFLiveness.h 101 const TargetRegisterInfo &TRI;
lib/Target/Hexagon/RDFRegisters.cpp 27 PhysicalRegisterInfo::PhysicalRegisterInfo(const TargetRegisterInfo &tri,
lib/Target/Hexagon/RDFRegisters.h 98 PhysicalRegisterInfo(const TargetRegisterInfo &tri,
132 const TargetRegisterInfo &getTRI() const { return TRI; }
146 const TargetRegisterInfo &TRI;
lib/Target/Lanai/LanaiDelaySlotFiller.cpp 38 const TargetRegisterInfo *TRI;
lib/Target/Lanai/LanaiISelLowering.cpp 236 LanaiTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/Lanai/LanaiISelLowering.h 96 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/Lanai/LanaiInstrInfo.cpp 102 const TargetRegisterInfo *TRI = &getRegisterInfo();
319 const TargetRegisterInfo *TRI = &getRegisterInfo();
759 unsigned &Width, const TargetRegisterInfo * /*TRI*/) const {
799 const TargetRegisterInfo *TRI) const {
lib/Target/Lanai/LanaiInstrInfo.h 73 const TargetRegisterInfo *TRI) const override;
78 const TargetRegisterInfo *TRI) const;
lib/Target/MSP430/MSP430ISelLowering.cpp 380 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
lib/Target/MSP430/MSP430ISelLowering.h 106 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/MSP430/MSP430InstrInfo.h 36 const TargetRegisterInfo &getRegisterInfo() const { return RI; }
lib/Target/MSP430/MSP430Subtarget.h 67 const TargetRegisterInfo *getRegisterInfo() const override {
lib/Target/Mips/MipsAsmPrinter.cpp 331 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
378 const TargetRegisterInfo &RI = *MF->getSubtarget().getRegisterInfo();
lib/Target/Mips/MipsCallLowering.cpp 582 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/Mips/MipsDelaySlotFiller.cpp 112 RegDefsUses(const TargetRegisterInfo &TRI);
136 const TargetRegisterInfo &TRI;
346 RegDefsUses::RegDefsUses(const TargetRegisterInfo &TRI)
lib/Target/Mips/MipsFrameLowering.cpp 95 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
104 const TargetRegisterInfo *TRI = STI.getRegisterInfo();
116 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
lib/Target/Mips/MipsISelLowering.cpp 2946 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
3877 const TargetRegisterInfo *TRI =
3953 MipsTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/Mips/MipsISelLowering.h 643 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/Mips/MipsMachineFunction.cpp 151 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
169 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
193 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/Target/Mips/MipsOptimizePICCall.cpp 138 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/Target/Mips/MipsRegisterBankInfo.cpp 76 MipsRegisterBankInfo::MipsRegisterBankInfo(const TargetRegisterInfo &TRI)
341 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/Target/Mips/MipsRegisterBankInfo.h 33 MipsRegisterBankInfo(const TargetRegisterInfo &TRI);
lib/Target/Mips/MipsSEFrameLowering.cpp 856 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
865 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/Mips/MipsSEInstrInfo.cpp 822 const TargetRegisterInfo &TRI = getRegisterInfo();
lib/Target/NVPTX/NVPTXAsmPrinter.cpp 1630 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/NVPTX/NVPTXISelLowering.cpp 4275 NVPTXTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/NVPTX/NVPTXISelLowering.h 480 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp 53 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
132 const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo();
lib/Target/PowerPC/PPCFrameLowering.cpp 341 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
1935 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2110 const TargetRegisterInfo &TRI = *Subtarget.getRegisterInfo();
2132 MachineFunction &MF, const TargetRegisterInfo *TRI,
lib/Target/PowerPC/PPCFrameLowering.h 123 const TargetRegisterInfo *TRI,
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 320 const TargetRegisterInfo *TRI = PPCSubTarget->getRegisterInfo();
lib/Target/PowerPC/PPCISelLowering.cpp 5242 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
14306 PPCTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/PowerPC/PPCISelLowering.h 789 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/PowerPC/PPCInstrInfo.cpp 910 const TargetRegisterInfo *TRI = &getRegisterInfo();
1650 const TargetRegisterInfo *TRI = &getRegisterInfo();
2282 const TargetRegisterInfo *TRI = &getRegisterInfo();
2327 const TargetRegisterInfo *TRI = &getRegisterInfo();
2347 const TargetRegisterInfo *TRI = &getRegisterInfo();
4268 const TargetRegisterInfo *TRI) const {
4300 const TargetRegisterInfo *TRI = &getRegisterInfo();
lib/Target/PowerPC/PPCInstrInfo.h 367 const TargetRegisterInfo *TRI) const;
lib/Target/PowerPC/PPCMIPeephole.cpp 266 const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
lib/Target/PowerPC/PPCPreEmitPeephole.cpp 72 const TargetRegisterInfo *TRI) {
170 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/PowerPC/PPCQPXLoadSplat.cpp 62 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 547 const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
lib/Target/PowerPC/PPCRegisterInfo.cpp 739 const TargetRegisterInfo* TRI = Subtarget.getRegisterInfo();
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 74 const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
lib/Target/RISCV/RISCVFrameLowering.cpp 27 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
327 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
415 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
lib/Target/RISCV/RISCVISelLowering.cpp 1158 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
1190 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
2301 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2555 RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/RISCV/RISCVISelLowering.h 100 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/RISCV/RISCVRegisterBankInfo.cpp 25 RISCVRegisterBankInfo::RISCVRegisterBankInfo(const TargetRegisterInfo &TRI)
lib/Target/RISCV/RISCVRegisterBankInfo.h 34 RISCVRegisterBankInfo(const TargetRegisterInfo &TRI);
lib/Target/Sparc/SparcFrameLowering.cpp 252 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
lib/Target/Sparc/SparcISelLowering.cpp 3255 SparcTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/Sparc/SparcISelLowering.h 93 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/Sparc/SparcInstrInfo.cpp 374 const TargetRegisterInfo *TRI = &getRegisterInfo();
lib/Target/SystemZ/SystemZElimCompare.cpp 99 const TargetRegisterInfo *TRI = nullptr;
lib/Target/SystemZ/SystemZFrameLowering.cpp 70 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
119 const TargetRegisterInfo *RI =
lib/Target/SystemZ/SystemZHazardRecognizer.cpp 119 const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
lib/Target/SystemZ/SystemZISelLowering.cpp 1071 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
1591 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2888 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
lib/Target/SystemZ/SystemZISelLowering.h 423 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/SystemZ/SystemZInstrInfo.cpp 827 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
1001 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
lib/Target/SystemZ/SystemZRegisterInfo.cpp 85 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
lib/Target/SystemZ/SystemZShortenInst.cpp 52 const TargetRegisterInfo *TRI;
lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp 58 const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo();
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 476 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
lib/Target/WebAssembly/WebAssemblyISelLowering.h 55 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/X86/X86CallingConv.cpp 165 const TargetRegisterInfo *TRI =
lib/Target/X86/X86CmovConversion.cpp 116 const TargetRegisterInfo *TRI;
lib/Target/X86/X86DomainReassignment.cpp 52 const TargetRegisterInfo *TRI) {
57 const TargetRegisterInfo *TRI) {
lib/Target/X86/X86FastISel.cpp 2133 const TargetRegisterInfo &TRI = *Subtarget->getRegisterInfo();
lib/Target/X86/X86FlagsCopyLowering.cpp 93 const TargetRegisterInfo *TRI;
lib/Target/X86/X86FloatingPoint.cpp 1683 const TargetRegisterInfo &TRI =
lib/Target/X86/X86FrameLowering.cpp 1960 MachineFunction &MF, const TargetRegisterInfo *TRI,
lib/Target/X86/X86FrameLowering.h 81 const TargetRegisterInfo *TRI,
lib/Target/X86/X86ISelLowering.cpp 2254 X86TargetLowering::findRepresentativeClass(const TargetRegisterInfo *TRI,
2826 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
4064 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
24379 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
29810 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
29965 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
30470 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
45788 X86TargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/X86/X86ISelLowering.h 993 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
1255 findRepresentativeClass(const TargetRegisterInfo *TRI,
lib/Target/X86/X86InstrInfo.cpp 2696 const TargetRegisterInfo *TRI = &getRegisterInfo();
2871 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
3001 const TargetRegisterInfo *TRI = &getRegisterInfo();
3016 const TargetRegisterInfo *TRI = &getRegisterInfo();
3197 const TargetRegisterInfo *TRI) const {
3649 const TargetRegisterInfo *TRI = &getRegisterInfo();
4020 const TargetRegisterInfo *TRI,
4043 const TargetRegisterInfo *TRI,
4107 const TargetRegisterInfo *TRI = &getRegisterInfo();
4121 const TargetRegisterInfo *TRI = &getRegisterInfo();
4135 const TargetRegisterInfo *TRI = &getRegisterInfo();
4342 const TargetRegisterInfo *TRI) const {
4556 const TargetRegisterInfo *TRI) const {
4568 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
4636 const TargetRegisterInfo &TRI = *MRI.getTargetRegisterInfo();
4743 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4767 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4786 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
4899 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5075 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5472 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
5612 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
7577 const TargetRegisterInfo *TRI = &getRegisterInfo();
lib/Target/X86/X86InstrInfo.h 297 const TargetRegisterInfo *TRI) const override;
436 const TargetRegisterInfo *TRI) const override;
438 const TargetRegisterInfo *TRI) const override;
440 const TargetRegisterInfo *TRI) const override;
lib/Target/X86/X86RegisterBankInfo.cpp 28 X86RegisterBankInfo::X86RegisterBankInfo(const TargetRegisterInfo &TRI)
281 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
lib/Target/X86/X86RegisterBankInfo.h 65 X86RegisterBankInfo(const TargetRegisterInfo &TRI);
lib/Target/X86/X86SpeculativeLoadHardening.cpp 164 const TargetRegisterInfo *TRI;
lib/Target/XCore/XCoreFrameLowering.cpp 578 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/Target/XCore/XCoreISelLowering.cpp 782 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
828 const TargetRegisterInfo *RegInfo = Subtarget.getRegisterInfo();
1927 XCoreTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/XCore/XCoreISelLowering.h 195 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
lib/Target/XCore/XCoreInstrInfo.h 34 const TargetRegisterInfo &getRegisterInfo() const { return RI; }
lib/Target/XCore/XCoreMachineFunctionInfo.cpp 39 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
57 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
70 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
lib/Target/XCore/XCoreSubtarget.h 59 const TargetRegisterInfo *getRegisterInfo() const override {
unittests/CodeGen/MachineInstrTest.cpp 52 class BogusRegisterInfo : public TargetRegisterInfo {
116 const TargetRegisterInfo *getRegisterInfo() const override { return &TRI; }