|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
Declarations
include/llvm/CodeGen/FastISel.h 57 class TargetRegisterClass;
include/llvm/CodeGen/GlobalISel/CSEInfo.h 163 class TargetRegisterClass;
include/llvm/CodeGen/GlobalISel/InstructionSelector.h 42 class TargetRegisterClass;
include/llvm/CodeGen/GlobalISel/RegisterBank.h 22 class TargetRegisterClass;
include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h 34 class TargetRegisterClass;
include/llvm/CodeGen/GlobalISel/Utils.h 36 class TargetRegisterClass;
include/llvm/CodeGen/LiveStacks.h 27 class TargetRegisterClass;
include/llvm/CodeGen/MIRParser/MIParser.h 31 class TargetRegisterClass;
include/llvm/CodeGen/MachineBasicBlock.h 45 class TargetRegisterClass;
include/llvm/CodeGen/MachineFunction.h 71 class TargetRegisterClass;
include/llvm/CodeGen/MachineInstr.h 53 class TargetRegisterClass;
include/llvm/CodeGen/MachineSSAUpdater.h 24 class TargetRegisterClass;
include/llvm/CodeGen/Passes.h 28 class TargetRegisterClass;
include/llvm/CodeGen/RegisterScavenging.h 31 class TargetRegisterClass;
include/llvm/CodeGen/ScheduleDAG.h 44 class TargetRegisterClass;
include/llvm/CodeGen/TargetInstrInfo.h 58 class TargetRegisterClass;
include/llvm/CodeGen/TargetLowering.h 89 class TargetRegisterClass;
include/llvm/CodeGen/TargetSubtargetInfo.h 51 class TargetRegisterClass;
lib/CodeGen/AggressiveAntiDepBreaker.h 36 class TargetRegisterClass;
lib/CodeGen/CriticalAntiDepBreaker.h 33 class TargetRegisterClass;
lib/CodeGen/RegisterCoalescer.h 20 class TargetRegisterClass;
lib/Target/AArch64/AArch64RegisterInfo.h 23 class TargetRegisterClass;
lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h 23 class TargetRegisterClass;
lib/Target/AMDGPU/SIInstrInfo.h 43 class TargetRegisterClass;
lib/Target/AMDGPU/SIMachineFunctionInfo.h 41 class TargetRegisterClass;
lib/Target/Hexagon/BitTracker.h 32 class TargetRegisterClass;
lib/Target/Hexagon/HexagonFrameLowering.h 28 class TargetRegisterClass;
lib/Target/Hexagon/HexagonVLIWPacketizer.h 25 class TargetRegisterClass;
lib/Target/Mips/MCTargetDesc/MipsABIInfo.h 21 class TargetRegisterClass;
lib/Target/Mips/MipsISelLowering.h 55 class TargetRegisterClass;
lib/Target/Mips/MipsInstrInfo.h 38 class TargetRegisterClass;
lib/Target/Mips/MipsRegisterInfo.h 25 class TargetRegisterClass;
lib/Target/Mips/MipsSEISelLowering.h 27 class TargetRegisterClass;
lib/Target/WebAssembly/WebAssemblyRegisterInfo.h 25 class TargetRegisterClass;
References
gen/lib/Target/AArch64/AArch64GenRegisterInfo.inc 5033 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
5033 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
5034 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
5039 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
5049 extern const TargetRegisterClass FPR8RegClass;
5050 extern const TargetRegisterClass FPR16RegClass;
5051 extern const TargetRegisterClass PPRRegClass;
5052 extern const TargetRegisterClass PPR_3bRegClass;
5053 extern const TargetRegisterClass GPR32allRegClass;
5054 extern const TargetRegisterClass FPR32RegClass;
5055 extern const TargetRegisterClass GPR32RegClass;
5056 extern const TargetRegisterClass GPR32spRegClass;
5057 extern const TargetRegisterClass GPR32commonRegClass;
5058 extern const TargetRegisterClass GPR32argRegClass;
5059 extern const TargetRegisterClass CCRRegClass;
5060 extern const TargetRegisterClass GPR32sponlyRegClass;
5061 extern const TargetRegisterClass WSeqPairsClassRegClass;
5062 extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass;
5063 extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32argRegClass;
5064 extern const TargetRegisterClass GPR64allRegClass;
5065 extern const TargetRegisterClass FPR64RegClass;
5066 extern const TargetRegisterClass GPR64RegClass;
5067 extern const TargetRegisterClass GPR64spRegClass;
5068 extern const TargetRegisterClass GPR64commonRegClass;
5069 extern const TargetRegisterClass GPR64noipRegClass;
5070 extern const TargetRegisterClass GPR64common_and_GPR64noipRegClass;
5071 extern const TargetRegisterClass tcGPR64RegClass;
5072 extern const TargetRegisterClass GPR64noip_and_tcGPR64RegClass;
5073 extern const TargetRegisterClass GPR64argRegClass;
5074 extern const TargetRegisterClass rtcGPR64RegClass;
5075 extern const TargetRegisterClass GPR64sponlyRegClass;
5076 extern const TargetRegisterClass DDRegClass;
5077 extern const TargetRegisterClass XSeqPairsClassRegClass;
5078 extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass;
5079 extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64noipRegClass;
5080 extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_GPR64noipRegClass;
5081 extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass;
5082 extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClass;
5083 extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass;
5084 extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClass;
5085 extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32argRegClass;
5086 extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_rtcGPR64RegClass;
5087 extern const TargetRegisterClass FPR128RegClass;
5088 extern const TargetRegisterClass ZPRRegClass;
5089 extern const TargetRegisterClass FPR128_loRegClass;
5090 extern const TargetRegisterClass ZPR_4bRegClass;
5091 extern const TargetRegisterClass ZPR_3bRegClass;
5092 extern const TargetRegisterClass DDDRegClass;
5093 extern const TargetRegisterClass DDDDRegClass;
5094 extern const TargetRegisterClass QQRegClass;
5095 extern const TargetRegisterClass ZPR2RegClass;
5096 extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_loRegClass;
5097 extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass;
5098 extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_4bRegClass;
5099 extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_loRegClass;
5100 extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass;
5101 extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass;
5102 extern const TargetRegisterClass ZPR2_with_zsub0_in_ZPR_3bRegClass;
5103 extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_3bRegClass;
5104 extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClass;
5105 extern const TargetRegisterClass QQQRegClass;
5106 extern const TargetRegisterClass ZPR3RegClass;
5107 extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_loRegClass;
5108 extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass;
5109 extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass;
5110 extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4bRegClass;
5111 extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_4bRegClass;
5112 extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_loRegClass;
5113 extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass;
5114 extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass;
5115 extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass;
5116 extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass;
5117 extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass;
5118 extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass;
5119 extern const TargetRegisterClass ZPR3_with_zsub0_in_ZPR_3bRegClass;
5120 extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3bRegClass;
5121 extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_3bRegClass;
5122 extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass;
5123 extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass;
5124 extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClass;
5125 extern const TargetRegisterClass QQQQRegClass;
5126 extern const TargetRegisterClass ZPR4RegClass;
5127 extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_loRegClass;
5128 extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass;
5129 extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass;
5130 extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass;
5131 extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4bRegClass;
5132 extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4bRegClass;
5133 extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_4bRegClass;
5134 extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_loRegClass;
5135 extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass;
5136 extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass;
5137 extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
5138 extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass;
5139 extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass;
5140 extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass;
5141 extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass;
5142 extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
5143 extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass;
5144 extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass;
5145 extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass;
5146 extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass;
5147 extern const TargetRegisterClass ZPR4_with_zsub0_in_ZPR_3bRegClass;
5148 extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3bRegClass;
5149 extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3bRegClass;
5150 extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_3bRegClass;
5151 extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass;
5152 extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass;
5153 extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass;
5154 extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass;
5155 extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass;
5156 extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClass;
5411 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
6106 static const TargetRegisterClass *const PPR_3bSuperclasses[] = {
6111 static const TargetRegisterClass *const GPR32Superclasses[] = {
6116 static const TargetRegisterClass *const GPR32spSuperclasses[] = {
6121 static const TargetRegisterClass *const GPR32commonSuperclasses[] = {
6128 static const TargetRegisterClass *const GPR32argSuperclasses[] = {
6136 static const TargetRegisterClass *const GPR32sponlySuperclasses[] = {
6142 static const TargetRegisterClass *const WSeqPairsClass_with_subo32_in_GPR32commonSuperclasses[] = {
6147 static const TargetRegisterClass *const WSeqPairsClass_with_sube32_in_GPR32argSuperclasses[] = {
6153 static const TargetRegisterClass *const GPR64Superclasses[] = {
6158 static const TargetRegisterClass *const GPR64spSuperclasses[] = {
6163 static const TargetRegisterClass *const GPR64commonSuperclasses[] = {
6170 static const TargetRegisterClass *const GPR64noipSuperclasses[] = {
6176 static const TargetRegisterClass *const GPR64common_and_GPR64noipSuperclasses[] = {
6185 static const TargetRegisterClass *const tcGPR64Superclasses[] = {
6193 static const TargetRegisterClass *const GPR64noip_and_tcGPR64Superclasses[] = {
6204 static const TargetRegisterClass *const GPR64argSuperclasses[] = {
6216 static const TargetRegisterClass *const rtcGPR64Superclasses[] = {
6225 static const TargetRegisterClass *const GPR64sponlySuperclasses[] = {
6231 static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_GPR64commonSuperclasses[] = {
6236 static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_GPR64noipSuperclasses[] = {
6241 static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_GPR64noipSuperclasses[] = {
6248 static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_tcGPR64Superclasses[] = {
6254 static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64Superclasses[] = {
6263 static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_tcGPR64Superclasses[] = {
6270 static const TargetRegisterClass *const XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64Superclasses[] = {
6281 static const TargetRegisterClass *const XSeqPairsClass_with_sub_32_in_GPR32argSuperclasses[] = {
6293 static const TargetRegisterClass *const XSeqPairsClass_with_sube64_in_rtcGPR64Superclasses[] = {
6301 static const TargetRegisterClass *const FPR128_loSuperclasses[] = {
6306 static const TargetRegisterClass *const ZPR_4bSuperclasses[] = {
6311 static const TargetRegisterClass *const ZPR_3bSuperclasses[] = {
6317 static const TargetRegisterClass *const QQ_with_qsub0_in_FPR128_loSuperclasses[] = {
6322 static const TargetRegisterClass *const QQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6327 static const TargetRegisterClass *const ZPR2_with_zsub1_in_ZPR_4bSuperclasses[] = {
6332 static const TargetRegisterClass *const ZPR2_with_zsub_in_FPR128_loSuperclasses[] = {
6337 static const TargetRegisterClass *const QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6344 static const TargetRegisterClass *const ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bSuperclasses[] = {
6351 static const TargetRegisterClass *const ZPR2_with_zsub0_in_ZPR_3bSuperclasses[] = {
6359 static const TargetRegisterClass *const ZPR2_with_zsub1_in_ZPR_3bSuperclasses[] = {
6365 static const TargetRegisterClass *const ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bSuperclasses[] = {
6375 static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_loSuperclasses[] = {
6380 static const TargetRegisterClass *const QQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6385 static const TargetRegisterClass *const QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6390 static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_4bSuperclasses[] = {
6395 static const TargetRegisterClass *const ZPR3_with_zsub2_in_ZPR_4bSuperclasses[] = {
6400 static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_loSuperclasses[] = {
6405 static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6412 static const TargetRegisterClass *const QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6419 static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses[] = {
6426 static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bSuperclasses[] = {
6433 static const TargetRegisterClass *const QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6443 static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bSuperclasses[] = {
6453 static const TargetRegisterClass *const ZPR3_with_zsub0_in_ZPR_3bSuperclasses[] = {
6464 static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_3bSuperclasses[] = {
6472 static const TargetRegisterClass *const ZPR3_with_zsub2_in_ZPR_3bSuperclasses[] = {
6478 static const TargetRegisterClass *const ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses[] = {
6488 static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bSuperclasses[] = {
6501 static const TargetRegisterClass *const ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bSuperclasses[] = {
6517 static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_loSuperclasses[] = {
6522 static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6527 static const TargetRegisterClass *const QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6532 static const TargetRegisterClass *const QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
6537 static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_4bSuperclasses[] = {
6542 static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_4bSuperclasses[] = {
6547 static const TargetRegisterClass *const ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = {
6552 static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_loSuperclasses[] = {
6557 static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loSuperclasses[] = {
6564 static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6571 static const TargetRegisterClass *const QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
6578 static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses[] = {
6585 static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = {
6592 static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bSuperclasses[] = {
6599 static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loSuperclasses[] = {
6609 static const TargetRegisterClass *const QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
6619 static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = {
6629 static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bSuperclasses[] = {
6639 static const TargetRegisterClass *const QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loSuperclasses[] = {
6653 static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bSuperclasses[] = {
6667 static const TargetRegisterClass *const ZPR4_with_zsub0_in_ZPR_3bSuperclasses[] = {
6682 static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_3bSuperclasses[] = {
6693 static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_3bSuperclasses[] = {
6701 static const TargetRegisterClass *const ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = {
6707 static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses[] = {
6720 static const TargetRegisterClass *const ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = {
6730 static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bSuperclasses[] = {
6747 static const TargetRegisterClass *const ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = {
6763 static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bSuperclasses[] = {
6783 static const TargetRegisterClass *const ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bSuperclasses[] = {
6893 extern const TargetRegisterClass FPR8RegClass = {
6905 extern const TargetRegisterClass FPR16RegClass = {
6917 extern const TargetRegisterClass PPRRegClass = {
6929 extern const TargetRegisterClass PPR_3bRegClass = {
6941 extern const TargetRegisterClass GPR32allRegClass = {
6953 extern const TargetRegisterClass FPR32RegClass = {
6965 extern const TargetRegisterClass GPR32RegClass = {
6977 extern const TargetRegisterClass GPR32spRegClass = {
6989 extern const TargetRegisterClass GPR32commonRegClass = {
7001 extern const TargetRegisterClass GPR32argRegClass = {
7013 extern const TargetRegisterClass CCRRegClass = {
7025 extern const TargetRegisterClass GPR32sponlyRegClass = {
7037 extern const TargetRegisterClass WSeqPairsClassRegClass = {
7049 extern const TargetRegisterClass WSeqPairsClass_with_subo32_in_GPR32commonRegClass = {
7061 extern const TargetRegisterClass WSeqPairsClass_with_sube32_in_GPR32argRegClass = {
7073 extern const TargetRegisterClass GPR64allRegClass = {
7085 extern const TargetRegisterClass FPR64RegClass = {
7097 extern const TargetRegisterClass GPR64RegClass = {
7109 extern const TargetRegisterClass GPR64spRegClass = {
7121 extern const TargetRegisterClass GPR64commonRegClass = {
7133 extern const TargetRegisterClass GPR64noipRegClass = {
7145 extern const TargetRegisterClass GPR64common_and_GPR64noipRegClass = {
7157 extern const TargetRegisterClass tcGPR64RegClass = {
7169 extern const TargetRegisterClass GPR64noip_and_tcGPR64RegClass = {
7181 extern const TargetRegisterClass GPR64argRegClass = {
7193 extern const TargetRegisterClass rtcGPR64RegClass = {
7205 extern const TargetRegisterClass GPR64sponlyRegClass = {
7217 extern const TargetRegisterClass DDRegClass = {
7229 extern const TargetRegisterClass XSeqPairsClassRegClass = {
7241 extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64commonRegClass = {
7253 extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64noipRegClass = {
7265 extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_GPR64noipRegClass = {
7277 extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_tcGPR64RegClass = {
7289 extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_GPR64noip_and_tcGPR64RegClass = {
7301 extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_tcGPR64RegClass = {
7313 extern const TargetRegisterClass XSeqPairsClass_with_subo64_in_GPR64noip_and_tcGPR64RegClass = {
7325 extern const TargetRegisterClass XSeqPairsClass_with_sub_32_in_GPR32argRegClass = {
7337 extern const TargetRegisterClass XSeqPairsClass_with_sube64_in_rtcGPR64RegClass = {
7349 extern const TargetRegisterClass FPR128RegClass = {
7361 extern const TargetRegisterClass ZPRRegClass = {
7373 extern const TargetRegisterClass FPR128_loRegClass = {
7385 extern const TargetRegisterClass ZPR_4bRegClass = {
7397 extern const TargetRegisterClass ZPR_3bRegClass = {
7409 extern const TargetRegisterClass DDDRegClass = {
7421 extern const TargetRegisterClass DDDDRegClass = {
7433 extern const TargetRegisterClass QQRegClass = {
7445 extern const TargetRegisterClass ZPR2RegClass = {
7457 extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_loRegClass = {
7469 extern const TargetRegisterClass QQ_with_qsub1_in_FPR128_loRegClass = {
7481 extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_4bRegClass = {
7493 extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_loRegClass = {
7505 extern const TargetRegisterClass QQ_with_qsub0_in_FPR128_lo_and_QQ_with_qsub1_in_FPR128_loRegClass = {
7517 extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_4bRegClass = {
7529 extern const TargetRegisterClass ZPR2_with_zsub0_in_ZPR_3bRegClass = {
7541 extern const TargetRegisterClass ZPR2_with_zsub1_in_ZPR_3bRegClass = {
7553 extern const TargetRegisterClass ZPR2_with_zsub_in_FPR128_lo_and_ZPR2_with_zsub1_in_ZPR_3bRegClass = {
7565 extern const TargetRegisterClass QQQRegClass = {
7577 extern const TargetRegisterClass ZPR3RegClass = {
7589 extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_loRegClass = {
7601 extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_loRegClass = {
7613 extern const TargetRegisterClass QQQ_with_qsub2_in_FPR128_loRegClass = {
7625 extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4bRegClass = {
7637 extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_4bRegClass = {
7649 extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_loRegClass = {
7661 extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub1_in_FPR128_loRegClass = {
7673 extern const TargetRegisterClass QQQ_with_qsub1_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass = {
7685 extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_4b_and_ZPR3_with_zsub2_in_ZPR_4bRegClass = {
7697 extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_4bRegClass = {
7709 extern const TargetRegisterClass QQQ_with_qsub0_in_FPR128_lo_and_QQQ_with_qsub2_in_FPR128_loRegClass = {
7721 extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_4bRegClass = {
7733 extern const TargetRegisterClass ZPR3_with_zsub0_in_ZPR_3bRegClass = {
7745 extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3bRegClass = {
7757 extern const TargetRegisterClass ZPR3_with_zsub2_in_ZPR_3bRegClass = {
7769 extern const TargetRegisterClass ZPR3_with_zsub1_in_ZPR_3b_and_ZPR3_with_zsub2_in_ZPR_3bRegClass = {
7781 extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub1_in_ZPR_3bRegClass = {
7793 extern const TargetRegisterClass ZPR3_with_zsub_in_FPR128_lo_and_ZPR3_with_zsub2_in_ZPR_3bRegClass = {
7805 extern const TargetRegisterClass QQQQRegClass = {
7817 extern const TargetRegisterClass ZPR4RegClass = {
7829 extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_loRegClass = {
7841 extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_loRegClass = {
7853 extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_loRegClass = {
7865 extern const TargetRegisterClass QQQQ_with_qsub3_in_FPR128_loRegClass = {
7877 extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4bRegClass = {
7889 extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4bRegClass = {
7901 extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_4bRegClass = {
7913 extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_loRegClass = {
7925 extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub1_in_FPR128_loRegClass = {
7937 extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass = {
7949 extern const TargetRegisterClass QQQQ_with_qsub2_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
7961 extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub2_in_ZPR_4bRegClass = {
7973 extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass = {
7985 extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_4bRegClass = {
7997 extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub2_in_FPR128_loRegClass = {
8009 extern const TargetRegisterClass QQQQ_with_qsub1_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
8021 extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_4b_and_ZPR4_with_zsub3_in_ZPR_4bRegClass = {
8033 extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_4bRegClass = {
8045 extern const TargetRegisterClass QQQQ_with_qsub0_in_FPR128_lo_and_QQQQ_with_qsub3_in_FPR128_loRegClass = {
8057 extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_4bRegClass = {
8069 extern const TargetRegisterClass ZPR4_with_zsub0_in_ZPR_3bRegClass = {
8081 extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3bRegClass = {
8093 extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3bRegClass = {
8105 extern const TargetRegisterClass ZPR4_with_zsub3_in_ZPR_3bRegClass = {
8117 extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub2_in_ZPR_3bRegClass = {
8129 extern const TargetRegisterClass ZPR4_with_zsub2_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass = {
8141 extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub1_in_ZPR_3bRegClass = {
8153 extern const TargetRegisterClass ZPR4_with_zsub1_in_ZPR_3b_and_ZPR4_with_zsub3_in_ZPR_3bRegClass = {
8165 extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub2_in_ZPR_3bRegClass = {
8177 extern const TargetRegisterClass ZPR4_with_zsub_in_FPR128_lo_and_ZPR4_with_zsub3_in_ZPR_3bRegClass = {
8192 const TargetRegisterClass* const RegisterClasses[] = {
9145 const TargetRegisterClass *AArch64GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
9145 const TargetRegisterClass *AArch64GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
20066 getRegClassWeight(const TargetRegisterClass *RC) const {
20321 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc17306 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
17306 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
17307 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
17312 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
17322 extern const TargetRegisterClass SCC_CLASSRegClass;
17323 extern const TargetRegisterClass SReg_1RegClass;
17324 extern const TargetRegisterClass SReg_1_XEXECRegClass;
17325 extern const TargetRegisterClass SReg_1_with_sub0RegClass;
17326 extern const TargetRegisterClass SReg_1_XEXEC_with_sub0RegClass;
17327 extern const TargetRegisterClass SReg_1_with_sub0_with_sub0_in_SGPR_32RegClass;
17328 extern const TargetRegisterClass SReg_1_with_sub0_with_sub0_in_TTMP_32RegClass;
17329 extern const TargetRegisterClass VReg_1RegClass;
17330 extern const TargetRegisterClass AV_32RegClass;
17331 extern const TargetRegisterClass VS_32RegClass;
17332 extern const TargetRegisterClass VRegOrLds_32RegClass;
17333 extern const TargetRegisterClass AGPR_32RegClass;
17334 extern const TargetRegisterClass VGPR_32RegClass;
17335 extern const TargetRegisterClass SRegOrLds_32RegClass;
17336 extern const TargetRegisterClass SReg_32RegClass;
17337 extern const TargetRegisterClass SReg_32_XEXEC_HIRegClass;
17338 extern const TargetRegisterClass SReg_32_XM0RegClass;
17339 extern const TargetRegisterClass SRegOrLds_32_and_SReg_1RegClass;
17340 extern const TargetRegisterClass SReg_32_XM0_XEXECRegClass;
17341 extern const TargetRegisterClass SGPR_32RegClass;
17342 extern const TargetRegisterClass TTMP_32RegClass;
17343 extern const TargetRegisterClass Pseudo_SReg_32RegClass;
17344 extern const TargetRegisterClass LDS_DIRECT_CLASSRegClass;
17345 extern const TargetRegisterClass M0_CLASSRegClass;
17346 extern const TargetRegisterClass AV_64RegClass;
17347 extern const TargetRegisterClass VS_64RegClass;
17348 extern const TargetRegisterClass AReg_64RegClass;
17349 extern const TargetRegisterClass VReg_64RegClass;
17350 extern const TargetRegisterClass SReg_64RegClass;
17351 extern const TargetRegisterClass SReg_64_XEXECRegClass;
17352 extern const TargetRegisterClass SGPR_64RegClass;
17353 extern const TargetRegisterClass CCR_SGPR_64RegClass;
17354 extern const TargetRegisterClass TTMP_64RegClass;
17355 extern const TargetRegisterClass VReg_96RegClass;
17356 extern const TargetRegisterClass SGPR_96RegClass;
17357 extern const TargetRegisterClass SReg_96RegClass;
17358 extern const TargetRegisterClass SGPR_96_with_sub0_sub1RegClass;
17359 extern const TargetRegisterClass SGPR_96_with_sub1_sub2RegClass;
17360 extern const TargetRegisterClass SGPR_96_with_sub0_sub1_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17361 extern const TargetRegisterClass SGPR_96_with_sub1_sub2_with_sub1_sub2_in_CCR_SGPR_64RegClass;
17362 extern const TargetRegisterClass AReg_128RegClass;
17363 extern const TargetRegisterClass VReg_128RegClass;
17364 extern const TargetRegisterClass SReg_128RegClass;
17365 extern const TargetRegisterClass SGPR_128RegClass;
17366 extern const TargetRegisterClass SGPR_128_with_sub0_sub1_sub2RegClass;
17367 extern const TargetRegisterClass SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17368 extern const TargetRegisterClass SGPR_128_with_sub1_sub2_sub3RegClass;
17369 extern const TargetRegisterClass TTMP_128RegClass;
17370 extern const TargetRegisterClass SGPR_128_with_sub0_sub1_sub2_and_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17371 extern const TargetRegisterClass SGPR_128_with_sub1_sub2_sub3_and_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17372 extern const TargetRegisterClass Pseudo_SReg_128RegClass;
17373 extern const TargetRegisterClass VReg_160RegClass;
17374 extern const TargetRegisterClass SGPR_160RegClass;
17375 extern const TargetRegisterClass SReg_160RegClass;
17376 extern const TargetRegisterClass SGPR_160_with_sub0_sub1_sub2RegClass;
17377 extern const TargetRegisterClass SGPR_160_with_sub2_sub3_sub4RegClass;
17378 extern const TargetRegisterClass SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17379 extern const TargetRegisterClass SGPR_160_with_sub1_sub2_sub3RegClass;
17380 extern const TargetRegisterClass SGPR_160_with_sub0_sub1_sub2_and_SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17381 extern const TargetRegisterClass SGPR_160_with_sub2_sub3_sub4_and_SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17382 extern const TargetRegisterClass SGPR_160_with_sub1_sub2_sub3_and_SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17383 extern const TargetRegisterClass VReg_256RegClass;
17384 extern const TargetRegisterClass SReg_256RegClass;
17385 extern const TargetRegisterClass SGPR_256RegClass;
17386 extern const TargetRegisterClass SGPR_256_with_sub0_sub1_sub2RegClass;
17387 extern const TargetRegisterClass SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17388 extern const TargetRegisterClass SGPR_256_with_sub1_sub2_sub3RegClass;
17389 extern const TargetRegisterClass SGPR_256_with_sub2_sub3_sub4RegClass;
17390 extern const TargetRegisterClass SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17391 extern const TargetRegisterClass SGPR_256_with_sub0_sub1_sub2_and_SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17392 extern const TargetRegisterClass SGPR_256_with_sub2_sub3_sub4_and_SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17393 extern const TargetRegisterClass TTMP_256RegClass;
17394 extern const TargetRegisterClass SGPR_256_with_sub1_sub2_sub3_and_SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17395 extern const TargetRegisterClass SGPR_256_with_sub2_sub3_sub4_and_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17396 extern const TargetRegisterClass AReg_512RegClass;
17397 extern const TargetRegisterClass VReg_512RegClass;
17398 extern const TargetRegisterClass SReg_512RegClass;
17399 extern const TargetRegisterClass SGPR_512RegClass;
17400 extern const TargetRegisterClass SGPR_512_with_sub0_sub1_sub2RegClass;
17401 extern const TargetRegisterClass SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17402 extern const TargetRegisterClass SGPR_512_with_sub2_sub3_sub4RegClass;
17403 extern const TargetRegisterClass SGPR_512_with_sub1_sub2_sub3RegClass;
17404 extern const TargetRegisterClass SGPR_512_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17405 extern const TargetRegisterClass SGPR_512_with_sub8_sub9_sub10_sub11_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17406 extern const TargetRegisterClass SGPR_512_with_sub12_sub13_sub14_sub15_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17407 extern const TargetRegisterClass SGPR_512_with_sub0_sub1_sub2_and_SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17408 extern const TargetRegisterClass SGPR_512_with_sub2_sub3_sub4_and_SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17409 extern const TargetRegisterClass SGPR_512_with_sub0_sub1_sub2_and_SGPR_512_with_sub8_sub9_sub10_sub11_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17410 extern const TargetRegisterClass SGPR_512_with_sub1_sub2_sub3_and_SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17411 extern const TargetRegisterClass SGPR_512_with_sub2_sub3_sub4_and_SGPR_512_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17412 extern const TargetRegisterClass SGPR_512_with_sub1_sub2_sub3_and_SGPR_512_with_sub12_sub13_sub14_sub15_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17413 extern const TargetRegisterClass TTMP_512RegClass;
17414 extern const TargetRegisterClass AReg_1024RegClass;
17415 extern const TargetRegisterClass VReg_1024RegClass;
17416 extern const TargetRegisterClass SGPR_1024RegClass;
17417 extern const TargetRegisterClass SReg_1024RegClass;
17418 extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17419 extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_sub2RegClass;
17420 extern const TargetRegisterClass SGPR_1024_with_sub4_sub5_in_CCR_SGPR_64RegClass;
17421 extern const TargetRegisterClass SGPR_1024_with_sub1_sub2_sub3RegClass;
17422 extern const TargetRegisterClass SGPR_1024_with_sub2_sub3_sub4RegClass;
17423 extern const TargetRegisterClass SGPR_1024_with_sub8_sub9_in_CCR_SGPR_64RegClass;
17424 extern const TargetRegisterClass SGPR_1024_with_sub12_sub13_in_CCR_SGPR_64RegClass;
17425 extern const TargetRegisterClass SGPR_1024_with_sub16_sub17_in_CCR_SGPR_64RegClass;
17426 extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_sub2_and_SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17427 extern const TargetRegisterClass SGPR_1024_with_sub20_sub21_in_CCR_SGPR_64RegClass;
17428 extern const TargetRegisterClass SGPR_1024_with_sub2_sub3_sub4_and_SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17429 extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_sub2_and_SGPR_1024_with_sub8_sub9_in_CCR_SGPR_64RegClass;
17430 extern const TargetRegisterClass SGPR_1024_with_sub1_sub2_sub3_and_SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64RegClass;
17431 extern const TargetRegisterClass SGPR_1024_with_sub24_sub25_in_CCR_SGPR_64RegClass;
17432 extern const TargetRegisterClass SGPR_1024_with_sub2_sub3_sub4_and_SGPR_1024_with_sub4_sub5_in_CCR_SGPR_64RegClass;
17433 extern const TargetRegisterClass SGPR_1024_with_sub1_sub2_sub3_and_SGPR_1024_with_sub12_sub13_in_CCR_SGPR_64RegClass;
17434 extern const TargetRegisterClass SGPR_1024_with_sub28_sub29_in_CCR_SGPR_64RegClass;
17435 extern const TargetRegisterClass SGPR_1024_with_sub2_sub3_sub4_and_SGPR_1024_with_sub16_sub17_in_CCR_SGPR_64RegClass;
17800 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
19605 static const TargetRegisterClass *const SReg_1_XEXECSuperclasses[] = {
19610 static const TargetRegisterClass *const SReg_1_with_sub0Superclasses[] = {
19615 static const TargetRegisterClass *const SReg_1_XEXEC_with_sub0Superclasses[] = {
19622 static const TargetRegisterClass *const SReg_1_with_sub0_with_sub0_in_SGPR_32Superclasses[] = {
19630 static const TargetRegisterClass *const SReg_1_with_sub0_with_sub0_in_TTMP_32Superclasses[] = {
19638 static const TargetRegisterClass *const VRegOrLds_32Superclasses[] = {
19643 static const TargetRegisterClass *const AGPR_32Superclasses[] = {
19648 static const TargetRegisterClass *const VGPR_32Superclasses[] = {
19655 static const TargetRegisterClass *const SRegOrLds_32Superclasses[] = {
19660 static const TargetRegisterClass *const SReg_32Superclasses[] = {
19666 static const TargetRegisterClass *const SReg_32_XEXEC_HISuperclasses[] = {
19673 static const TargetRegisterClass *const SReg_32_XM0Superclasses[] = {
19680 static const TargetRegisterClass *const SRegOrLds_32_and_SReg_1Superclasses[] = {
19690 static const TargetRegisterClass *const SReg_32_XM0_XEXECSuperclasses[] = {
19702 static const TargetRegisterClass *const SGPR_32Superclasses[] = {
19715 static const TargetRegisterClass *const TTMP_32Superclasses[] = {
19728 static const TargetRegisterClass *const LDS_DIRECT_CLASSSuperclasses[] = {
19735 static const TargetRegisterClass *const M0_CLASSSuperclasses[] = {
19743 static const TargetRegisterClass *const AReg_64Superclasses[] = {
19748 static const TargetRegisterClass *const VReg_64Superclasses[] = {
19754 static const TargetRegisterClass *const SReg_64Superclasses[] = {
19761 static const TargetRegisterClass *const SReg_64_XEXECSuperclasses[] = {
19771 static const TargetRegisterClass *const SGPR_64Superclasses[] = {
19783 static const TargetRegisterClass *const CCR_SGPR_64Superclasses[] = {
19796 static const TargetRegisterClass *const TTMP_64Superclasses[] = {
19808 static const TargetRegisterClass *const SGPR_96Superclasses[] = {
19813 static const TargetRegisterClass *const SReg_96Superclasses[] = {
19818 static const TargetRegisterClass *const SGPR_96_with_sub0_sub1Superclasses[] = {
19824 static const TargetRegisterClass *const SGPR_96_with_sub1_sub2Superclasses[] = {
19830 static const TargetRegisterClass *const SGPR_96_with_sub0_sub1_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
19837 static const TargetRegisterClass *const SGPR_96_with_sub1_sub2_with_sub1_sub2_in_CCR_SGPR_64Superclasses[] = {
19844 static const TargetRegisterClass *const SGPR_128Superclasses[] = {
19849 static const TargetRegisterClass *const SGPR_128_with_sub0_sub1_sub2Superclasses[] = {
19855 static const TargetRegisterClass *const SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
19861 static const TargetRegisterClass *const SGPR_128_with_sub1_sub2_sub3Superclasses[] = {
19867 static const TargetRegisterClass *const TTMP_128Superclasses[] = {
19872 static const TargetRegisterClass *const SGPR_128_with_sub0_sub1_sub2_and_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
19880 static const TargetRegisterClass *const SGPR_128_with_sub1_sub2_sub3_and_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
19888 static const TargetRegisterClass *const SGPR_160Superclasses[] = {
19893 static const TargetRegisterClass *const SReg_160Superclasses[] = {
19898 static const TargetRegisterClass *const SGPR_160_with_sub0_sub1_sub2Superclasses[] = {
19904 static const TargetRegisterClass *const SGPR_160_with_sub2_sub3_sub4Superclasses[] = {
19910 static const TargetRegisterClass *const SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
19916 static const TargetRegisterClass *const SGPR_160_with_sub1_sub2_sub3Superclasses[] = {
19922 static const TargetRegisterClass *const SGPR_160_with_sub0_sub1_sub2_and_SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
19930 static const TargetRegisterClass *const SGPR_160_with_sub2_sub3_sub4_and_SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
19938 static const TargetRegisterClass *const SGPR_160_with_sub1_sub2_sub3_and_SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
19946 static const TargetRegisterClass *const SGPR_256Superclasses[] = {
19951 static const TargetRegisterClass *const SGPR_256_with_sub0_sub1_sub2Superclasses[] = {
19957 static const TargetRegisterClass *const SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
19963 static const TargetRegisterClass *const SGPR_256_with_sub1_sub2_sub3Superclasses[] = {
19969 static const TargetRegisterClass *const SGPR_256_with_sub2_sub3_sub4Superclasses[] = {
19975 static const TargetRegisterClass *const SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
19982 static const TargetRegisterClass *const SGPR_256_with_sub0_sub1_sub2_and_SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
19991 static const TargetRegisterClass *const SGPR_256_with_sub2_sub3_sub4_and_SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
19999 static const TargetRegisterClass *const TTMP_256Superclasses[] = {
20004 static const TargetRegisterClass *const SGPR_256_with_sub1_sub2_sub3_and_SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
20013 static const TargetRegisterClass *const SGPR_256_with_sub2_sub3_sub4_and_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
20023 static const TargetRegisterClass *const SGPR_512Superclasses[] = {
20028 static const TargetRegisterClass *const SGPR_512_with_sub0_sub1_sub2Superclasses[] = {
20034 static const TargetRegisterClass *const SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
20040 static const TargetRegisterClass *const SGPR_512_with_sub2_sub3_sub4Superclasses[] = {
20046 static const TargetRegisterClass *const SGPR_512_with_sub1_sub2_sub3Superclasses[] = {
20052 static const TargetRegisterClass *const SGPR_512_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
20059 static const TargetRegisterClass *const SGPR_512_with_sub8_sub9_sub10_sub11_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
20067 static const TargetRegisterClass *const SGPR_512_with_sub12_sub13_sub14_sub15_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
20076 static const TargetRegisterClass *const SGPR_512_with_sub0_sub1_sub2_and_SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
20085 static const TargetRegisterClass *const SGPR_512_with_sub2_sub3_sub4_and_SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
20093 static const TargetRegisterClass *const SGPR_512_with_sub0_sub1_sub2_and_SGPR_512_with_sub8_sub9_sub10_sub11_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
20105 static const TargetRegisterClass *const SGPR_512_with_sub1_sub2_sub3_and_SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
20115 static const TargetRegisterClass *const SGPR_512_with_sub2_sub3_sub4_and_SGPR_512_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
20127 static const TargetRegisterClass *const SGPR_512_with_sub1_sub2_sub3_and_SGPR_512_with_sub12_sub13_sub14_sub15_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
20139 static const TargetRegisterClass *const TTMP_512Superclasses[] = {
20144 static const TargetRegisterClass *const SGPR_1024Superclasses[] = {
20149 static const TargetRegisterClass *const SReg_1024Superclasses[] = {
20154 static const TargetRegisterClass *const SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
20160 static const TargetRegisterClass *const SGPR_1024_with_sub0_sub1_sub2Superclasses[] = {
20166 static const TargetRegisterClass *const SGPR_1024_with_sub4_sub5_in_CCR_SGPR_64Superclasses[] = {
20173 static const TargetRegisterClass *const SGPR_1024_with_sub1_sub2_sub3Superclasses[] = {
20179 static const TargetRegisterClass *const SGPR_1024_with_sub2_sub3_sub4Superclasses[] = {
20185 static const TargetRegisterClass *const SGPR_1024_with_sub8_sub9_in_CCR_SGPR_64Superclasses[] = {
20193 static const TargetRegisterClass *const SGPR_1024_with_sub12_sub13_in_CCR_SGPR_64Superclasses[] = {
20202 static const TargetRegisterClass *const SGPR_1024_with_sub16_sub17_in_CCR_SGPR_64Superclasses[] = {
20212 static const TargetRegisterClass *const SGPR_1024_with_sub0_sub1_sub2_and_SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
20221 static const TargetRegisterClass *const SGPR_1024_with_sub20_sub21_in_CCR_SGPR_64Superclasses[] = {
20232 static const TargetRegisterClass *const SGPR_1024_with_sub2_sub3_sub4_and_SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
20240 static const TargetRegisterClass *const SGPR_1024_with_sub0_sub1_sub2_and_SGPR_1024_with_sub8_sub9_in_CCR_SGPR_64Superclasses[] = {
20253 static const TargetRegisterClass *const SGPR_1024_with_sub1_sub2_sub3_and_SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64Superclasses[] = {
20263 static const TargetRegisterClass *const SGPR_1024_with_sub24_sub25_in_CCR_SGPR_64Superclasses[] = {
20275 static const TargetRegisterClass *const SGPR_1024_with_sub2_sub3_sub4_and_SGPR_1024_with_sub4_sub5_in_CCR_SGPR_64Superclasses[] = {
20287 static const TargetRegisterClass *const SGPR_1024_with_sub1_sub2_sub3_and_SGPR_1024_with_sub12_sub13_in_CCR_SGPR_64Superclasses[] = {
20301 static const TargetRegisterClass *const SGPR_1024_with_sub28_sub29_in_CCR_SGPR_64Superclasses[] = {
20317 static const TargetRegisterClass *const SGPR_1024_with_sub2_sub3_sub4_and_SGPR_1024_with_sub16_sub17_in_CCR_SGPR_64Superclasses[] = {
20335 extern const TargetRegisterClass SCC_CLASSRegClass = {
20347 extern const TargetRegisterClass SReg_1RegClass = {
20359 extern const TargetRegisterClass SReg_1_XEXECRegClass = {
20371 extern const TargetRegisterClass SReg_1_with_sub0RegClass = {
20383 extern const TargetRegisterClass SReg_1_XEXEC_with_sub0RegClass = {
20395 extern const TargetRegisterClass SReg_1_with_sub0_with_sub0_in_SGPR_32RegClass = {
20407 extern const TargetRegisterClass SReg_1_with_sub0_with_sub0_in_TTMP_32RegClass = {
20419 extern const TargetRegisterClass VReg_1RegClass = {
20431 extern const TargetRegisterClass AV_32RegClass = {
20443 extern const TargetRegisterClass VS_32RegClass = {
20455 extern const TargetRegisterClass VRegOrLds_32RegClass = {
20467 extern const TargetRegisterClass AGPR_32RegClass = {
20479 extern const TargetRegisterClass VGPR_32RegClass = {
20491 extern const TargetRegisterClass SRegOrLds_32RegClass = {
20503 extern const TargetRegisterClass SReg_32RegClass = {
20515 extern const TargetRegisterClass SReg_32_XEXEC_HIRegClass = {
20527 extern const TargetRegisterClass SReg_32_XM0RegClass = {
20539 extern const TargetRegisterClass SRegOrLds_32_and_SReg_1RegClass = {
20551 extern const TargetRegisterClass SReg_32_XM0_XEXECRegClass = {
20563 extern const TargetRegisterClass SGPR_32RegClass = {
20575 extern const TargetRegisterClass TTMP_32RegClass = {
20587 extern const TargetRegisterClass Pseudo_SReg_32RegClass = {
20599 extern const TargetRegisterClass LDS_DIRECT_CLASSRegClass = {
20611 extern const TargetRegisterClass M0_CLASSRegClass = {
20623 extern const TargetRegisterClass AV_64RegClass = {
20635 extern const TargetRegisterClass VS_64RegClass = {
20647 extern const TargetRegisterClass AReg_64RegClass = {
20659 extern const TargetRegisterClass VReg_64RegClass = {
20671 extern const TargetRegisterClass SReg_64RegClass = {
20683 extern const TargetRegisterClass SReg_64_XEXECRegClass = {
20695 extern const TargetRegisterClass SGPR_64RegClass = {
20707 extern const TargetRegisterClass CCR_SGPR_64RegClass = {
20719 extern const TargetRegisterClass TTMP_64RegClass = {
20731 extern const TargetRegisterClass VReg_96RegClass = {
20743 extern const TargetRegisterClass SGPR_96RegClass = {
20755 extern const TargetRegisterClass SReg_96RegClass = {
20767 extern const TargetRegisterClass SGPR_96_with_sub0_sub1RegClass = {
20779 extern const TargetRegisterClass SGPR_96_with_sub1_sub2RegClass = {
20791 extern const TargetRegisterClass SGPR_96_with_sub0_sub1_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
20803 extern const TargetRegisterClass SGPR_96_with_sub1_sub2_with_sub1_sub2_in_CCR_SGPR_64RegClass = {
20815 extern const TargetRegisterClass AReg_128RegClass = {
20827 extern const TargetRegisterClass VReg_128RegClass = {
20839 extern const TargetRegisterClass SReg_128RegClass = {
20851 extern const TargetRegisterClass SGPR_128RegClass = {
20863 extern const TargetRegisterClass SGPR_128_with_sub0_sub1_sub2RegClass = {
20875 extern const TargetRegisterClass SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
20887 extern const TargetRegisterClass SGPR_128_with_sub1_sub2_sub3RegClass = {
20899 extern const TargetRegisterClass TTMP_128RegClass = {
20911 extern const TargetRegisterClass SGPR_128_with_sub0_sub1_sub2_and_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
20923 extern const TargetRegisterClass SGPR_128_with_sub1_sub2_sub3_and_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
20935 extern const TargetRegisterClass Pseudo_SReg_128RegClass = {
20947 extern const TargetRegisterClass VReg_160RegClass = {
20959 extern const TargetRegisterClass SGPR_160RegClass = {
20971 extern const TargetRegisterClass SReg_160RegClass = {
20983 extern const TargetRegisterClass SGPR_160_with_sub0_sub1_sub2RegClass = {
20995 extern const TargetRegisterClass SGPR_160_with_sub2_sub3_sub4RegClass = {
21007 extern const TargetRegisterClass SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21019 extern const TargetRegisterClass SGPR_160_with_sub1_sub2_sub3RegClass = {
21031 extern const TargetRegisterClass SGPR_160_with_sub0_sub1_sub2_and_SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21043 extern const TargetRegisterClass SGPR_160_with_sub2_sub3_sub4_and_SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21055 extern const TargetRegisterClass SGPR_160_with_sub1_sub2_sub3_and_SGPR_160_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21067 extern const TargetRegisterClass VReg_256RegClass = {
21079 extern const TargetRegisterClass SReg_256RegClass = {
21091 extern const TargetRegisterClass SGPR_256RegClass = {
21103 extern const TargetRegisterClass SGPR_256_with_sub0_sub1_sub2RegClass = {
21115 extern const TargetRegisterClass SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21127 extern const TargetRegisterClass SGPR_256_with_sub1_sub2_sub3RegClass = {
21139 extern const TargetRegisterClass SGPR_256_with_sub2_sub3_sub4RegClass = {
21151 extern const TargetRegisterClass SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21163 extern const TargetRegisterClass SGPR_256_with_sub0_sub1_sub2_and_SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21175 extern const TargetRegisterClass SGPR_256_with_sub2_sub3_sub4_and_SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21187 extern const TargetRegisterClass TTMP_256RegClass = {
21199 extern const TargetRegisterClass SGPR_256_with_sub1_sub2_sub3_and_SGPR_256_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21211 extern const TargetRegisterClass SGPR_256_with_sub2_sub3_sub4_and_SGPR_256_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21223 extern const TargetRegisterClass AReg_512RegClass = {
21235 extern const TargetRegisterClass VReg_512RegClass = {
21247 extern const TargetRegisterClass SReg_512RegClass = {
21259 extern const TargetRegisterClass SGPR_512RegClass = {
21271 extern const TargetRegisterClass SGPR_512_with_sub0_sub1_sub2RegClass = {
21283 extern const TargetRegisterClass SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21295 extern const TargetRegisterClass SGPR_512_with_sub2_sub3_sub4RegClass = {
21307 extern const TargetRegisterClass SGPR_512_with_sub1_sub2_sub3RegClass = {
21319 extern const TargetRegisterClass SGPR_512_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21331 extern const TargetRegisterClass SGPR_512_with_sub8_sub9_sub10_sub11_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21343 extern const TargetRegisterClass SGPR_512_with_sub12_sub13_sub14_sub15_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21355 extern const TargetRegisterClass SGPR_512_with_sub0_sub1_sub2_and_SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21367 extern const TargetRegisterClass SGPR_512_with_sub2_sub3_sub4_and_SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21379 extern const TargetRegisterClass SGPR_512_with_sub0_sub1_sub2_and_SGPR_512_with_sub8_sub9_sub10_sub11_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21391 extern const TargetRegisterClass SGPR_512_with_sub1_sub2_sub3_and_SGPR_512_with_sub0_sub1_sub2_sub3_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21403 extern const TargetRegisterClass SGPR_512_with_sub2_sub3_sub4_and_SGPR_512_with_sub4_sub5_sub6_sub7_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21415 extern const TargetRegisterClass SGPR_512_with_sub1_sub2_sub3_and_SGPR_512_with_sub12_sub13_sub14_sub15_in_SGPR_128_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21427 extern const TargetRegisterClass TTMP_512RegClass = {
21439 extern const TargetRegisterClass AReg_1024RegClass = {
21451 extern const TargetRegisterClass VReg_1024RegClass = {
21463 extern const TargetRegisterClass SGPR_1024RegClass = {
21475 extern const TargetRegisterClass SReg_1024RegClass = {
21487 extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21499 extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_sub2RegClass = {
21511 extern const TargetRegisterClass SGPR_1024_with_sub4_sub5_in_CCR_SGPR_64RegClass = {
21523 extern const TargetRegisterClass SGPR_1024_with_sub1_sub2_sub3RegClass = {
21535 extern const TargetRegisterClass SGPR_1024_with_sub2_sub3_sub4RegClass = {
21547 extern const TargetRegisterClass SGPR_1024_with_sub8_sub9_in_CCR_SGPR_64RegClass = {
21559 extern const TargetRegisterClass SGPR_1024_with_sub12_sub13_in_CCR_SGPR_64RegClass = {
21571 extern const TargetRegisterClass SGPR_1024_with_sub16_sub17_in_CCR_SGPR_64RegClass = {
21583 extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_sub2_and_SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21595 extern const TargetRegisterClass SGPR_1024_with_sub20_sub21_in_CCR_SGPR_64RegClass = {
21607 extern const TargetRegisterClass SGPR_1024_with_sub2_sub3_sub4_and_SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21619 extern const TargetRegisterClass SGPR_1024_with_sub0_sub1_sub2_and_SGPR_1024_with_sub8_sub9_in_CCR_SGPR_64RegClass = {
21631 extern const TargetRegisterClass SGPR_1024_with_sub1_sub2_sub3_and_SGPR_1024_with_sub0_sub1_in_CCR_SGPR_64RegClass = {
21643 extern const TargetRegisterClass SGPR_1024_with_sub24_sub25_in_CCR_SGPR_64RegClass = {
21655 extern const TargetRegisterClass SGPR_1024_with_sub2_sub3_sub4_and_SGPR_1024_with_sub4_sub5_in_CCR_SGPR_64RegClass = {
21667 extern const TargetRegisterClass SGPR_1024_with_sub1_sub2_sub3_and_SGPR_1024_with_sub12_sub13_in_CCR_SGPR_64RegClass = {
21679 extern const TargetRegisterClass SGPR_1024_with_sub28_sub29_in_CCR_SGPR_64RegClass = {
21691 extern const TargetRegisterClass SGPR_1024_with_sub2_sub3_sub4_and_SGPR_1024_with_sub16_sub17_in_CCR_SGPR_64RegClass = {
21706 const TargetRegisterClass* const RegisterClasses[] = {
25795 const TargetRegisterClass *AMDGPUGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
25795 const TargetRegisterClass *AMDGPUGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
47924 getRegClassWeight(const TargetRegisterClass *RC) const {
48682 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/AMDGPU/R600GenRegisterInfo.inc 8793 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
8793 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
8794 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
8799 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
8809 extern const TargetRegisterClass R600_Reg32RegClass;
8810 extern const TargetRegisterClass R600_TReg32RegClass;
8811 extern const TargetRegisterClass R600_TReg32_XRegClass;
8812 extern const TargetRegisterClass R600_AddrRegClass;
8813 extern const TargetRegisterClass R600_KC0RegClass;
8814 extern const TargetRegisterClass R600_KC1RegClass;
8815 extern const TargetRegisterClass R600_TReg32_WRegClass;
8816 extern const TargetRegisterClass R600_TReg32_YRegClass;
8817 extern const TargetRegisterClass R600_TReg32_ZRegClass;
8818 extern const TargetRegisterClass R600_ArrayBaseRegClass;
8819 extern const TargetRegisterClass R600_KC0_WRegClass;
8820 extern const TargetRegisterClass R600_KC0_XRegClass;
8821 extern const TargetRegisterClass R600_KC0_YRegClass;
8822 extern const TargetRegisterClass R600_KC0_ZRegClass;
8823 extern const TargetRegisterClass R600_KC1_WRegClass;
8824 extern const TargetRegisterClass R600_KC1_XRegClass;
8825 extern const TargetRegisterClass R600_KC1_YRegClass;
8826 extern const TargetRegisterClass R600_KC1_ZRegClass;
8827 extern const TargetRegisterClass R600_LDS_SRC_REGRegClass;
8828 extern const TargetRegisterClass R600_PredicateRegClass;
8829 extern const TargetRegisterClass R600_Addr_WRegClass;
8830 extern const TargetRegisterClass R600_Addr_YRegClass;
8831 extern const TargetRegisterClass R600_Addr_ZRegClass;
8832 extern const TargetRegisterClass R600_LDS_SRC_REG_and_R600_Reg32RegClass;
8833 extern const TargetRegisterClass R600_Predicate_BitRegClass;
8834 extern const TargetRegisterClass R600_Reg64RegClass;
8835 extern const TargetRegisterClass R600_Reg64VerticalRegClass;
8836 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClass;
8837 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClass;
8838 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClass;
8839 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClass;
8840 extern const TargetRegisterClass R600_Reg128RegClass;
8841 extern const TargetRegisterClass R600_Reg128VerticalRegClass;
8842 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClass;
8843 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClass;
8844 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClass;
8845 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClass;
8941 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
9119 static const TargetRegisterClass *const R600_TReg32Superclasses[] = {
9124 static const TargetRegisterClass *const R600_TReg32_XSuperclasses[] = {
9130 static const TargetRegisterClass *const R600_AddrSuperclasses[] = {
9135 static const TargetRegisterClass *const R600_KC0Superclasses[] = {
9140 static const TargetRegisterClass *const R600_KC1Superclasses[] = {
9145 static const TargetRegisterClass *const R600_TReg32_WSuperclasses[] = {
9151 static const TargetRegisterClass *const R600_TReg32_YSuperclasses[] = {
9157 static const TargetRegisterClass *const R600_TReg32_ZSuperclasses[] = {
9163 static const TargetRegisterClass *const R600_ArrayBaseSuperclasses[] = {
9168 static const TargetRegisterClass *const R600_KC0_WSuperclasses[] = {
9174 static const TargetRegisterClass *const R600_KC0_XSuperclasses[] = {
9180 static const TargetRegisterClass *const R600_KC0_YSuperclasses[] = {
9186 static const TargetRegisterClass *const R600_KC0_ZSuperclasses[] = {
9192 static const TargetRegisterClass *const R600_KC1_WSuperclasses[] = {
9198 static const TargetRegisterClass *const R600_KC1_XSuperclasses[] = {
9204 static const TargetRegisterClass *const R600_KC1_YSuperclasses[] = {
9210 static const TargetRegisterClass *const R600_KC1_ZSuperclasses[] = {
9216 static const TargetRegisterClass *const R600_LDS_SRC_REG_and_R600_Reg32Superclasses[] = {
9222 static const TargetRegisterClass *const R600_Reg64Vertical_with_sub0_in_R600_TReg32_WSuperclasses[] = {
9227 static const TargetRegisterClass *const R600_Reg64Vertical_with_sub0_in_R600_TReg32_XSuperclasses[] = {
9232 static const TargetRegisterClass *const R600_Reg64Vertical_with_sub0_in_R600_TReg32_YSuperclasses[] = {
9237 static const TargetRegisterClass *const R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZSuperclasses[] = {
9242 static const TargetRegisterClass *const R600_Reg128Vertical_with_sub0_in_R600_TReg32_WSuperclasses[] = {
9247 static const TargetRegisterClass *const R600_Reg128Vertical_with_sub0_in_R600_TReg32_XSuperclasses[] = {
9252 static const TargetRegisterClass *const R600_Reg128Vertical_with_sub0_in_R600_TReg32_YSuperclasses[] = {
9257 static const TargetRegisterClass *const R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZSuperclasses[] = {
9264 extern const TargetRegisterClass R600_Reg32RegClass = {
9276 extern const TargetRegisterClass R600_TReg32RegClass = {
9288 extern const TargetRegisterClass R600_TReg32_XRegClass = {
9300 extern const TargetRegisterClass R600_AddrRegClass = {
9312 extern const TargetRegisterClass R600_KC0RegClass = {
9324 extern const TargetRegisterClass R600_KC1RegClass = {
9336 extern const TargetRegisterClass R600_TReg32_WRegClass = {
9348 extern const TargetRegisterClass R600_TReg32_YRegClass = {
9360 extern const TargetRegisterClass R600_TReg32_ZRegClass = {
9372 extern const TargetRegisterClass R600_ArrayBaseRegClass = {
9384 extern const TargetRegisterClass R600_KC0_WRegClass = {
9396 extern const TargetRegisterClass R600_KC0_XRegClass = {
9408 extern const TargetRegisterClass R600_KC0_YRegClass = {
9420 extern const TargetRegisterClass R600_KC0_ZRegClass = {
9432 extern const TargetRegisterClass R600_KC1_WRegClass = {
9444 extern const TargetRegisterClass R600_KC1_XRegClass = {
9456 extern const TargetRegisterClass R600_KC1_YRegClass = {
9468 extern const TargetRegisterClass R600_KC1_ZRegClass = {
9480 extern const TargetRegisterClass R600_LDS_SRC_REGRegClass = {
9492 extern const TargetRegisterClass R600_PredicateRegClass = {
9504 extern const TargetRegisterClass R600_Addr_WRegClass = {
9516 extern const TargetRegisterClass R600_Addr_YRegClass = {
9528 extern const TargetRegisterClass R600_Addr_ZRegClass = {
9540 extern const TargetRegisterClass R600_LDS_SRC_REG_and_R600_Reg32RegClass = {
9552 extern const TargetRegisterClass R600_Predicate_BitRegClass = {
9564 extern const TargetRegisterClass R600_Reg64RegClass = {
9576 extern const TargetRegisterClass R600_Reg64VerticalRegClass = {
9588 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_WRegClass = {
9600 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_XRegClass = {
9612 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_YRegClass = {
9624 extern const TargetRegisterClass R600_Reg64Vertical_with_sub0_in_R600_TReg32_ZRegClass = {
9636 extern const TargetRegisterClass R600_Reg128RegClass = {
9648 extern const TargetRegisterClass R600_Reg128VerticalRegClass = {
9660 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_WRegClass = {
9672 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_XRegClass = {
9684 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_YRegClass = {
9696 extern const TargetRegisterClass R600_Reg128Vertical_with_sub0_in_R600_TReg32_ZRegClass = {
9711 const TargetRegisterClass* const RegisterClasses[] = {
11507 const TargetRegisterClass *R600GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
11507 const TargetRegisterClass *R600GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
12186 getRegClassWeight(const TargetRegisterClass *RC) const {
12326 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/ARC/ARCGenRegisterInfo.inc 513 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
518 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
528 extern const TargetRegisterClass SREGRegClass;
529 extern const TargetRegisterClass GPR_SRegClass;
530 extern const TargetRegisterClass GPR32RegClass;
531 extern const TargetRegisterClass GPR32_and_GPR_SRegClass;
575 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
597 static const TargetRegisterClass *const GPR32_and_GPR_SSuperclasses[] = {
605 extern const TargetRegisterClass SREGRegClass = {
617 extern const TargetRegisterClass GPR_SRegClass = {
629 extern const TargetRegisterClass GPR32RegClass = {
641 extern const TargetRegisterClass GPR32_and_GPR_SRegClass = {
656 const TargetRegisterClass* const RegisterClasses[] = {
702 getRegClassWeight(const TargetRegisterClass *RC) const {
758 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/ARM/ARMGenRegisterInfo.inc 3585 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
3585 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
3586 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3591 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
3601 extern const TargetRegisterClass HPRRegClass;
3602 extern const TargetRegisterClass FPWithVPRRegClass;
3603 extern const TargetRegisterClass SPRRegClass;
3604 extern const TargetRegisterClass FPWithVPR_with_ssub_0RegClass;
3605 extern const TargetRegisterClass GPRRegClass;
3606 extern const TargetRegisterClass GPRwithAPSRRegClass;
3607 extern const TargetRegisterClass GPRwithZRRegClass;
3608 extern const TargetRegisterClass SPR_8RegClass;
3609 extern const TargetRegisterClass GPRnopcRegClass;
3610 extern const TargetRegisterClass GPRwithAPSRnospRegClass;
3611 extern const TargetRegisterClass GPRwithZRnospRegClass;
3612 extern const TargetRegisterClass rGPRRegClass;
3613 extern const TargetRegisterClass tGPRwithpcRegClass;
3614 extern const TargetRegisterClass FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClass;
3615 extern const TargetRegisterClass hGPRRegClass;
3616 extern const TargetRegisterClass tGPRRegClass;
3617 extern const TargetRegisterClass tGPREvenRegClass;
3618 extern const TargetRegisterClass GPRnopc_and_hGPRRegClass;
3619 extern const TargetRegisterClass GPRwithAPSRnosp_and_hGPRRegClass;
3620 extern const TargetRegisterClass tGPROddRegClass;
3621 extern const TargetRegisterClass tcGPRRegClass;
3622 extern const TargetRegisterClass hGPR_and_tGPREvenRegClass;
3623 extern const TargetRegisterClass tGPR_and_tGPREvenRegClass;
3624 extern const TargetRegisterClass tGPR_and_tGPROddRegClass;
3625 extern const TargetRegisterClass tGPR_and_tcGPRRegClass;
3626 extern const TargetRegisterClass tGPREven_and_tcGPRRegClass;
3627 extern const TargetRegisterClass hGPR_and_tGPROddRegClass;
3628 extern const TargetRegisterClass tGPREven_and_tGPR_and_tcGPRRegClass;
3629 extern const TargetRegisterClass tGPROdd_and_tcGPRRegClass;
3630 extern const TargetRegisterClass CCRRegClass;
3631 extern const TargetRegisterClass GPRlrRegClass;
3632 extern const TargetRegisterClass GPRspRegClass;
3633 extern const TargetRegisterClass VCCRRegClass;
3634 extern const TargetRegisterClass cl_FPSCR_NZCVRegClass;
3635 extern const TargetRegisterClass hGPR_and_tGPRwithpcRegClass;
3636 extern const TargetRegisterClass hGPR_and_tcGPRRegClass;
3637 extern const TargetRegisterClass DPRRegClass;
3638 extern const TargetRegisterClass DPR_VFP2RegClass;
3639 extern const TargetRegisterClass DPR_8RegClass;
3640 extern const TargetRegisterClass GPRPairRegClass;
3641 extern const TargetRegisterClass GPRPairnospRegClass;
3642 extern const TargetRegisterClass GPRPair_with_gsub_0_in_tGPRRegClass;
3643 extern const TargetRegisterClass GPRPair_with_gsub_0_in_hGPRRegClass;
3644 extern const TargetRegisterClass GPRPair_with_gsub_0_in_tcGPRRegClass;
3645 extern const TargetRegisterClass GPRPair_with_gsub_1_in_tcGPRRegClass;
3646 extern const TargetRegisterClass GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClass;
3647 extern const TargetRegisterClass GPRPair_with_gsub_1_in_GPRspRegClass;
3648 extern const TargetRegisterClass DPairSpcRegClass;
3649 extern const TargetRegisterClass DPairSpc_with_ssub_0RegClass;
3650 extern const TargetRegisterClass DPairSpc_with_ssub_4RegClass;
3651 extern const TargetRegisterClass DPairSpc_with_dsub_0_in_DPR_8RegClass;
3652 extern const TargetRegisterClass DPairSpc_with_dsub_2_in_DPR_8RegClass;
3653 extern const TargetRegisterClass DPairRegClass;
3654 extern const TargetRegisterClass DPair_with_ssub_0RegClass;
3655 extern const TargetRegisterClass QPRRegClass;
3656 extern const TargetRegisterClass DPair_with_ssub_2RegClass;
3657 extern const TargetRegisterClass DPair_with_dsub_0_in_DPR_8RegClass;
3658 extern const TargetRegisterClass MQPRRegClass;
3659 extern const TargetRegisterClass QPR_VFP2RegClass;
3660 extern const TargetRegisterClass DPair_with_dsub_1_in_DPR_8RegClass;
3661 extern const TargetRegisterClass QPR_8RegClass;
3662 extern const TargetRegisterClass DTripleRegClass;
3663 extern const TargetRegisterClass DTripleSpcRegClass;
3664 extern const TargetRegisterClass DTripleSpc_with_ssub_0RegClass;
3665 extern const TargetRegisterClass DTriple_with_ssub_0RegClass;
3666 extern const TargetRegisterClass DTriple_with_qsub_0_in_QPRRegClass;
3667 extern const TargetRegisterClass DTriple_with_ssub_2RegClass;
3668 extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3669 extern const TargetRegisterClass DTripleSpc_with_ssub_4RegClass;
3670 extern const TargetRegisterClass DTriple_with_ssub_4RegClass;
3671 extern const TargetRegisterClass DTripleSpc_with_ssub_8RegClass;
3672 extern const TargetRegisterClass DTripleSpc_with_dsub_0_in_DPR_8RegClass;
3673 extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8RegClass;
3674 extern const TargetRegisterClass DTriple_with_qsub_0_in_MQPRRegClass;
3675 extern const TargetRegisterClass DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3676 extern const TargetRegisterClass DTriple_with_dsub_1_in_DPR_8RegClass;
3677 extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass;
3678 extern const TargetRegisterClass DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClass;
3679 extern const TargetRegisterClass DTripleSpc_with_dsub_2_in_DPR_8RegClass;
3680 extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8RegClass;
3681 extern const TargetRegisterClass DTripleSpc_with_dsub_4_in_DPR_8RegClass;
3682 extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass;
3683 extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_8RegClass;
3684 extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClass;
3685 extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass;
3686 extern const TargetRegisterClass DQuadSpcRegClass;
3687 extern const TargetRegisterClass DQuadSpc_with_ssub_0RegClass;
3688 extern const TargetRegisterClass DQuadSpc_with_ssub_4RegClass;
3689 extern const TargetRegisterClass DQuadSpc_with_ssub_8RegClass;
3690 extern const TargetRegisterClass DQuadSpc_with_dsub_0_in_DPR_8RegClass;
3691 extern const TargetRegisterClass DQuadSpc_with_dsub_2_in_DPR_8RegClass;
3692 extern const TargetRegisterClass DQuadSpc_with_dsub_4_in_DPR_8RegClass;
3693 extern const TargetRegisterClass DQuadRegClass;
3694 extern const TargetRegisterClass DQuad_with_ssub_0RegClass;
3695 extern const TargetRegisterClass DQuad_with_ssub_2RegClass;
3696 extern const TargetRegisterClass QQPRRegClass;
3697 extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3698 extern const TargetRegisterClass DQuad_with_ssub_4RegClass;
3699 extern const TargetRegisterClass DQuad_with_ssub_6RegClass;
3700 extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8RegClass;
3701 extern const TargetRegisterClass DQuad_with_qsub_0_in_MQPRRegClass;
3702 extern const TargetRegisterClass DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass;
3703 extern const TargetRegisterClass DQuad_with_dsub_1_in_DPR_8RegClass;
3704 extern const TargetRegisterClass DQuad_with_qsub_1_in_MQPRRegClass;
3705 extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass;
3706 extern const TargetRegisterClass DQuad_with_dsub_2_in_DPR_8RegClass;
3707 extern const TargetRegisterClass DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass;
3708 extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8RegClass;
3709 extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass;
3710 extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_8RegClass;
3711 extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_8RegClass;
3712 extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass;
3713 extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass;
3714 extern const TargetRegisterClass QQQQPRRegClass;
3715 extern const TargetRegisterClass QQQQPR_with_ssub_0RegClass;
3716 extern const TargetRegisterClass QQQQPR_with_ssub_4RegClass;
3717 extern const TargetRegisterClass QQQQPR_with_ssub_8RegClass;
3718 extern const TargetRegisterClass QQQQPR_with_ssub_12RegClass;
3719 extern const TargetRegisterClass QQQQPR_with_dsub_0_in_DPR_8RegClass;
3720 extern const TargetRegisterClass QQQQPR_with_dsub_2_in_DPR_8RegClass;
3721 extern const TargetRegisterClass QQQQPR_with_dsub_4_in_DPR_8RegClass;
3722 extern const TargetRegisterClass QQQQPR_with_dsub_6_in_DPR_8RegClass;
3950 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
4905 static const TargetRegisterClass *const SPRSuperclasses[] = {
4911 static const TargetRegisterClass *const FPWithVPR_with_ssub_0Superclasses[] = {
4916 static const TargetRegisterClass *const SPR_8Superclasses[] = {
4923 static const TargetRegisterClass *const GPRnopcSuperclasses[] = {
4930 static const TargetRegisterClass *const GPRwithZRnospSuperclasses[] = {
4935 static const TargetRegisterClass *const rGPRSuperclasses[] = {
4945 static const TargetRegisterClass *const tGPRwithpcSuperclasses[] = {
4950 static const TargetRegisterClass *const FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8Superclasses[] = {
4956 static const TargetRegisterClass *const hGPRSuperclasses[] = {
4961 static const TargetRegisterClass *const tGPRSuperclasses[] = {
4973 static const TargetRegisterClass *const tGPREvenSuperclasses[] = {
4984 static const TargetRegisterClass *const GPRnopc_and_hGPRSuperclasses[] = {
4993 static const TargetRegisterClass *const GPRwithAPSRnosp_and_hGPRSuperclasses[] = {
5006 static const TargetRegisterClass *const tGPROddSuperclasses[] = {
5017 static const TargetRegisterClass *const tcGPRSuperclasses[] = {
5028 static const TargetRegisterClass *const hGPR_and_tGPREvenSuperclasses[] = {
5043 static const TargetRegisterClass *const tGPR_and_tGPREvenSuperclasses[] = {
5057 static const TargetRegisterClass *const tGPR_and_tGPROddSuperclasses[] = {
5071 static const TargetRegisterClass *const tGPR_and_tcGPRSuperclasses[] = {
5085 static const TargetRegisterClass *const tGPREven_and_tcGPRSuperclasses[] = {
5098 static const TargetRegisterClass *const hGPR_and_tGPROddSuperclasses[] = {
5113 static const TargetRegisterClass *const tGPREven_and_tGPR_and_tcGPRSuperclasses[] = {
5131 static const TargetRegisterClass *const tGPROdd_and_tcGPRSuperclasses[] = {
5148 static const TargetRegisterClass *const GPRlrSuperclasses[] = {
5164 static const TargetRegisterClass *const GPRspSuperclasses[] = {
5174 static const TargetRegisterClass *const VCCRSuperclasses[] = {
5179 static const TargetRegisterClass *const hGPR_and_tGPRwithpcSuperclasses[] = {
5186 static const TargetRegisterClass *const hGPR_and_tcGPRSuperclasses[] = {
5204 static const TargetRegisterClass *const DPRSuperclasses[] = {
5209 static const TargetRegisterClass *const DPR_VFP2Superclasses[] = {
5216 static const TargetRegisterClass *const DPR_8Superclasses[] = {
5225 static const TargetRegisterClass *const GPRPairnospSuperclasses[] = {
5230 static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tGPRSuperclasses[] = {
5236 static const TargetRegisterClass *const GPRPair_with_gsub_0_in_hGPRSuperclasses[] = {
5241 static const TargetRegisterClass *const GPRPair_with_gsub_0_in_tcGPRSuperclasses[] = {
5246 static const TargetRegisterClass *const GPRPair_with_gsub_1_in_tcGPRSuperclasses[] = {
5254 static const TargetRegisterClass *const GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRSuperclasses[] = {
5261 static const TargetRegisterClass *const GPRPair_with_gsub_1_in_GPRspSuperclasses[] = {
5268 static const TargetRegisterClass *const DPairSpc_with_ssub_0Superclasses[] = {
5273 static const TargetRegisterClass *const DPairSpc_with_ssub_4Superclasses[] = {
5279 static const TargetRegisterClass *const DPairSpc_with_dsub_0_in_DPR_8Superclasses[] = {
5286 static const TargetRegisterClass *const DPairSpc_with_dsub_2_in_DPR_8Superclasses[] = {
5294 static const TargetRegisterClass *const DPair_with_ssub_0Superclasses[] = {
5299 static const TargetRegisterClass *const QPRSuperclasses[] = {
5304 static const TargetRegisterClass *const DPair_with_ssub_2Superclasses[] = {
5310 static const TargetRegisterClass *const DPair_with_dsub_0_in_DPR_8Superclasses[] = {
5317 static const TargetRegisterClass *const MQPRSuperclasses[] = {
5326 static const TargetRegisterClass *const QPR_VFP2Superclasses[] = {
5335 static const TargetRegisterClass *const DPair_with_dsub_1_in_DPR_8Superclasses[] = {
5343 static const TargetRegisterClass *const QPR_8Superclasses[] = {
5355 static const TargetRegisterClass *const DTripleSpc_with_ssub_0Superclasses[] = {
5360 static const TargetRegisterClass *const DTriple_with_ssub_0Superclasses[] = {
5365 static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPRSuperclasses[] = {
5370 static const TargetRegisterClass *const DTriple_with_ssub_2Superclasses[] = {
5376 static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5381 static const TargetRegisterClass *const DTripleSpc_with_ssub_4Superclasses[] = {
5387 static const TargetRegisterClass *const DTriple_with_ssub_4Superclasses[] = {
5394 static const TargetRegisterClass *const DTripleSpc_with_ssub_8Superclasses[] = {
5401 static const TargetRegisterClass *const DTripleSpc_with_dsub_0_in_DPR_8Superclasses[] = {
5409 static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8Superclasses[] = {
5417 static const TargetRegisterClass *const DTriple_with_qsub_0_in_MQPRSuperclasses[] = {
5425 static const TargetRegisterClass *const DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5432 static const TargetRegisterClass *const DTriple_with_dsub_1_in_DPR_8Superclasses[] = {
5441 static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = {
5451 static const TargetRegisterClass *const DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRSuperclasses[] = {
5461 static const TargetRegisterClass *const DTripleSpc_with_dsub_2_in_DPR_8Superclasses[] = {
5470 static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8Superclasses[] = {
5480 static const TargetRegisterClass *const DTripleSpc_with_dsub_4_in_DPR_8Superclasses[] = {
5490 static const TargetRegisterClass *const DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = {
5502 static const TargetRegisterClass *const DTriple_with_qsub_0_in_QPR_8Superclasses[] = {
5515 static const TargetRegisterClass *const DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRSuperclasses[] = {
5530 static const TargetRegisterClass *const DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = {
5545 static const TargetRegisterClass *const DQuadSpcSuperclasses[] = {
5550 static const TargetRegisterClass *const DQuadSpc_with_ssub_0Superclasses[] = {
5557 static const TargetRegisterClass *const DQuadSpc_with_ssub_4Superclasses[] = {
5566 static const TargetRegisterClass *const DQuadSpc_with_ssub_8Superclasses[] = {
5577 static const TargetRegisterClass *const DQuadSpc_with_dsub_0_in_DPR_8Superclasses[] = {
5590 static const TargetRegisterClass *const DQuadSpc_with_dsub_2_in_DPR_8Superclasses[] = {
5605 static const TargetRegisterClass *const DQuadSpc_with_dsub_4_in_DPR_8Superclasses[] = {
5622 static const TargetRegisterClass *const DQuad_with_ssub_0Superclasses[] = {
5627 static const TargetRegisterClass *const DQuad_with_ssub_2Superclasses[] = {
5633 static const TargetRegisterClass *const QQPRSuperclasses[] = {
5638 static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5643 static const TargetRegisterClass *const DQuad_with_ssub_4Superclasses[] = {
5650 static const TargetRegisterClass *const DQuad_with_ssub_6Superclasses[] = {
5658 static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8Superclasses[] = {
5667 static const TargetRegisterClass *const DQuad_with_qsub_0_in_MQPRSuperclasses[] = {
5675 static const TargetRegisterClass *const DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRSuperclasses[] = {
5682 static const TargetRegisterClass *const DQuad_with_dsub_1_in_DPR_8Superclasses[] = {
5692 static const TargetRegisterClass *const DQuad_with_qsub_1_in_MQPRSuperclasses[] = {
5703 static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = {
5713 static const TargetRegisterClass *const DQuad_with_dsub_2_in_DPR_8Superclasses[] = {
5724 static const TargetRegisterClass *const DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = {
5736 static const TargetRegisterClass *const DQuad_with_dsub_3_in_DPR_8Superclasses[] = {
5748 static const TargetRegisterClass *const DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = {
5762 static const TargetRegisterClass *const DQuad_with_qsub_0_in_QPR_8Superclasses[] = {
5776 static const TargetRegisterClass *const DQuad_with_qsub_1_in_QPR_8Superclasses[] = {
5793 static const TargetRegisterClass *const DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8Superclasses[] = {
5810 static const TargetRegisterClass *const DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRSuperclasses[] = {
5829 static const TargetRegisterClass *const QQQQPR_with_ssub_0Superclasses[] = {
5834 static const TargetRegisterClass *const QQQQPR_with_ssub_4Superclasses[] = {
5840 static const TargetRegisterClass *const QQQQPR_with_ssub_8Superclasses[] = {
5847 static const TargetRegisterClass *const QQQQPR_with_ssub_12Superclasses[] = {
5855 static const TargetRegisterClass *const QQQQPR_with_dsub_0_in_DPR_8Superclasses[] = {
5864 static const TargetRegisterClass *const QQQQPR_with_dsub_2_in_DPR_8Superclasses[] = {
5874 static const TargetRegisterClass *const QQQQPR_with_dsub_4_in_DPR_8Superclasses[] = {
5885 static const TargetRegisterClass *const QQQQPR_with_dsub_6_in_DPR_8Superclasses[] = {
6545 extern const TargetRegisterClass HPRRegClass = {
6557 extern const TargetRegisterClass FPWithVPRRegClass = {
6569 extern const TargetRegisterClass SPRRegClass = {
6581 extern const TargetRegisterClass FPWithVPR_with_ssub_0RegClass = {
6593 extern const TargetRegisterClass GPRRegClass = {
6605 extern const TargetRegisterClass GPRwithAPSRRegClass = {
6617 extern const TargetRegisterClass GPRwithZRRegClass = {
6629 extern const TargetRegisterClass SPR_8RegClass = {
6641 extern const TargetRegisterClass GPRnopcRegClass = {
6653 extern const TargetRegisterClass GPRwithAPSRnospRegClass = {
6665 extern const TargetRegisterClass GPRwithZRnospRegClass = {
6677 extern const TargetRegisterClass rGPRRegClass = {
6689 extern const TargetRegisterClass tGPRwithpcRegClass = {
6701 extern const TargetRegisterClass FPWithVPR_with_ssub_0_with_ssub_0_in_SPR_8RegClass = {
6713 extern const TargetRegisterClass hGPRRegClass = {
6725 extern const TargetRegisterClass tGPRRegClass = {
6737 extern const TargetRegisterClass tGPREvenRegClass = {
6749 extern const TargetRegisterClass GPRnopc_and_hGPRRegClass = {
6761 extern const TargetRegisterClass GPRwithAPSRnosp_and_hGPRRegClass = {
6773 extern const TargetRegisterClass tGPROddRegClass = {
6785 extern const TargetRegisterClass tcGPRRegClass = {
6797 extern const TargetRegisterClass hGPR_and_tGPREvenRegClass = {
6809 extern const TargetRegisterClass tGPR_and_tGPREvenRegClass = {
6821 extern const TargetRegisterClass tGPR_and_tGPROddRegClass = {
6833 extern const TargetRegisterClass tGPR_and_tcGPRRegClass = {
6845 extern const TargetRegisterClass tGPREven_and_tcGPRRegClass = {
6857 extern const TargetRegisterClass hGPR_and_tGPROddRegClass = {
6869 extern const TargetRegisterClass tGPREven_and_tGPR_and_tcGPRRegClass = {
6881 extern const TargetRegisterClass tGPROdd_and_tcGPRRegClass = {
6893 extern const TargetRegisterClass CCRRegClass = {
6905 extern const TargetRegisterClass GPRlrRegClass = {
6917 extern const TargetRegisterClass GPRspRegClass = {
6929 extern const TargetRegisterClass VCCRRegClass = {
6941 extern const TargetRegisterClass cl_FPSCR_NZCVRegClass = {
6953 extern const TargetRegisterClass hGPR_and_tGPRwithpcRegClass = {
6965 extern const TargetRegisterClass hGPR_and_tcGPRRegClass = {
6977 extern const TargetRegisterClass DPRRegClass = {
6989 extern const TargetRegisterClass DPR_VFP2RegClass = {
7001 extern const TargetRegisterClass DPR_8RegClass = {
7013 extern const TargetRegisterClass GPRPairRegClass = {
7025 extern const TargetRegisterClass GPRPairnospRegClass = {
7037 extern const TargetRegisterClass GPRPair_with_gsub_0_in_tGPRRegClass = {
7049 extern const TargetRegisterClass GPRPair_with_gsub_0_in_hGPRRegClass = {
7061 extern const TargetRegisterClass GPRPair_with_gsub_0_in_tcGPRRegClass = {
7073 extern const TargetRegisterClass GPRPair_with_gsub_1_in_tcGPRRegClass = {
7085 extern const TargetRegisterClass GPRPairnosp_and_GPRPair_with_gsub_0_in_hGPRRegClass = {
7097 extern const TargetRegisterClass GPRPair_with_gsub_1_in_GPRspRegClass = {
7109 extern const TargetRegisterClass DPairSpcRegClass = {
7121 extern const TargetRegisterClass DPairSpc_with_ssub_0RegClass = {
7133 extern const TargetRegisterClass DPairSpc_with_ssub_4RegClass = {
7145 extern const TargetRegisterClass DPairSpc_with_dsub_0_in_DPR_8RegClass = {
7157 extern const TargetRegisterClass DPairSpc_with_dsub_2_in_DPR_8RegClass = {
7169 extern const TargetRegisterClass DPairRegClass = {
7181 extern const TargetRegisterClass DPair_with_ssub_0RegClass = {
7193 extern const TargetRegisterClass QPRRegClass = {
7205 extern const TargetRegisterClass DPair_with_ssub_2RegClass = {
7217 extern const TargetRegisterClass DPair_with_dsub_0_in_DPR_8RegClass = {
7229 extern const TargetRegisterClass MQPRRegClass = {
7241 extern const TargetRegisterClass QPR_VFP2RegClass = {
7253 extern const TargetRegisterClass DPair_with_dsub_1_in_DPR_8RegClass = {
7265 extern const TargetRegisterClass QPR_8RegClass = {
7277 extern const TargetRegisterClass DTripleRegClass = {
7289 extern const TargetRegisterClass DTripleSpcRegClass = {
7301 extern const TargetRegisterClass DTripleSpc_with_ssub_0RegClass = {
7313 extern const TargetRegisterClass DTriple_with_ssub_0RegClass = {
7325 extern const TargetRegisterClass DTriple_with_qsub_0_in_QPRRegClass = {
7337 extern const TargetRegisterClass DTriple_with_ssub_2RegClass = {
7349 extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
7361 extern const TargetRegisterClass DTripleSpc_with_ssub_4RegClass = {
7373 extern const TargetRegisterClass DTriple_with_ssub_4RegClass = {
7385 extern const TargetRegisterClass DTripleSpc_with_ssub_8RegClass = {
7397 extern const TargetRegisterClass DTripleSpc_with_dsub_0_in_DPR_8RegClass = {
7409 extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8RegClass = {
7421 extern const TargetRegisterClass DTriple_with_qsub_0_in_MQPRRegClass = {
7433 extern const TargetRegisterClass DTriple_with_ssub_0_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
7445 extern const TargetRegisterClass DTriple_with_dsub_1_in_DPR_8RegClass = {
7457 extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = {
7469 extern const TargetRegisterClass DTriple_with_ssub_4_and_DTriple_with_qsub_0_in_MQPRRegClass = {
7481 extern const TargetRegisterClass DTripleSpc_with_dsub_2_in_DPR_8RegClass = {
7493 extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8RegClass = {
7505 extern const TargetRegisterClass DTripleSpc_with_dsub_4_in_DPR_8RegClass = {
7517 extern const TargetRegisterClass DTriple_with_dsub_0_in_DPR_8_and_DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = {
7529 extern const TargetRegisterClass DTriple_with_qsub_0_in_QPR_8RegClass = {
7541 extern const TargetRegisterClass DTriple_with_dsub_2_in_DPR_8_and_DTriple_with_qsub_0_in_MQPRRegClass = {
7553 extern const TargetRegisterClass DTriple_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass = {
7565 extern const TargetRegisterClass DQuadSpcRegClass = {
7577 extern const TargetRegisterClass DQuadSpc_with_ssub_0RegClass = {
7589 extern const TargetRegisterClass DQuadSpc_with_ssub_4RegClass = {
7601 extern const TargetRegisterClass DQuadSpc_with_ssub_8RegClass = {
7613 extern const TargetRegisterClass DQuadSpc_with_dsub_0_in_DPR_8RegClass = {
7625 extern const TargetRegisterClass DQuadSpc_with_dsub_2_in_DPR_8RegClass = {
7637 extern const TargetRegisterClass DQuadSpc_with_dsub_4_in_DPR_8RegClass = {
7649 extern const TargetRegisterClass DQuadRegClass = {
7661 extern const TargetRegisterClass DQuad_with_ssub_0RegClass = {
7673 extern const TargetRegisterClass DQuad_with_ssub_2RegClass = {
7685 extern const TargetRegisterClass QQPRRegClass = {
7697 extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
7709 extern const TargetRegisterClass DQuad_with_ssub_4RegClass = {
7721 extern const TargetRegisterClass DQuad_with_ssub_6RegClass = {
7733 extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8RegClass = {
7745 extern const TargetRegisterClass DQuad_with_qsub_0_in_MQPRRegClass = {
7757 extern const TargetRegisterClass DQuad_with_ssub_0_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPRRegClass = {
7769 extern const TargetRegisterClass DQuad_with_dsub_1_in_DPR_8RegClass = {
7781 extern const TargetRegisterClass DQuad_with_qsub_1_in_MQPRRegClass = {
7793 extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = {
7805 extern const TargetRegisterClass DQuad_with_dsub_2_in_DPR_8RegClass = {
7817 extern const TargetRegisterClass DQuad_with_ssub_6_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = {
7829 extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8RegClass = {
7841 extern const TargetRegisterClass DQuad_with_dsub_0_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = {
7853 extern const TargetRegisterClass DQuad_with_qsub_0_in_QPR_8RegClass = {
7865 extern const TargetRegisterClass DQuad_with_qsub_1_in_QPR_8RegClass = {
7877 extern const TargetRegisterClass DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_QPR_8RegClass = {
7889 extern const TargetRegisterClass DQuad_with_dsub_3_in_DPR_8_and_DQuad_with_ssub_2_ssub_3_ssub_4_ssub_5_in_MQPRRegClass = {
7901 extern const TargetRegisterClass QQQQPRRegClass = {
7913 extern const TargetRegisterClass QQQQPR_with_ssub_0RegClass = {
7925 extern const TargetRegisterClass QQQQPR_with_ssub_4RegClass = {
7937 extern const TargetRegisterClass QQQQPR_with_ssub_8RegClass = {
7949 extern const TargetRegisterClass QQQQPR_with_ssub_12RegClass = {
7961 extern const TargetRegisterClass QQQQPR_with_dsub_0_in_DPR_8RegClass = {
7973 extern const TargetRegisterClass QQQQPR_with_dsub_2_in_DPR_8RegClass = {
7985 extern const TargetRegisterClass QQQQPR_with_dsub_4_in_DPR_8RegClass = {
7997 extern const TargetRegisterClass QQQQPR_with_dsub_6_in_DPR_8RegClass = {
8012 const TargetRegisterClass* const RegisterClasses[] = {
8565 const TargetRegisterClass *ARMGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
8565 const TargetRegisterClass *ARMGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
15654 getRegClassWeight(const TargetRegisterClass *RC) const {
15916 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/AVR/AVRGenRegisterInfo.inc 860 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
860 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
861 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
866 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
876 extern const TargetRegisterClass GPR8RegClass;
877 extern const TargetRegisterClass GPR8loRegClass;
878 extern const TargetRegisterClass LD8RegClass;
879 extern const TargetRegisterClass LD8loRegClass;
880 extern const TargetRegisterClass CCRRegClass;
881 extern const TargetRegisterClass DREGSRegClass;
882 extern const TargetRegisterClass DREGS_WITHOUT_YZ_WORKAROUNDRegClass;
883 extern const TargetRegisterClass DLDREGSRegClass;
884 extern const TargetRegisterClass DREGS_with_sub_hi_in_GPR8loRegClass;
885 extern const TargetRegisterClass DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDRegClass;
886 extern const TargetRegisterClass DLDREGS_with_sub_hi_in_LD8loRegClass;
887 extern const TargetRegisterClass IWREGSRegClass;
888 extern const TargetRegisterClass PTRREGSRegClass;
889 extern const TargetRegisterClass DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSRegClass;
890 extern const TargetRegisterClass PTRDISPREGSRegClass;
891 extern const TargetRegisterClass DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGSRegClass;
892 extern const TargetRegisterClass GPRSPRegClass;
893 extern const TargetRegisterClass ZREGRegClass;
954 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
1040 static const TargetRegisterClass *const GPR8loSuperclasses[] = {
1045 static const TargetRegisterClass *const LD8Superclasses[] = {
1050 static const TargetRegisterClass *const LD8loSuperclasses[] = {
1056 static const TargetRegisterClass *const DREGS_WITHOUT_YZ_WORKAROUNDSuperclasses[] = {
1061 static const TargetRegisterClass *const DLDREGSSuperclasses[] = {
1066 static const TargetRegisterClass *const DREGS_with_sub_hi_in_GPR8loSuperclasses[] = {
1072 static const TargetRegisterClass *const DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDSuperclasses[] = {
1079 static const TargetRegisterClass *const DLDREGS_with_sub_hi_in_LD8loSuperclasses[] = {
1087 static const TargetRegisterClass *const IWREGSSuperclasses[] = {
1093 static const TargetRegisterClass *const PTRREGSSuperclasses[] = {
1100 static const TargetRegisterClass *const DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSSuperclasses[] = {
1109 static const TargetRegisterClass *const PTRDISPREGSSuperclasses[] = {
1117 static const TargetRegisterClass *const DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGSSuperclasses[] = {
1128 static const TargetRegisterClass *const ZREGSuperclasses[] = {
1139 extern const TargetRegisterClass GPR8RegClass = {
1151 extern const TargetRegisterClass GPR8loRegClass = {
1163 extern const TargetRegisterClass LD8RegClass = {
1175 extern const TargetRegisterClass LD8loRegClass = {
1187 extern const TargetRegisterClass CCRRegClass = {
1199 extern const TargetRegisterClass DREGSRegClass = {
1211 extern const TargetRegisterClass DREGS_WITHOUT_YZ_WORKAROUNDRegClass = {
1223 extern const TargetRegisterClass DLDREGSRegClass = {
1235 extern const TargetRegisterClass DREGS_with_sub_hi_in_GPR8loRegClass = {
1247 extern const TargetRegisterClass DLDREGS_and_DREGS_WITHOUT_YZ_WORKAROUNDRegClass = {
1259 extern const TargetRegisterClass DLDREGS_with_sub_hi_in_LD8loRegClass = {
1271 extern const TargetRegisterClass IWREGSRegClass = {
1283 extern const TargetRegisterClass PTRREGSRegClass = {
1295 extern const TargetRegisterClass DREGS_WITHOUT_YZ_WORKAROUND_and_IWREGSRegClass = {
1307 extern const TargetRegisterClass PTRDISPREGSRegClass = {
1319 extern const TargetRegisterClass DREGS_WITHOUT_YZ_WORKAROUND_and_PTRREGSRegClass = {
1331 extern const TargetRegisterClass GPRSPRegClass = {
1343 extern const TargetRegisterClass ZREGRegClass = {
1358 const TargetRegisterClass* const RegisterClasses[] = {
1485 const TargetRegisterClass *AVRGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
1485 const TargetRegisterClass *AVRGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
1570 getRegClassWeight(const TargetRegisterClass *RC) const {
1658 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/BPF/BPFGenRegisterInfo.inc 390 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
390 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
391 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
396 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
406 extern const TargetRegisterClass GPR32RegClass;
407 extern const TargetRegisterClass GPRRegClass;
451 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
468 extern const TargetRegisterClass GPR32RegClass = {
480 extern const TargetRegisterClass GPRRegClass = {
495 const TargetRegisterClass* const RegisterClasses[] = {
576 const TargetRegisterClass *BPFGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
576 const TargetRegisterClass *BPFGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
595 getRegClassWeight(const TargetRegisterClass *RC) const {
644 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/Hexagon/HexagonGenRegisterInfo.inc 2275 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
2275 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
2276 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
2281 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
2291 extern const TargetRegisterClass UsrBitsRegClass;
2292 extern const TargetRegisterClass GuestRegsRegClass;
2293 extern const TargetRegisterClass IntRegsRegClass;
2294 extern const TargetRegisterClass CtrRegsRegClass;
2295 extern const TargetRegisterClass GeneralSubRegsRegClass;
2296 extern const TargetRegisterClass V62RegsRegClass;
2297 extern const TargetRegisterClass IntRegsLow8RegClass;
2298 extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass;
2299 extern const TargetRegisterClass PredRegsRegClass;
2300 extern const TargetRegisterClass V62Regs_with_isub_hiRegClass;
2301 extern const TargetRegisterClass ModRegsRegClass;
2302 extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass;
2303 extern const TargetRegisterClass V65RegsRegClass;
2304 extern const TargetRegisterClass DoubleRegsRegClass;
2305 extern const TargetRegisterClass GuestRegs64RegClass;
2306 extern const TargetRegisterClass CtrRegs64RegClass;
2307 extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass;
2308 extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass;
2309 extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass;
2310 extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass;
2311 extern const TargetRegisterClass HvxVRRegClass;
2312 extern const TargetRegisterClass HvxQRRegClass;
2313 extern const TargetRegisterClass HvxVR_and_V65RegsRegClass;
2314 extern const TargetRegisterClass HvxWRRegClass;
2315 extern const TargetRegisterClass HvxVQRRegClass;
2451 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
2583 static const TargetRegisterClass *const GeneralSubRegsSuperclasses[] = {
2588 static const TargetRegisterClass *const IntRegsLow8Superclasses[] = {
2594 static const TargetRegisterClass *const CtrRegs_and_V62RegsSuperclasses[] = {
2600 static const TargetRegisterClass *const V62Regs_with_isub_hiSuperclasses[] = {
2605 static const TargetRegisterClass *const ModRegsSuperclasses[] = {
2610 static const TargetRegisterClass *const CtrRegs_with_subreg_overflowSuperclasses[] = {
2615 static const TargetRegisterClass *const GeneralDoubleLow8RegsSuperclasses[] = {
2620 static const TargetRegisterClass *const DoubleRegs_with_isub_hi_in_IntRegsLow8Superclasses[] = {
2626 static const TargetRegisterClass *const CtrRegs64_and_V62RegsSuperclasses[] = {
2633 static const TargetRegisterClass *const CtrRegs64_with_isub_hi_in_ModRegsSuperclasses[] = {
2638 static const TargetRegisterClass *const HvxVR_and_V65RegsSuperclasses[] = {
2646 extern const TargetRegisterClass UsrBitsRegClass = {
2658 extern const TargetRegisterClass GuestRegsRegClass = {
2670 extern const TargetRegisterClass IntRegsRegClass = {
2682 extern const TargetRegisterClass CtrRegsRegClass = {
2694 extern const TargetRegisterClass GeneralSubRegsRegClass = {
2706 extern const TargetRegisterClass V62RegsRegClass = {
2718 extern const TargetRegisterClass IntRegsLow8RegClass = {
2730 extern const TargetRegisterClass CtrRegs_and_V62RegsRegClass = {
2742 extern const TargetRegisterClass PredRegsRegClass = {
2754 extern const TargetRegisterClass V62Regs_with_isub_hiRegClass = {
2766 extern const TargetRegisterClass ModRegsRegClass = {
2778 extern const TargetRegisterClass CtrRegs_with_subreg_overflowRegClass = {
2790 extern const TargetRegisterClass V65RegsRegClass = {
2802 extern const TargetRegisterClass DoubleRegsRegClass = {
2814 extern const TargetRegisterClass GuestRegs64RegClass = {
2826 extern const TargetRegisterClass CtrRegs64RegClass = {
2838 extern const TargetRegisterClass GeneralDoubleLow8RegsRegClass = {
2850 extern const TargetRegisterClass DoubleRegs_with_isub_hi_in_IntRegsLow8RegClass = {
2862 extern const TargetRegisterClass CtrRegs64_and_V62RegsRegClass = {
2874 extern const TargetRegisterClass CtrRegs64_with_isub_hi_in_ModRegsRegClass = {
2886 extern const TargetRegisterClass HvxVRRegClass = {
2898 extern const TargetRegisterClass HvxQRRegClass = {
2910 extern const TargetRegisterClass HvxVR_and_V65RegsRegClass = {
2922 extern const TargetRegisterClass HvxWRRegClass = {
2934 extern const TargetRegisterClass HvxVQRRegClass = {
2949 const TargetRegisterClass* const RegisterClasses[] = {
3243 const TargetRegisterClass *HexagonGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
3243 const TargetRegisterClass *HexagonGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
3531 getRegClassWeight(const TargetRegisterClass *RC) const {
3621 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/Lanai/LanaiGenRegisterInfo.inc 571 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
571 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
572 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
577 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
587 extern const TargetRegisterClass GPRRegClass;
588 extern const TargetRegisterClass GPR_with_sub_32RegClass;
589 extern const TargetRegisterClass CCRRegClass;
633 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
652 static const TargetRegisterClass *const GPR_with_sub_32Superclasses[] = {
659 extern const TargetRegisterClass GPRRegClass = {
671 extern const TargetRegisterClass GPR_with_sub_32RegClass = {
683 extern const TargetRegisterClass CCRRegClass = {
698 const TargetRegisterClass* const RegisterClasses[] = {
796 const TargetRegisterClass *LanaiGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
796 const TargetRegisterClass *LanaiGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
818 getRegClassWeight(const TargetRegisterClass *RC) const {
870 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/MSP430/MSP430GenRegisterInfo.inc 315 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
315 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
316 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
321 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
331 extern const TargetRegisterClass GR8RegClass;
332 extern const TargetRegisterClass GR16RegClass;
376 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
393 extern const TargetRegisterClass GR8RegClass = {
405 extern const TargetRegisterClass GR16RegClass = {
420 const TargetRegisterClass* const RegisterClasses[] = {
509 const TargetRegisterClass *MSP430GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
509 const TargetRegisterClass *MSP430GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
528 getRegClassWeight(const TargetRegisterClass *RC) const {
577 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/Mips/MipsGenRegisterInfo.inc 3813 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
3813 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
3814 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3819 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
3829 extern const TargetRegisterClass MSA128F16RegClass;
3830 extern const TargetRegisterClass CCRRegClass;
3831 extern const TargetRegisterClass COP0RegClass;
3832 extern const TargetRegisterClass COP2RegClass;
3833 extern const TargetRegisterClass COP3RegClass;
3834 extern const TargetRegisterClass DSPRRegClass;
3835 extern const TargetRegisterClass FGR32RegClass;
3836 extern const TargetRegisterClass FGRCCRegClass;
3837 extern const TargetRegisterClass GPR32RegClass;
3838 extern const TargetRegisterClass HWRegsRegClass;
3839 extern const TargetRegisterClass MSACtrlRegClass;
3840 extern const TargetRegisterClass GPR32NONZERORegClass;
3841 extern const TargetRegisterClass CPU16RegsPlusSPRegClass;
3842 extern const TargetRegisterClass CPU16RegsRegClass;
3843 extern const TargetRegisterClass FCCRegClass;
3844 extern const TargetRegisterClass GPRMM16RegClass;
3845 extern const TargetRegisterClass GPRMM16MovePRegClass;
3846 extern const TargetRegisterClass GPRMM16ZeroRegClass;
3847 extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass;
3848 extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass;
3849 extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass;
3850 extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass;
3851 extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass;
3852 extern const TargetRegisterClass HI32DSPRegClass;
3853 extern const TargetRegisterClass LO32DSPRegClass;
3854 extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass;
3855 extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass;
3856 extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
3857 extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;
3858 extern const TargetRegisterClass CPURARegRegClass;
3859 extern const TargetRegisterClass CPUSPRegRegClass;
3860 extern const TargetRegisterClass DSPCCRegClass;
3861 extern const TargetRegisterClass GP32RegClass;
3862 extern const TargetRegisterClass GPR32ZERORegClass;
3863 extern const TargetRegisterClass HI32RegClass;
3864 extern const TargetRegisterClass LO32RegClass;
3865 extern const TargetRegisterClass SP32RegClass;
3866 extern const TargetRegisterClass FGR64RegClass;
3867 extern const TargetRegisterClass GPR64RegClass;
3868 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass;
3869 extern const TargetRegisterClass AFGR64RegClass;
3870 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass;
3871 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass;
3872 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass;
3873 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass;
3874 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass;
3875 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass;
3876 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass;
3877 extern const TargetRegisterClass ACC64DSPRegClass;
3878 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass;
3879 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass;
3880 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass;
3881 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass;
3882 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass;
3883 extern const TargetRegisterClass OCTEON_MPLRegClass;
3884 extern const TargetRegisterClass OCTEON_PRegClass;
3885 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass;
3886 extern const TargetRegisterClass ACC64RegClass;
3887 extern const TargetRegisterClass GP64RegClass;
3888 extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass;
3889 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass;
3890 extern const TargetRegisterClass HI64RegClass;
3891 extern const TargetRegisterClass LO64RegClass;
3892 extern const TargetRegisterClass SP64RegClass;
3893 extern const TargetRegisterClass MSA128BRegClass;
3894 extern const TargetRegisterClass MSA128DRegClass;
3895 extern const TargetRegisterClass MSA128HRegClass;
3896 extern const TargetRegisterClass MSA128WRegClass;
3897 extern const TargetRegisterClass MSA128WEvensRegClass;
3898 extern const TargetRegisterClass ACC128RegClass;
4029 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
4362 static const TargetRegisterClass *const FGR32Superclasses[] = {
4367 static const TargetRegisterClass *const FGRCCSuperclasses[] = {
4372 static const TargetRegisterClass *const GPR32Superclasses[] = {
4377 static const TargetRegisterClass *const GPR32NONZEROSuperclasses[] = {
4383 static const TargetRegisterClass *const CPU16RegsPlusSPSuperclasses[] = {
4390 static const TargetRegisterClass *const CPU16RegsSuperclasses[] = {
4398 static const TargetRegisterClass *const GPRMM16Superclasses[] = {
4407 static const TargetRegisterClass *const GPRMM16MovePSuperclasses[] = {
4413 static const TargetRegisterClass *const GPRMM16ZeroSuperclasses[] = {
4419 static const TargetRegisterClass *const CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4430 static const TargetRegisterClass *const GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
4438 static const TargetRegisterClass *const GPRMM16MovePPairSecondSuperclasses[] = {
4445 static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
4457 static const TargetRegisterClass *const GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
4465 static const TargetRegisterClass *const CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
4478 static const TargetRegisterClass *const GPRMM16MovePPairFirstSuperclasses[] = {
4490 static const TargetRegisterClass *const GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4506 static const TargetRegisterClass *const GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
4521 static const TargetRegisterClass *const CPURARegSuperclasses[] = {
4528 static const TargetRegisterClass *const CPUSPRegSuperclasses[] = {
4536 static const TargetRegisterClass *const GP32Superclasses[] = {
4543 static const TargetRegisterClass *const GPR32ZEROSuperclasses[] = {
4552 static const TargetRegisterClass *const HI32Superclasses[] = {
4557 static const TargetRegisterClass *const LO32Superclasses[] = {
4562 static const TargetRegisterClass *const SP32Superclasses[] = {
4571 static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZEROSuperclasses[] = {
4576 static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsPlusSPSuperclasses[] = {
4582 static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16RegsSuperclasses[] = {
4589 static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePSuperclasses[] = {
4594 static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16ZeroSuperclasses[] = {
4599 static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4608 static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePSuperclasses[] = {
4615 static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairSecondSuperclasses[] = {
4621 static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePSuperclasses[] = {
4631 static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroSuperclasses[] = {
4638 static const TargetRegisterClass *const GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondSuperclasses[] = {
4649 static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirstSuperclasses[] = {
4659 static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroSuperclasses[] = {
4673 static const TargetRegisterClass *const GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondSuperclasses[] = {
4686 static const TargetRegisterClass *const ACC64Superclasses[] = {
4691 static const TargetRegisterClass *const GP64Superclasses[] = {
4697 static const TargetRegisterClass *const GPR64_with_sub_32_in_CPURARegSuperclasses[] = {
4703 static const TargetRegisterClass *const GPR64_with_sub_32_in_GPR32ZEROSuperclasses[] = {
4711 static const TargetRegisterClass *const SP64Superclasses[] = {
4718 static const TargetRegisterClass *const MSA128BSuperclasses[] = {
4726 static const TargetRegisterClass *const MSA128DSuperclasses[] = {
4734 static const TargetRegisterClass *const MSA128HSuperclasses[] = {
4742 static const TargetRegisterClass *const MSA128WSuperclasses[] = {
4750 static const TargetRegisterClass *const MSA128WEvensSuperclasses[] = {
4795 extern const TargetRegisterClass MSA128F16RegClass = {
4807 extern const TargetRegisterClass CCRRegClass = {
4819 extern const TargetRegisterClass COP0RegClass = {
4831 extern const TargetRegisterClass COP2RegClass = {
4843 extern const TargetRegisterClass COP3RegClass = {
4855 extern const TargetRegisterClass DSPRRegClass = {
4867 extern const TargetRegisterClass FGR32RegClass = {
4879 extern const TargetRegisterClass FGRCCRegClass = {
4891 extern const TargetRegisterClass GPR32RegClass = {
4903 extern const TargetRegisterClass HWRegsRegClass = {
4915 extern const TargetRegisterClass MSACtrlRegClass = {
4927 extern const TargetRegisterClass GPR32NONZERORegClass = {
4939 extern const TargetRegisterClass CPU16RegsPlusSPRegClass = {
4951 extern const TargetRegisterClass CPU16RegsRegClass = {
4963 extern const TargetRegisterClass FCCRegClass = {
4975 extern const TargetRegisterClass GPRMM16RegClass = {
4987 extern const TargetRegisterClass GPRMM16MovePRegClass = {
4999 extern const TargetRegisterClass GPRMM16ZeroRegClass = {
5011 extern const TargetRegisterClass CPU16Regs_and_GPRMM16ZeroRegClass = {
5023 extern const TargetRegisterClass GPR32NONZERO_and_GPRMM16MovePRegClass = {
5035 extern const TargetRegisterClass GPRMM16MovePPairSecondRegClass = {
5047 extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePRegClass = {
5059 extern const TargetRegisterClass GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
5071 extern const TargetRegisterClass HI32DSPRegClass = {
5083 extern const TargetRegisterClass LO32DSPRegClass = {
5095 extern const TargetRegisterClass CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
5107 extern const TargetRegisterClass GPRMM16MovePPairFirstRegClass = {
5119 extern const TargetRegisterClass GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
5131 extern const TargetRegisterClass GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
5143 extern const TargetRegisterClass CPURARegRegClass = {
5155 extern const TargetRegisterClass CPUSPRegRegClass = {
5167 extern const TargetRegisterClass DSPCCRegClass = {
5179 extern const TargetRegisterClass GP32RegClass = {
5191 extern const TargetRegisterClass GPR32ZERORegClass = {
5203 extern const TargetRegisterClass HI32RegClass = {
5215 extern const TargetRegisterClass LO32RegClass = {
5227 extern const TargetRegisterClass SP32RegClass = {
5239 extern const TargetRegisterClass FGR64RegClass = {
5251 extern const TargetRegisterClass GPR64RegClass = {
5263 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERORegClass = {
5275 extern const TargetRegisterClass AFGR64RegClass = {
5287 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsPlusSPRegClass = {
5299 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16RegsRegClass = {
5311 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePRegClass = {
5323 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16ZeroRegClass = {
5335 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16ZeroRegClass = {
5347 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32NONZERO_and_GPRMM16MovePRegClass = {
5359 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairSecondRegClass = {
5371 extern const TargetRegisterClass ACC64DSPRegClass = {
5383 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePRegClass = {
5395 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_GPRMM16ZeroRegClass = {
5407 extern const TargetRegisterClass GPR64_with_sub_32_in_CPU16Regs_and_GPRMM16MovePPairSecondRegClass = {
5419 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirstRegClass = {
5431 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MoveP_and_CPU16Regs_and_GPRMM16ZeroRegClass = {
5443 extern const TargetRegisterClass OCTEON_MPLRegClass = {
5455 extern const TargetRegisterClass OCTEON_PRegClass = {
5467 extern const TargetRegisterClass GPR64_with_sub_32_in_GPRMM16MovePPairFirst_and_GPRMM16MovePPairSecondRegClass = {
5479 extern const TargetRegisterClass ACC64RegClass = {
5491 extern const TargetRegisterClass GP64RegClass = {
5503 extern const TargetRegisterClass GPR64_with_sub_32_in_CPURARegRegClass = {
5515 extern const TargetRegisterClass GPR64_with_sub_32_in_GPR32ZERORegClass = {
5527 extern const TargetRegisterClass HI64RegClass = {
5539 extern const TargetRegisterClass LO64RegClass = {
5551 extern const TargetRegisterClass SP64RegClass = {
5563 extern const TargetRegisterClass MSA128BRegClass = {
5575 extern const TargetRegisterClass MSA128DRegClass = {
5587 extern const TargetRegisterClass MSA128HRegClass = {
5599 extern const TargetRegisterClass MSA128WRegClass = {
5611 extern const TargetRegisterClass MSA128WEvensRegClass = {
5623 extern const TargetRegisterClass ACC128RegClass = {
5638 const TargetRegisterClass* const RegisterClasses[] = {
6224 const TargetRegisterClass *MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
6224 const TargetRegisterClass *MipsGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
7147 getRegClassWeight(const TargetRegisterClass *RC) const {
7313 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc 759 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
764 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
774 extern const TargetRegisterClass Int1RegsRegClass;
775 extern const TargetRegisterClass Float16RegsRegClass;
776 extern const TargetRegisterClass Int16RegsRegClass;
777 extern const TargetRegisterClass SpecialRegsRegClass;
778 extern const TargetRegisterClass Float16x2RegsRegClass;
779 extern const TargetRegisterClass Float32ArgRegsRegClass;
780 extern const TargetRegisterClass Float32RegsRegClass;
781 extern const TargetRegisterClass Int32ArgRegsRegClass;
782 extern const TargetRegisterClass Int32RegsRegClass;
783 extern const TargetRegisterClass Float64ArgRegsRegClass;
784 extern const TargetRegisterClass Float64RegsRegClass;
785 extern const TargetRegisterClass Int64ArgRegsRegClass;
786 extern const TargetRegisterClass Int64RegsRegClass;
846 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
906 extern const TargetRegisterClass Int1RegsRegClass = {
918 extern const TargetRegisterClass Float16RegsRegClass = {
930 extern const TargetRegisterClass Int16RegsRegClass = {
942 extern const TargetRegisterClass SpecialRegsRegClass = {
954 extern const TargetRegisterClass Float16x2RegsRegClass = {
966 extern const TargetRegisterClass Float32ArgRegsRegClass = {
978 extern const TargetRegisterClass Float32RegsRegClass = {
990 extern const TargetRegisterClass Int32ArgRegsRegClass = {
1002 extern const TargetRegisterClass Int32RegsRegClass = {
1014 extern const TargetRegisterClass Float64ArgRegsRegClass = {
1026 extern const TargetRegisterClass Float64RegsRegClass = {
1038 extern const TargetRegisterClass Int64ArgRegsRegClass = {
1050 extern const TargetRegisterClass Int64RegsRegClass = {
1065 const TargetRegisterClass* const RegisterClasses[] = {
1182 getRegClassWeight(const TargetRegisterClass *RC) const {
1278 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/PowerPC/PPCGenRegisterInfo.inc 3847 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
3847 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
3848 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
3853 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
3863 extern const TargetRegisterClass VSSRCRegClass;
3864 extern const TargetRegisterClass GPRCRegClass;
3865 extern const TargetRegisterClass GPRC_NOR0RegClass;
3866 extern const TargetRegisterClass GPRC_and_GPRC_NOR0RegClass;
3867 extern const TargetRegisterClass CRBITRCRegClass;
3868 extern const TargetRegisterClass F4RCRegClass;
3869 extern const TargetRegisterClass CRRCRegClass;
3870 extern const TargetRegisterClass CARRYRCRegClass;
3871 extern const TargetRegisterClass CTRRCRegClass;
3872 extern const TargetRegisterClass VRSAVERCRegClass;
3873 extern const TargetRegisterClass SPILLTOVSRRCRegClass;
3874 extern const TargetRegisterClass VSFRCRegClass;
3875 extern const TargetRegisterClass G8RCRegClass;
3876 extern const TargetRegisterClass G8RC_NOX0RegClass;
3877 extern const TargetRegisterClass SPILLTOVSRRC_and_VSFRCRegClass;
3878 extern const TargetRegisterClass G8RC_and_G8RC_NOX0RegClass;
3879 extern const TargetRegisterClass F8RCRegClass;
3880 extern const TargetRegisterClass SPERCRegClass;
3881 extern const TargetRegisterClass VFRCRegClass;
3882 extern const TargetRegisterClass SPERC_with_sub_32_in_GPRC_NOR0RegClass;
3883 extern const TargetRegisterClass SPILLTOVSRRC_and_VFRCRegClass;
3884 extern const TargetRegisterClass SPILLTOVSRRC_and_F4RCRegClass;
3885 extern const TargetRegisterClass CTRRC8RegClass;
3886 extern const TargetRegisterClass VSRCRegClass;
3887 extern const TargetRegisterClass VSRC_with_sub_64_in_SPILLTOVSRRCRegClass;
3888 extern const TargetRegisterClass QSRCRegClass;
3889 extern const TargetRegisterClass VRRCRegClass;
3890 extern const TargetRegisterClass VSLRCRegClass;
3891 extern const TargetRegisterClass VRRC_with_sub_64_in_SPILLTOVSRRCRegClass;
3892 extern const TargetRegisterClass QSRC_with_sub_64_in_SPILLTOVSRRCRegClass;
3893 extern const TargetRegisterClass VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass;
3894 extern const TargetRegisterClass QBRCRegClass;
3895 extern const TargetRegisterClass QFRCRegClass;
3896 extern const TargetRegisterClass QBRC_with_sub_64_in_SPILLTOVSRRCRegClass;
3985 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
4145 static const TargetRegisterClass *const GPRC_and_GPRC_NOR0Superclasses[] = {
4151 static const TargetRegisterClass *const F4RCSuperclasses[] = {
4156 static const TargetRegisterClass *const VSFRCSuperclasses[] = {
4161 static const TargetRegisterClass *const G8RCSuperclasses[] = {
4166 static const TargetRegisterClass *const SPILLTOVSRRC_and_VSFRCSuperclasses[] = {
4173 static const TargetRegisterClass *const G8RC_and_G8RC_NOX0Superclasses[] = {
4180 static const TargetRegisterClass *const F8RCSuperclasses[] = {
4187 static const TargetRegisterClass *const VFRCSuperclasses[] = {
4193 static const TargetRegisterClass *const SPERC_with_sub_32_in_GPRC_NOR0Superclasses[] = {
4198 static const TargetRegisterClass *const SPILLTOVSRRC_and_VFRCSuperclasses[] = {
4207 static const TargetRegisterClass *const SPILLTOVSRRC_and_F4RCSuperclasses[] = {
4217 static const TargetRegisterClass *const VSRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
4222 static const TargetRegisterClass *const VRRCSuperclasses[] = {
4227 static const TargetRegisterClass *const VSLRCSuperclasses[] = {
4232 static const TargetRegisterClass *const VRRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
4239 static const TargetRegisterClass *const QSRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
4244 static const TargetRegisterClass *const VSLRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
4251 static const TargetRegisterClass *const QBRCSuperclasses[] = {
4257 static const TargetRegisterClass *const QFRCSuperclasses[] = {
4263 static const TargetRegisterClass *const QBRC_with_sub_64_in_SPILLTOVSRRCSuperclasses[] = {
4369 extern const TargetRegisterClass VSSRCRegClass = {
4381 extern const TargetRegisterClass GPRCRegClass = {
4393 extern const TargetRegisterClass GPRC_NOR0RegClass = {
4405 extern const TargetRegisterClass GPRC_and_GPRC_NOR0RegClass = {
4417 extern const TargetRegisterClass CRBITRCRegClass = {
4429 extern const TargetRegisterClass F4RCRegClass = {
4441 extern const TargetRegisterClass CRRCRegClass = {
4453 extern const TargetRegisterClass CARRYRCRegClass = {
4465 extern const TargetRegisterClass CTRRCRegClass = {
4477 extern const TargetRegisterClass VRSAVERCRegClass = {
4489 extern const TargetRegisterClass SPILLTOVSRRCRegClass = {
4501 extern const TargetRegisterClass VSFRCRegClass = {
4513 extern const TargetRegisterClass G8RCRegClass = {
4525 extern const TargetRegisterClass G8RC_NOX0RegClass = {
4537 extern const TargetRegisterClass SPILLTOVSRRC_and_VSFRCRegClass = {
4549 extern const TargetRegisterClass G8RC_and_G8RC_NOX0RegClass = {
4561 extern const TargetRegisterClass F8RCRegClass = {
4573 extern const TargetRegisterClass SPERCRegClass = {
4585 extern const TargetRegisterClass VFRCRegClass = {
4597 extern const TargetRegisterClass SPERC_with_sub_32_in_GPRC_NOR0RegClass = {
4609 extern const TargetRegisterClass SPILLTOVSRRC_and_VFRCRegClass = {
4621 extern const TargetRegisterClass SPILLTOVSRRC_and_F4RCRegClass = {
4633 extern const TargetRegisterClass CTRRC8RegClass = {
4645 extern const TargetRegisterClass VSRCRegClass = {
4657 extern const TargetRegisterClass VSRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
4669 extern const TargetRegisterClass QSRCRegClass = {
4681 extern const TargetRegisterClass VRRCRegClass = {
4693 extern const TargetRegisterClass VSLRCRegClass = {
4705 extern const TargetRegisterClass VRRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
4717 extern const TargetRegisterClass QSRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
4729 extern const TargetRegisterClass VSLRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
4741 extern const TargetRegisterClass QBRCRegClass = {
4753 extern const TargetRegisterClass QFRCRegClass = {
4765 extern const TargetRegisterClass QBRC_with_sub_64_in_SPILLTOVSRRCRegClass = {
4780 const TargetRegisterClass* const RegisterClasses[] = {
5222 const TargetRegisterClass *PPCGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
5222 const TargetRegisterClass *PPCGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
5507 getRegClassWeight(const TargetRegisterClass *RC) const {
5627 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/RISCV/RISCVGenRegisterInfo.inc 1118 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
1118 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
1119 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
1124 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
1134 extern const TargetRegisterClass FPR32RegClass;
1135 extern const TargetRegisterClass GPRRegClass;
1136 extern const TargetRegisterClass GPRNoX0RegClass;
1137 extern const TargetRegisterClass GPRNoX0X2RegClass;
1138 extern const TargetRegisterClass GPRTCRegClass;
1139 extern const TargetRegisterClass FPR32CRegClass;
1140 extern const TargetRegisterClass GPRCRegClass;
1141 extern const TargetRegisterClass GPRC_and_GPRTCRegClass;
1142 extern const TargetRegisterClass GPRX0RegClass;
1143 extern const TargetRegisterClass SPRegClass;
1144 extern const TargetRegisterClass FPR64RegClass;
1145 extern const TargetRegisterClass FPR64CRegClass;
1227 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
1283 static const TargetRegisterClass *const GPRNoX0Superclasses[] = {
1288 static const TargetRegisterClass *const GPRNoX0X2Superclasses[] = {
1294 static const TargetRegisterClass *const GPRTCSuperclasses[] = {
1301 static const TargetRegisterClass *const FPR32CSuperclasses[] = {
1306 static const TargetRegisterClass *const GPRCSuperclasses[] = {
1313 static const TargetRegisterClass *const GPRC_and_GPRTCSuperclasses[] = {
1322 static const TargetRegisterClass *const GPRX0Superclasses[] = {
1327 static const TargetRegisterClass *const SPSuperclasses[] = {
1333 static const TargetRegisterClass *const FPR64CSuperclasses[] = {
1340 extern const TargetRegisterClass FPR32RegClass = {
1352 extern const TargetRegisterClass GPRRegClass = {
1364 extern const TargetRegisterClass GPRNoX0RegClass = {
1376 extern const TargetRegisterClass GPRNoX0X2RegClass = {
1388 extern const TargetRegisterClass GPRTCRegClass = {
1400 extern const TargetRegisterClass FPR32CRegClass = {
1412 extern const TargetRegisterClass GPRCRegClass = {
1424 extern const TargetRegisterClass GPRC_and_GPRTCRegClass = {
1436 extern const TargetRegisterClass GPRX0RegClass = {
1448 extern const TargetRegisterClass SPRegClass = {
1460 extern const TargetRegisterClass FPR64RegClass = {
1472 extern const TargetRegisterClass FPR64CRegClass = {
1487 const TargetRegisterClass* const RegisterClasses[] = {
1650 const TargetRegisterClass *RISCVGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
1650 const TargetRegisterClass *RISCVGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
1699 getRegClassWeight(const TargetRegisterClass *RC) const {
1773 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/Sparc/SparcGenRegisterInfo.inc 1891 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
1891 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
1892 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
1897 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
1907 extern const TargetRegisterClass FCCRegsRegClass;
1908 extern const TargetRegisterClass ASRRegsRegClass;
1909 extern const TargetRegisterClass CoprocRegsRegClass;
1910 extern const TargetRegisterClass FPRegsRegClass;
1911 extern const TargetRegisterClass IntRegsRegClass;
1912 extern const TargetRegisterClass DFPRegsRegClass;
1913 extern const TargetRegisterClass I64RegsRegClass;
1914 extern const TargetRegisterClass CoprocPairRegClass;
1915 extern const TargetRegisterClass IntPairRegClass;
1916 extern const TargetRegisterClass LowDFPRegsRegClass;
1917 extern const TargetRegisterClass PRRegsRegClass;
1918 extern const TargetRegisterClass QFPRegsRegClass;
1919 extern const TargetRegisterClass LowQFPRegsRegClass;
1984 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
2058 static const TargetRegisterClass *const I64RegsSuperclasses[] = {
2063 static const TargetRegisterClass *const LowDFPRegsSuperclasses[] = {
2068 static const TargetRegisterClass *const LowQFPRegsSuperclasses[] = {
2075 extern const TargetRegisterClass FCCRegsRegClass = {
2087 extern const TargetRegisterClass ASRRegsRegClass = {
2099 extern const TargetRegisterClass CoprocRegsRegClass = {
2111 extern const TargetRegisterClass FPRegsRegClass = {
2123 extern const TargetRegisterClass IntRegsRegClass = {
2135 extern const TargetRegisterClass DFPRegsRegClass = {
2147 extern const TargetRegisterClass I64RegsRegClass = {
2159 extern const TargetRegisterClass CoprocPairRegClass = {
2171 extern const TargetRegisterClass IntPairRegClass = {
2183 extern const TargetRegisterClass LowDFPRegsRegClass = {
2195 extern const TargetRegisterClass PRRegsRegClass = {
2207 extern const TargetRegisterClass QFPRegsRegClass = {
2219 extern const TargetRegisterClass LowQFPRegsRegClass = {
2234 const TargetRegisterClass* const RegisterClasses[] = {
2549 const TargetRegisterClass *SparcGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
2549 const TargetRegisterClass *SparcGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
2666 getRegClassWeight(const TargetRegisterClass *RC) const {
2738 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/SystemZ/SystemZGenRegisterInfo.inc 1785 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
1785 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
1786 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
1791 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
1801 extern const TargetRegisterClass GRX32BitRegClass;
1802 extern const TargetRegisterClass VR32BitRegClass;
1803 extern const TargetRegisterClass AR32BitRegClass;
1804 extern const TargetRegisterClass FP32BitRegClass;
1805 extern const TargetRegisterClass GR32BitRegClass;
1806 extern const TargetRegisterClass GRH32BitRegClass;
1807 extern const TargetRegisterClass ADDR32BitRegClass;
1808 extern const TargetRegisterClass CCRRegClass;
1809 extern const TargetRegisterClass FPCRegsRegClass;
1810 extern const TargetRegisterClass AnyRegBitRegClass;
1811 extern const TargetRegisterClass AnyRegBit_with_subreg_h32_in_FP32BitRegClass;
1812 extern const TargetRegisterClass VR64BitRegClass;
1813 extern const TargetRegisterClass AnyRegBit_with_subreg_h64RegClass;
1814 extern const TargetRegisterClass CR64BitRegClass;
1815 extern const TargetRegisterClass FP64BitRegClass;
1816 extern const TargetRegisterClass GR64BitRegClass;
1817 extern const TargetRegisterClass ADDR64BitRegClass;
1818 extern const TargetRegisterClass VR128BitRegClass;
1819 extern const TargetRegisterClass VF128BitRegClass;
1820 extern const TargetRegisterClass FP128BitRegClass;
1821 extern const TargetRegisterClass GR128BitRegClass;
1822 extern const TargetRegisterClass ADDR128BitRegClass;
1898 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
2020 static const TargetRegisterClass *const FP32BitSuperclasses[] = {
2025 static const TargetRegisterClass *const GR32BitSuperclasses[] = {
2030 static const TargetRegisterClass *const GRH32BitSuperclasses[] = {
2035 static const TargetRegisterClass *const ADDR32BitSuperclasses[] = {
2041 static const TargetRegisterClass *const AnyRegBit_with_subreg_h32_in_FP32BitSuperclasses[] = {
2046 static const TargetRegisterClass *const AnyRegBit_with_subreg_h64Superclasses[] = {
2052 static const TargetRegisterClass *const FP64BitSuperclasses[] = {
2059 static const TargetRegisterClass *const GR64BitSuperclasses[] = {
2064 static const TargetRegisterClass *const ADDR64BitSuperclasses[] = {
2070 static const TargetRegisterClass *const VF128BitSuperclasses[] = {
2078 static const TargetRegisterClass *const ADDR128BitSuperclasses[] = {
2085 extern const TargetRegisterClass GRX32BitRegClass = {
2097 extern const TargetRegisterClass VR32BitRegClass = {
2109 extern const TargetRegisterClass AR32BitRegClass = {
2121 extern const TargetRegisterClass FP32BitRegClass = {
2133 extern const TargetRegisterClass GR32BitRegClass = {
2145 extern const TargetRegisterClass GRH32BitRegClass = {
2157 extern const TargetRegisterClass ADDR32BitRegClass = {
2169 extern const TargetRegisterClass CCRRegClass = {
2181 extern const TargetRegisterClass FPCRegsRegClass = {
2193 extern const TargetRegisterClass AnyRegBitRegClass = {
2205 extern const TargetRegisterClass AnyRegBit_with_subreg_h32_in_FP32BitRegClass = {
2217 extern const TargetRegisterClass VR64BitRegClass = {
2229 extern const TargetRegisterClass AnyRegBit_with_subreg_h64RegClass = {
2241 extern const TargetRegisterClass CR64BitRegClass = {
2253 extern const TargetRegisterClass FP64BitRegClass = {
2265 extern const TargetRegisterClass GR64BitRegClass = {
2277 extern const TargetRegisterClass ADDR64BitRegClass = {
2289 extern const TargetRegisterClass VR128BitRegClass = {
2301 extern const TargetRegisterClass VF128BitRegClass = {
2313 extern const TargetRegisterClass FP128BitRegClass = {
2325 extern const TargetRegisterClass GR128BitRegClass = {
2337 extern const TargetRegisterClass ADDR128BitRegClass = {
2352 const TargetRegisterClass* const RegisterClasses[] = {
2636 const TargetRegisterClass *SystemZGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
2636 const TargetRegisterClass *SystemZGenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
2825 getRegClassWeight(const TargetRegisterClass *RC) const {
2904 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc 258 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
263 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
273 extern const TargetRegisterClass EXNREFRegClass;
274 extern const TargetRegisterClass I32RegClass;
275 extern const TargetRegisterClass F32RegClass;
276 extern const TargetRegisterClass I64RegClass;
277 extern const TargetRegisterClass F64RegClass;
278 extern const TargetRegisterClass V128RegClass;
329 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
361 extern const TargetRegisterClass EXNREFRegClass = {
373 extern const TargetRegisterClass I32RegClass = {
385 extern const TargetRegisterClass F32RegClass = {
397 extern const TargetRegisterClass I64RegClass = {
409 extern const TargetRegisterClass F64RegClass = {
421 extern const TargetRegisterClass V128RegClass = {
436 const TargetRegisterClass* const RegisterClasses[] = {
463 getRegClassWeight(const TargetRegisterClass *RC) const {
531 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/X86/X86GenRegisterInfo.inc 4315 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
4315 const TargetRegisterClass *getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const override;
4316 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
4321 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
4331 extern const TargetRegisterClass GR8RegClass;
4332 extern const TargetRegisterClass GRH8RegClass;
4333 extern const TargetRegisterClass GR8_NOREXRegClass;
4334 extern const TargetRegisterClass GR8_ABCD_HRegClass;
4335 extern const TargetRegisterClass GR8_ABCD_LRegClass;
4336 extern const TargetRegisterClass GRH16RegClass;
4337 extern const TargetRegisterClass GR16RegClass;
4338 extern const TargetRegisterClass GR16_NOREXRegClass;
4339 extern const TargetRegisterClass VK1RegClass;
4340 extern const TargetRegisterClass VK16RegClass;
4341 extern const TargetRegisterClass VK2RegClass;
4342 extern const TargetRegisterClass VK4RegClass;
4343 extern const TargetRegisterClass VK8RegClass;
4344 extern const TargetRegisterClass VK16WMRegClass;
4345 extern const TargetRegisterClass VK1WMRegClass;
4346 extern const TargetRegisterClass VK2WMRegClass;
4347 extern const TargetRegisterClass VK4WMRegClass;
4348 extern const TargetRegisterClass VK8WMRegClass;
4349 extern const TargetRegisterClass SEGMENT_REGRegClass;
4350 extern const TargetRegisterClass GR16_ABCDRegClass;
4351 extern const TargetRegisterClass FPCCRRegClass;
4352 extern const TargetRegisterClass VK16PAIRRegClass;
4353 extern const TargetRegisterClass VK1PAIRRegClass;
4354 extern const TargetRegisterClass VK2PAIRRegClass;
4355 extern const TargetRegisterClass VK4PAIRRegClass;
4356 extern const TargetRegisterClass VK8PAIRRegClass;
4357 extern const TargetRegisterClass VK16PAIR_with_sub_mask_0_in_VK16WMRegClass;
4358 extern const TargetRegisterClass FR32XRegClass;
4359 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass;
4360 extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass;
4361 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass;
4362 extern const TargetRegisterClass DEBUG_REGRegClass;
4363 extern const TargetRegisterClass FR32RegClass;
4364 extern const TargetRegisterClass GR32RegClass;
4365 extern const TargetRegisterClass GR32_NOSPRegClass;
4366 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass;
4367 extern const TargetRegisterClass GR32_NOREXRegClass;
4368 extern const TargetRegisterClass VK32RegClass;
4369 extern const TargetRegisterClass GR32_NOREX_NOSPRegClass;
4370 extern const TargetRegisterClass RFP32RegClass;
4371 extern const TargetRegisterClass VK32WMRegClass;
4372 extern const TargetRegisterClass GR32_ABCDRegClass;
4373 extern const TargetRegisterClass GR32_TCRegClass;
4374 extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass;
4375 extern const TargetRegisterClass GR32_ADRegClass;
4376 extern const TargetRegisterClass GR32_BPSPRegClass;
4377 extern const TargetRegisterClass GR32_BSIRegClass;
4378 extern const TargetRegisterClass GR32_CBRegClass;
4379 extern const TargetRegisterClass GR32_DCRegClass;
4380 extern const TargetRegisterClass GR32_DIBPRegClass;
4381 extern const TargetRegisterClass GR32_SIDIRegClass;
4382 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass;
4383 extern const TargetRegisterClass CCRRegClass;
4384 extern const TargetRegisterClass DFCCRRegClass;
4385 extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass;
4386 extern const TargetRegisterClass GR32_AD_and_GR32_DCRegClass;
4387 extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass;
4388 extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass;
4389 extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass;
4390 extern const TargetRegisterClass GR32_CB_and_GR32_DCRegClass;
4391 extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass;
4392 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass;
4393 extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass;
4394 extern const TargetRegisterClass RFP64RegClass;
4395 extern const TargetRegisterClass FR64XRegClass;
4396 extern const TargetRegisterClass GR64RegClass;
4397 extern const TargetRegisterClass CONTROL_REGRegClass;
4398 extern const TargetRegisterClass FR64RegClass;
4399 extern const TargetRegisterClass GR64_with_sub_8bitRegClass;
4400 extern const TargetRegisterClass GR64_NOSPRegClass;
4401 extern const TargetRegisterClass GR64_TCRegClass;
4402 extern const TargetRegisterClass GR64_NOREXRegClass;
4403 extern const TargetRegisterClass GR64_TCW64RegClass;
4404 extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass;
4405 extern const TargetRegisterClass GR64_NOSP_and_GR64_TCRegClass;
4406 extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass;
4407 extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass;
4408 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass;
4409 extern const TargetRegisterClass VK64RegClass;
4410 extern const TargetRegisterClass VR64RegClass;
4411 extern const TargetRegisterClass GR64_NOREX_NOSPRegClass;
4412 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass;
4413 extern const TargetRegisterClass GR64_NOSP_and_GR64_TCW64RegClass;
4414 extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass;
4415 extern const TargetRegisterClass VK64WMRegClass;
4416 extern const TargetRegisterClass GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass;
4417 extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass;
4418 extern const TargetRegisterClass GR64_NOREX_NOSP_and_GR64_TCRegClass;
4419 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass;
4420 extern const TargetRegisterClass GR64_ABCDRegClass;
4421 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass;
4422 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass;
4423 extern const TargetRegisterClass GR64_ADRegClass;
4424 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass;
4425 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass;
4426 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass;
4427 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass;
4428 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DCRegClass;
4429 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass;
4430 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass;
4431 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass;
4432 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass;
4433 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass;
4434 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass;
4435 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass;
4436 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass;
4437 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass;
4438 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass;
4439 extern const TargetRegisterClass RSTRegClass;
4440 extern const TargetRegisterClass RFP80RegClass;
4441 extern const TargetRegisterClass RFP80_7RegClass;
4442 extern const TargetRegisterClass VR128XRegClass;
4443 extern const TargetRegisterClass VR128RegClass;
4444 extern const TargetRegisterClass BNDRRegClass;
4445 extern const TargetRegisterClass VR256XRegClass;
4446 extern const TargetRegisterClass VR256RegClass;
4447 extern const TargetRegisterClass VR512RegClass;
4448 extern const TargetRegisterClass VR512_0_15RegClass;
4635 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
5189 static const TargetRegisterClass *const GR8_NOREXSuperclasses[] = {
5194 static const TargetRegisterClass *const GR8_ABCD_HSuperclasses[] = {
5200 static const TargetRegisterClass *const GR8_ABCD_LSuperclasses[] = {
5206 static const TargetRegisterClass *const GR16_NOREXSuperclasses[] = {
5211 static const TargetRegisterClass *const VK1Superclasses[] = {
5219 static const TargetRegisterClass *const VK16Superclasses[] = {
5227 static const TargetRegisterClass *const VK2Superclasses[] = {
5235 static const TargetRegisterClass *const VK4Superclasses[] = {
5243 static const TargetRegisterClass *const VK8Superclasses[] = {
5251 static const TargetRegisterClass *const VK16WMSuperclasses[] = {
5264 static const TargetRegisterClass *const VK1WMSuperclasses[] = {
5277 static const TargetRegisterClass *const VK2WMSuperclasses[] = {
5290 static const TargetRegisterClass *const VK4WMSuperclasses[] = {
5303 static const TargetRegisterClass *const VK8WMSuperclasses[] = {
5316 static const TargetRegisterClass *const GR16_ABCDSuperclasses[] = {
5322 static const TargetRegisterClass *const VK16PAIRSuperclasses[] = {
5330 static const TargetRegisterClass *const VK1PAIRSuperclasses[] = {
5338 static const TargetRegisterClass *const VK2PAIRSuperclasses[] = {
5346 static const TargetRegisterClass *const VK4PAIRSuperclasses[] = {
5354 static const TargetRegisterClass *const VK8PAIRSuperclasses[] = {
5362 static const TargetRegisterClass *const VK16PAIR_with_sub_mask_0_in_VK16WMSuperclasses[] = {
5371 static const TargetRegisterClass *const LOW32_ADDR_ACCESSSuperclasses[] = {
5376 static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bitSuperclasses[] = {
5381 static const TargetRegisterClass *const FR32Superclasses[] = {
5386 static const TargetRegisterClass *const GR32Superclasses[] = {
5393 static const TargetRegisterClass *const GR32_NOSPSuperclasses[] = {
5401 static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
5407 static const TargetRegisterClass *const GR32_NOREXSuperclasses[] = {
5416 static const TargetRegisterClass *const VK32Superclasses[] = {
5425 static const TargetRegisterClass *const GR32_NOREX_NOSPSuperclasses[] = {
5436 static const TargetRegisterClass *const VK32WMSuperclasses[] = {
5451 static const TargetRegisterClass *const GR32_ABCDSuperclasses[] = {
5463 static const TargetRegisterClass *const GR32_TCSuperclasses[] = {
5473 static const TargetRegisterClass *const GR32_ABCD_and_GR32_TCSuperclasses[] = {
5487 static const TargetRegisterClass *const GR32_ADSuperclasses[] = {
5502 static const TargetRegisterClass *const GR32_BPSPSuperclasses[] = {
5512 static const TargetRegisterClass *const GR32_BSISuperclasses[] = {
5524 static const TargetRegisterClass *const GR32_CBSuperclasses[] = {
5537 static const TargetRegisterClass *const GR32_DCSuperclasses[] = {
5552 static const TargetRegisterClass *const GR32_DIBPSuperclasses[] = {
5564 static const TargetRegisterClass *const GR32_SIDISuperclasses[] = {
5576 static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_32bitSuperclasses[] = {
5581 static const TargetRegisterClass *const GR32_ABCD_and_GR32_BSISuperclasses[] = {
5596 static const TargetRegisterClass *const GR32_AD_and_GR32_DCSuperclasses[] = {
5613 static const TargetRegisterClass *const GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
5627 static const TargetRegisterClass *const GR32_BPSP_and_GR32_TCSuperclasses[] = {
5639 static const TargetRegisterClass *const GR32_BSI_and_GR32_SIDISuperclasses[] = {
5653 static const TargetRegisterClass *const GR32_CB_and_GR32_DCSuperclasses[] = {
5670 static const TargetRegisterClass *const GR32_DIBP_and_GR32_SIDISuperclasses[] = {
5684 static const TargetRegisterClass *const LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitSuperclasses[] = {
5692 static const TargetRegisterClass *const LOW32_ADDR_ACCESS_with_sub_32bitSuperclasses[] = {
5699 static const TargetRegisterClass *const RFP64Superclasses[] = {
5704 static const TargetRegisterClass *const FR64XSuperclasses[] = {
5709 static const TargetRegisterClass *const FR64Superclasses[] = {
5716 static const TargetRegisterClass *const GR64_with_sub_8bitSuperclasses[] = {
5721 static const TargetRegisterClass *const GR64_NOSPSuperclasses[] = {
5727 static const TargetRegisterClass *const GR64_TCSuperclasses[] = {
5732 static const TargetRegisterClass *const GR64_NOREXSuperclasses[] = {
5737 static const TargetRegisterClass *const GR64_TCW64Superclasses[] = {
5742 static const TargetRegisterClass *const GR64_TC_with_sub_8bitSuperclasses[] = {
5749 static const TargetRegisterClass *const GR64_NOSP_and_GR64_TCSuperclasses[] = {
5758 static const TargetRegisterClass *const GR64_TCW64_with_sub_8bitSuperclasses[] = {
5765 static const TargetRegisterClass *const GR64_TC_and_GR64_TCW64Superclasses[] = {
5772 static const TargetRegisterClass *const GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
5779 static const TargetRegisterClass *const VK64Superclasses[] = {
5789 static const TargetRegisterClass *const GR64_NOREX_NOSPSuperclasses[] = {
5798 static const TargetRegisterClass *const GR64_NOREX_and_GR64_TCSuperclasses[] = {
5805 static const TargetRegisterClass *const GR64_NOSP_and_GR64_TCW64Superclasses[] = {
5814 static const TargetRegisterClass *const GR64_TCW64_and_GR64_TC_with_sub_8bitSuperclasses[] = {
5825 static const TargetRegisterClass *const VK64WMSuperclasses[] = {
5842 static const TargetRegisterClass *const GR64_TC_and_GR64_NOSP_and_GR64_TCW64Superclasses[] = {
5857 static const TargetRegisterClass *const GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXSuperclasses[] = {
5868 static const TargetRegisterClass *const GR64_NOREX_NOSP_and_GR64_TCSuperclasses[] = {
5883 static const TargetRegisterClass *const GR64_NOREX_and_GR64_TCW64Superclasses[] = {
5893 static const TargetRegisterClass *const GR64_ABCDSuperclasses[] = {
5903 static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_TCSuperclasses[] = {
5920 static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCSuperclasses[] = {
5945 static const TargetRegisterClass *const GR64_ADSuperclasses[] = {
5971 static const TargetRegisterClass *const GR64_and_LOW32_ADDR_ACCESS_RBPSuperclasses[] = {
5979 static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSPSuperclasses[] = {
5987 static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BSISuperclasses[] = {
5997 static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_CBSuperclasses[] = {
6008 static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DCSuperclasses[] = {
6034 static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DIBPSuperclasses[] = {
6044 static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_SIDISuperclasses[] = {
6060 static const TargetRegisterClass *const GR64_and_LOW32_ADDR_ACCESSSuperclasses[] = {
6076 static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSISuperclasses[] = {
6089 static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCSuperclasses[] = {
6117 static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPSuperclasses[] = {
6135 static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCSuperclasses[] = {
6154 static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDISuperclasses[] = {
6172 static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCSuperclasses[] = {
6200 static const TargetRegisterClass *const GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDISuperclasses[] = {
6218 static const TargetRegisterClass *const RFP80Superclasses[] = {
6224 static const TargetRegisterClass *const VR128XSuperclasses[] = {
6230 static const TargetRegisterClass *const VR128Superclasses[] = {
6239 static const TargetRegisterClass *const VR256Superclasses[] = {
6244 static const TargetRegisterClass *const VR512_0_15Superclasses[] = {
6283 extern const TargetRegisterClass GR8RegClass = {
6295 extern const TargetRegisterClass GRH8RegClass = {
6307 extern const TargetRegisterClass GR8_NOREXRegClass = {
6319 extern const TargetRegisterClass GR8_ABCD_HRegClass = {
6331 extern const TargetRegisterClass GR8_ABCD_LRegClass = {
6343 extern const TargetRegisterClass GRH16RegClass = {
6355 extern const TargetRegisterClass GR16RegClass = {
6367 extern const TargetRegisterClass GR16_NOREXRegClass = {
6379 extern const TargetRegisterClass VK1RegClass = {
6391 extern const TargetRegisterClass VK16RegClass = {
6403 extern const TargetRegisterClass VK2RegClass = {
6415 extern const TargetRegisterClass VK4RegClass = {
6427 extern const TargetRegisterClass VK8RegClass = {
6439 extern const TargetRegisterClass VK16WMRegClass = {
6451 extern const TargetRegisterClass VK1WMRegClass = {
6463 extern const TargetRegisterClass VK2WMRegClass = {
6475 extern const TargetRegisterClass VK4WMRegClass = {
6487 extern const TargetRegisterClass VK8WMRegClass = {
6499 extern const TargetRegisterClass SEGMENT_REGRegClass = {
6511 extern const TargetRegisterClass GR16_ABCDRegClass = {
6523 extern const TargetRegisterClass FPCCRRegClass = {
6535 extern const TargetRegisterClass VK16PAIRRegClass = {
6547 extern const TargetRegisterClass VK1PAIRRegClass = {
6559 extern const TargetRegisterClass VK2PAIRRegClass = {
6571 extern const TargetRegisterClass VK4PAIRRegClass = {
6583 extern const TargetRegisterClass VK8PAIRRegClass = {
6595 extern const TargetRegisterClass VK16PAIR_with_sub_mask_0_in_VK16WMRegClass = {
6607 extern const TargetRegisterClass FR32XRegClass = {
6619 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBPRegClass = {
6631 extern const TargetRegisterClass LOW32_ADDR_ACCESSRegClass = {
6643 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bitRegClass = {
6655 extern const TargetRegisterClass DEBUG_REGRegClass = {
6667 extern const TargetRegisterClass FR32RegClass = {
6679 extern const TargetRegisterClass GR32RegClass = {
6691 extern const TargetRegisterClass GR32_NOSPRegClass = {
6703 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREXRegClass = {
6715 extern const TargetRegisterClass GR32_NOREXRegClass = {
6727 extern const TargetRegisterClass VK32RegClass = {
6739 extern const TargetRegisterClass GR32_NOREX_NOSPRegClass = {
6751 extern const TargetRegisterClass RFP32RegClass = {
6763 extern const TargetRegisterClass VK32WMRegClass = {
6775 extern const TargetRegisterClass GR32_ABCDRegClass = {
6787 extern const TargetRegisterClass GR32_TCRegClass = {
6799 extern const TargetRegisterClass GR32_ABCD_and_GR32_TCRegClass = {
6811 extern const TargetRegisterClass GR32_ADRegClass = {
6823 extern const TargetRegisterClass GR32_BPSPRegClass = {
6835 extern const TargetRegisterClass GR32_BSIRegClass = {
6847 extern const TargetRegisterClass GR32_CBRegClass = {
6859 extern const TargetRegisterClass GR32_DCRegClass = {
6871 extern const TargetRegisterClass GR32_DIBPRegClass = {
6883 extern const TargetRegisterClass GR32_SIDIRegClass = {
6895 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_32bitRegClass = {
6907 extern const TargetRegisterClass CCRRegClass = {
6919 extern const TargetRegisterClass DFCCRRegClass = {
6931 extern const TargetRegisterClass GR32_ABCD_and_GR32_BSIRegClass = {
6943 extern const TargetRegisterClass GR32_AD_and_GR32_DCRegClass = {
6955 extern const TargetRegisterClass GR32_BPSP_and_GR32_DIBPRegClass = {
6967 extern const TargetRegisterClass GR32_BPSP_and_GR32_TCRegClass = {
6979 extern const TargetRegisterClass GR32_BSI_and_GR32_SIDIRegClass = {
6991 extern const TargetRegisterClass GR32_CB_and_GR32_DCRegClass = {
7003 extern const TargetRegisterClass GR32_DIBP_and_GR32_SIDIRegClass = {
7015 extern const TargetRegisterClass LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bitRegClass = {
7027 extern const TargetRegisterClass LOW32_ADDR_ACCESS_with_sub_32bitRegClass = {
7039 extern const TargetRegisterClass RFP64RegClass = {
7051 extern const TargetRegisterClass FR64XRegClass = {
7063 extern const TargetRegisterClass GR64RegClass = {
7075 extern const TargetRegisterClass CONTROL_REGRegClass = {
7087 extern const TargetRegisterClass FR64RegClass = {
7099 extern const TargetRegisterClass GR64_with_sub_8bitRegClass = {
7111 extern const TargetRegisterClass GR64_NOSPRegClass = {
7123 extern const TargetRegisterClass GR64_TCRegClass = {
7135 extern const TargetRegisterClass GR64_NOREXRegClass = {
7147 extern const TargetRegisterClass GR64_TCW64RegClass = {
7159 extern const TargetRegisterClass GR64_TC_with_sub_8bitRegClass = {
7171 extern const TargetRegisterClass GR64_NOSP_and_GR64_TCRegClass = {
7183 extern const TargetRegisterClass GR64_TCW64_with_sub_8bitRegClass = {
7195 extern const TargetRegisterClass GR64_TC_and_GR64_TCW64RegClass = {
7207 extern const TargetRegisterClass GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
7219 extern const TargetRegisterClass VK64RegClass = {
7231 extern const TargetRegisterClass VR64RegClass = {
7243 extern const TargetRegisterClass GR64_NOREX_NOSPRegClass = {
7255 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCRegClass = {
7267 extern const TargetRegisterClass GR64_NOSP_and_GR64_TCW64RegClass = {
7279 extern const TargetRegisterClass GR64_TCW64_and_GR64_TC_with_sub_8bitRegClass = {
7291 extern const TargetRegisterClass VK64WMRegClass = {
7303 extern const TargetRegisterClass GR64_TC_and_GR64_NOSP_and_GR64_TCW64RegClass = {
7315 extern const TargetRegisterClass GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREXRegClass = {
7327 extern const TargetRegisterClass GR64_NOREX_NOSP_and_GR64_TCRegClass = {
7339 extern const TargetRegisterClass GR64_NOREX_and_GR64_TCW64RegClass = {
7351 extern const TargetRegisterClass GR64_ABCDRegClass = {
7363 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_TCRegClass = {
7375 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TCRegClass = {
7387 extern const TargetRegisterClass GR64_ADRegClass = {
7399 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESS_RBPRegClass = {
7411 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSPRegClass = {
7423 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSIRegClass = {
7435 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CBRegClass = {
7447 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DCRegClass = {
7459 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBPRegClass = {
7471 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_SIDIRegClass = {
7483 extern const TargetRegisterClass GR64_and_LOW32_ADDR_ACCESSRegClass = {
7495 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSIRegClass = {
7507 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_AD_and_GR32_DCRegClass = {
7519 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBPRegClass = {
7531 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TCRegClass = {
7543 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDIRegClass = {
7555 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_CB_and_GR32_DCRegClass = {
7567 extern const TargetRegisterClass GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDIRegClass = {
7579 extern const TargetRegisterClass RSTRegClass = {
7591 extern const TargetRegisterClass RFP80RegClass = {
7603 extern const TargetRegisterClass RFP80_7RegClass = {
7615 extern const TargetRegisterClass VR128XRegClass = {
7627 extern const TargetRegisterClass VR128RegClass = {
7639 extern const TargetRegisterClass BNDRRegClass = {
7651 extern const TargetRegisterClass VR256XRegClass = {
7663 extern const TargetRegisterClass VR256RegClass = {
7675 extern const TargetRegisterClass VR512RegClass = {
7687 extern const TargetRegisterClass VR512_0_15RegClass = {
7702 const TargetRegisterClass* const RegisterClasses[] = {
8171 const TargetRegisterClass *X86GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
8171 const TargetRegisterClass *X86GenRegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
9600 getRegClassWeight(const TargetRegisterClass *RC) const {
9863 getRegClassPressureSets(const TargetRegisterClass *RC) const {
gen/lib/Target/XCore/XCoreGenRegisterInfo.inc 334 const RegClassWeight &getRegClassWeight(const TargetRegisterClass *RC) const override;
339 const int *getRegClassPressureSets(const TargetRegisterClass *RC) const override;
349 extern const TargetRegisterClass RRegsRegClass;
350 extern const TargetRegisterClass GRRegsRegClass;
392 static const TargetRegisterClass *const NullRegClasses[] = { nullptr };
406 static const TargetRegisterClass *const GRRegsSuperclasses[] = {
413 extern const TargetRegisterClass RRegsRegClass = {
425 extern const TargetRegisterClass GRRegsRegClass = {
440 const TargetRegisterClass* const RegisterClasses[] = {
467 getRegClassWeight(const TargetRegisterClass *RC) const {
516 getRegClassPressureSets(const TargetRegisterClass *RC) const {
include/llvm/CodeGen/ExecutionDomainFix.h 111 const TargetRegisterClass *const RC;
130 ExecutionDomainFix(char &PassID, const TargetRegisterClass &RC)
include/llvm/CodeGen/FastISel.h 393 const TargetRegisterClass *RC);
398 const TargetRegisterClass *RC, unsigned Op0,
404 const TargetRegisterClass *RC, unsigned Op0,
410 const TargetRegisterClass *RC, unsigned Op0,
417 const TargetRegisterClass *RC, unsigned Op0,
423 const TargetRegisterClass *RC, unsigned Op0,
429 const TargetRegisterClass *RC,
435 const TargetRegisterClass *RC, unsigned Op0,
442 const TargetRegisterClass *RC, uint64_t Imm);
471 unsigned createResultReg(const TargetRegisterClass *RC);
include/llvm/CodeGen/FunctionLoweringInfo.h 280 const TargetRegisterClass *RC);
include/llvm/CodeGen/GlobalISel/CSEInfo.h 180 addNodeIDRegType(const TargetRegisterClass *RC) const;
include/llvm/CodeGen/GlobalISel/InstructionSelector.h 482 const TargetRegisterClass &RC,
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 63 const TargetRegisterClass *RC;
72 DstOp(const TargetRegisterClass *TRC) : RC(TRC), Ty(DstType::Ty_RC) {}
105 const TargetRegisterClass *getRegClass() const {
include/llvm/CodeGen/GlobalISel/RegisterBank.h 71 bool covers(const TargetRegisterClass &RC) const;
include/llvm/CodeGen/GlobalISel/RegisterBankInfo.h 413 mutable DenseMap<unsigned, const TargetRegisterClass *> PhysRegMinimalRCs;
437 const TargetRegisterClass &
602 getRegBankFromRegClass(const TargetRegisterClass &RC) const {
643 static const TargetRegisterClass *
644 constrainGenericRegister(Register Reg, const TargetRegisterClass &RC,
include/llvm/CodeGen/GlobalISel/Utils.h 48 const TargetRegisterClass &RegClass);
63 const TargetRegisterClass &RegClass,
include/llvm/CodeGen/LiveStacks.h 42 std::map<int, const TargetRegisterClass *> S2RCMap;
61 LiveInterval &getOrCreateInterval(int Slot, const TargetRegisterClass *RC);
79 const TargetRegisterClass *getIntervalRegClass(int Slot) const {
81 std::map<int, const TargetRegisterClass *>::const_iterator I =
include/llvm/CodeGen/MIRParser/MIParser.h 40 const TargetRegisterClass *RC;
47 using Name2RegClassMap = StringMap<const TargetRegisterClass *>;
141 const TargetRegisterClass *getRegClass(StringRef Name);
include/llvm/CodeGen/MachineBasicBlock.h 334 unsigned addLiveIn(MCRegister PhysReg, const TargetRegisterClass *RC);
include/llvm/CodeGen/MachineFunction.h 646 unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
include/llvm/CodeGen/MachineInstr.h 1313 const TargetRegisterClass*
1330 const TargetRegisterClass *getRegClassConstraintEffectForVReg(
1331 Register Reg, const TargetRegisterClass *CurRC,
1344 const TargetRegisterClass *
1345 getRegClassConstraintEffect(unsigned OpIdx, const TargetRegisterClass *CurRC,
1689 const TargetRegisterClass *getRegClassConstraintEffectForVRegImpl(
1690 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
include/llvm/CodeGen/MachineRegisterInfo.h 47 PointerUnion<const TargetRegisterClass *, const RegisterBank *>;
214 bool shouldTrackSubRegLiveness(const TargetRegisterClass &RC) const {
631 const TargetRegisterClass *getRegClass(Register Reg) const {
634 return VRegInfo[Reg.id()].first.get<const TargetRegisterClass *>();
648 const TargetRegisterClass *getRegClassOrNull(unsigned Reg) const {
650 return Val.dyn_cast<const TargetRegisterClass *>();
670 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
691 const TargetRegisterClass *constrainRegClass(unsigned Reg,
692 const TargetRegisterClass *RC,
720 Register createVirtualRegister(const TargetRegisterClass *RegClass,
1180 const TargetRegisterClass *RC = MRI->getRegClass(RegUnit);
include/llvm/CodeGen/MachineSSAUpdater.h 45 const TargetRegisterClass *VRC;
include/llvm/CodeGen/RegisterClassInfo.h 70 void compute(const TargetRegisterClass *RC) const;
73 const RCInfo &get(const TargetRegisterClass *RC) const {
89 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const {
96 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const {
106 bool isProperSubClass(const TargetRegisterClass *RC) const {
122 unsigned getMinCost(const TargetRegisterClass *RC) {
130 unsigned getLastCostChange(const TargetRegisterClass *RC) {
include/llvm/CodeGen/RegisterScavenging.h 125 BitVector getRegsAvailable(const TargetRegisterClass *RC);
129 Register FindUnusedReg(const TargetRegisterClass *RC) const;
163 Register scavengeRegister(const TargetRegisterClass *RC,
166 Register scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj,
180 Register scavengeRegisterBackwards(const TargetRegisterClass &RC,
228 ScavengedInfo &spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
include/llvm/CodeGen/ScheduleDAG.h 302 const TargetRegisterClass *CopyDstRC =
304 const TargetRegisterClass *CopySrcRC = nullptr;
include/llvm/CodeGen/TargetInstrInfo.h 89 const TargetRegisterClass *getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
322 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
1320 virtual bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
include/llvm/CodeGen/TargetLowering.h 697 virtual const TargetRegisterClass *getRegClassFor(MVT VT, bool isDivergent = false) const {
699 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
719 virtual const TargetRegisterClass *getRepRegClassFor(MVT VT) const {
720 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
2019 void addRegisterClass(MVT VT, const TargetRegisterClass *RC) {
2026 virtual std::pair<const TargetRegisterClass *, uint8_t>
2744 const TargetRegisterClass *RegClassForVT[MVT::LAST_VALUETYPE];
2754 const TargetRegisterClass *RepRegClassForVT[MVT::LAST_VALUETYPE];
2920 const TargetRegisterClass &RC) const;
3939 virtual std::pair<unsigned, const TargetRegisterClass *>
include/llvm/CodeGen/TargetRegisterInfo.h 48 using sc_iterator = const TargetRegisterClass* const *;
118 bool hasSubClass(const TargetRegisterClass *RC) const {
123 bool hasSubClassEq(const TargetRegisterClass *RC) const {
130 bool hasSuperClass(const TargetRegisterClass *RC) const {
135 bool hasSuperClassEq(const TargetRegisterClass *RC) const {
230 using regclass_iterator = const TargetRegisterClass * const *;
271 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const {
277 unsigned getSpillSize(const TargetRegisterClass &RC) const {
283 unsigned getSpillAlignment(const TargetRegisterClass &RC) const {
288 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const {
297 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const {
301 vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const {
311 const TargetRegisterClass *
316 const TargetRegisterClass *
317 getAllocatableClass(const TargetRegisterClass *RC) const;
323 const TargetRegisterClass *RC = nullptr) const;
490 virtual bool isDivergentRegClass(const TargetRegisterClass *RC) const {
517 const TargetRegisterClass *RC) const {
526 virtual const TargetRegisterClass *
527 getMatchingSuperRegClass(const TargetRegisterClass *A,
528 const TargetRegisterClass *B, unsigned Idx) const;
534 virtual bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
536 const TargetRegisterClass *SrcRC,
551 virtual const TargetRegisterClass *
552 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const {
644 const TargetRegisterClass*
645 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
646 const TargetRegisterClass *RCB, unsigned SubB,
653 const RegClassInfo &getRegClassInfo(const TargetRegisterClass &RC) const {
671 const TargetRegisterClass *getRegClass(unsigned i) const {
677 const char *getRegClassName(const TargetRegisterClass *Class) const {
683 const TargetRegisterClass *
684 getCommonSubClass(const TargetRegisterClass *A,
685 const TargetRegisterClass *B) const;
690 virtual const TargetRegisterClass *
699 virtual const TargetRegisterClass *
700 getCrossCopyRegClass(const TargetRegisterClass *RC) const {
708 virtual const TargetRegisterClass *
709 getLargestLegalSuperClass(const TargetRegisterClass *RC,
722 virtual unsigned getRegPressureLimit(const TargetRegisterClass *RC,
738 const TargetRegisterClass *RC) const = 0;
760 const TargetRegisterClass *RC) const = 0;
915 const TargetRegisterClass *RC,
947 const TargetRegisterClass *SrcRC,
949 const TargetRegisterClass *DstRC,
951 const TargetRegisterClass *NewRC,
970 virtual const TargetRegisterClass *
1009 SuperRegClassIterator(const TargetRegisterClass *RC,
include/llvm/CodeGen/TargetSubtargetInfo.h 76 using RegClassVector = SmallVectorImpl<const TargetRegisterClass *>;
include/llvm/CodeGen/VirtRegMap.h 65 unsigned createSpillSlot(const TargetRegisterClass *RC);
include/llvm/Support/PointerLikeTypeTraits.h 56 static inline void *getAsVoidPointer(T *P) { return P; }
57 static inline T *getFromVoidPointer(void *P) { return static_cast<T *>(P); }
59 enum { NumLowBitsAvailable = detail::ConstantLog2<alignof(T)>::value };
91 typedef PointerLikeTypeTraits<T *> NonConst;
93 static inline const void *getAsVoidPointer(const T *P) {
96 static inline const T *getFromVoidPointer(const void *P) {
lib/CodeGen/AggressiveAntiDepBreaker.cpp 407 const TargetRegisterClass *RC = nullptr;
491 const TargetRegisterClass *RC = nullptr;
533 const TargetRegisterClass *RC = Q.second.RC;
629 const TargetRegisterClass *SuperRC =
lib/CodeGen/AggressiveAntiDepBreaker.h 48 const TargetRegisterClass *RC;
158 using RenameOrderType = std::map<const TargetRegisterClass *, unsigned>;
lib/CodeGen/AsmPrinter/DwarfExpression.cpp 136 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(MachineReg);
lib/CodeGen/BreakFalseDeps.cpp 125 const TargetRegisterClass *OpRC =
lib/CodeGen/CalcSpillWeights.cpp 72 const TargetRegisterClass *rc = mri.getRegClass(reg);
lib/CodeGen/CallingConvLower.cpp 251 const TargetRegisterClass *RC = TL->getRegClassFor(RegVT);
lib/CodeGen/CriticalAntiDepBreaker.cpp 192 const TargetRegisterClass *NewRC = nullptr;
310 const TargetRegisterClass *NewRC = nullptr;
395 const TargetRegisterClass *RC,
629 const TargetRegisterClass *RC = AntiDepReg != 0 ? Classes[AntiDepReg]
lib/CodeGen/CriticalAntiDepBreaker.h 53 std::vector<const TargetRegisterClass *> Classes;
106 const TargetRegisterClass *RC,
lib/CodeGen/DetectDeadLanes.cpp 154 const TargetRegisterClass *DstRC,
158 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
254 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
373 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
438 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
487 const TargetRegisterClass *DstRC = MRI->getRegClass(DefReg);
lib/CodeGen/GlobalISel/CSEInfo.cpp 291 GISelInstProfileBuilder::addNodeIDRegType(const TargetRegisterClass *RC) const {
lib/CodeGen/GlobalISel/InstructionSelect.cpp 200 const TargetRegisterClass *RC = MRI.getRegClassOrNull(VReg);
lib/CodeGen/GlobalISel/InstructionSelector.cpp 37 MachineInstr &I, unsigned OpIdx, const TargetRegisterClass &RC,
lib/CodeGen/GlobalISel/RegisterBank.cpp 34 const TargetRegisterClass &RC = *TRI.getRegClass(RCId);
45 const TargetRegisterClass &SubRC = *TRI.getRegClass(RCId);
60 bool RegisterBank::covers(const TargetRegisterClass &RC) const {
104 const TargetRegisterClass &RC = *TRI->getRegClass(RCId);
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 92 if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
97 const TargetRegisterClass &
104 const TargetRegisterClass *PhysRC = TRI.getMinimalPhysRegClass(Reg);
114 const TargetRegisterClass *RC = MI.getRegClassConstraint(OpIdx, &TII, &TRI);
126 const TargetRegisterClass *RegisterBankInfo::constrainGenericRegister(
127 Register Reg, const TargetRegisterClass &RC, MachineRegisterInfo &MRI) {
131 if (RegClassOrBank.is<const TargetRegisterClass *>())
lib/CodeGen/GlobalISel/Utils.cpp 33 const TargetRegisterClass &RegClass) {
44 const TargetRegisterClass &RegClass, const MachineOperand &RegMO,
79 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF);
lib/CodeGen/LiveDebugVariables.cpp 1184 const TargetRegisterClass *TRC = MRI.getRegClass(VirtReg);
lib/CodeGen/LiveIntervals.cpp 1660 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
lib/CodeGen/LiveStacks.cpp 57 LiveStacks::getOrCreateInterval(int Slot, const TargetRegisterClass *RC) {
69 const TargetRegisterClass *OldRC = S2RCMap[Slot];
82 const TargetRegisterClass *RC = getIntervalRegClass(Slot);
lib/CodeGen/LocalStackSlotAllocation.cpp 413 const TargetRegisterClass *RC = TRI->getPointerRegClass(*MF);
lib/CodeGen/MIRParser/MIParser.cpp 280 const auto *RC = TRI->getRegClass(I);
303 const TargetRegisterClass *
1235 const TargetRegisterClass *RC = PFS.Target.getRegClass(Name);
lib/CodeGen/MIRParser/MIRParser.cpp 515 const auto *RC = Target->getRegClass(VReg.Class.Value);
lib/CodeGen/MachineBasicBlock.cpp 493 MachineBasicBlock::addLiveIn(MCRegister PhysReg, const TargetRegisterClass *RC) {
lib/CodeGen/MachineCopyPropagation.cpp 326 if (const TargetRegisterClass *URC =
349 const TargetRegisterClass *UseDstRC =
352 const TargetRegisterClass *SuperRC = UseDstRC;
353 for (TargetRegisterClass::sc_iterator SuperRCI = UseDstRC->getSuperClasses();
lib/CodeGen/MachineFunction.cpp 584 const TargetRegisterClass *RC) {
588 const TargetRegisterClass *VRegRC = MRI.getRegClass(VReg);
lib/CodeGen/MachineInstr.cpp 830 const TargetRegisterClass*
870 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVReg(
871 Register Reg, const TargetRegisterClass *CurRC, const TargetInstrInfo *TII,
887 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffectForVRegImpl(
888 unsigned OpIdx, Register Reg, const TargetRegisterClass *CurRC,
899 const TargetRegisterClass *MachineInstr::getRegClassConstraintEffect(
900 unsigned OpIdx, const TargetRegisterClass *CurRC,
902 const TargetRegisterClass *OpRC = getRegClassConstraint(OpIdx, TII, TRI);
lib/CodeGen/MachineLICM.cpp 860 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
1304 const TargetRegisterClass *RC = TII->getRegClass(MID, LoadRegIndex, TRI, MF);
1389 SmallVector<const TargetRegisterClass*, 2> OrigRCs;
lib/CodeGen/MachineRegisterInfo.cpp 58 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
68 static const TargetRegisterClass *
70 const TargetRegisterClass *OldRC,
71 const TargetRegisterClass *RC, unsigned MinNumRegs) {
74 const TargetRegisterClass *NewRC =
84 const TargetRegisterClass *
86 const TargetRegisterClass *RC,
105 else if (RegCB.is<const TargetRegisterClass *>() !=
106 ConstrainingRegCB.is<const TargetRegisterClass *>())
108 else if (RegCB.is<const TargetRegisterClass *>()) {
110 *this, Reg, RegCB.get<const TargetRegisterClass *>(),
111 ConstrainingRegCB.get<const TargetRegisterClass *>(), MinNumRegs))
124 const TargetRegisterClass *OldRC = getRegClass(Reg);
125 const TargetRegisterClass *NewRC =
158 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass,
502 const TargetRegisterClass &TRC = *getRegClass(Reg);
lib/CodeGen/MachineSink.cpp 212 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg);
213 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg);
lib/CodeGen/MachineVerifier.cpp 1691 if (const TargetRegisterClass *DRC =
1712 const TargetRegisterClass *RC = MRI->getRegClassOrNull(Reg);
1775 const TargetRegisterClass *SRC =
1791 if (const TargetRegisterClass *DRC =
1794 const TargetRegisterClass *SuperRC =
lib/CodeGen/ModuloSchedule.cpp 547 const TargetRegisterClass *RC = MRI.getRegClass(Def);
663 const TargetRegisterClass *RC = MRI.getRegClass(Def);
1032 const TargetRegisterClass *RC = MRI.getRegClass(reg);
1254 DenseMap<const TargetRegisterClass *, Register> Undefs;
1268 const TargetRegisterClass *RC = nullptr);
1270 Register undef(const TargetRegisterClass *RC);
1449 const TargetRegisterClass *RC) {
1498 Register KernelRewriter::undef(const TargetRegisterClass *RC) {
lib/CodeGen/PHIElimination.cpp 281 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
lib/CodeGen/PeepholeOptimizer.cpp 473 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
570 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
668 const TargetRegisterClass *DefRC = MRI->getRegClass(Reg);
730 const TargetRegisterClass *SrcRC = MRI->getRegClass(CurSrcPair.Reg);
760 const TargetRegisterClass *NewRC = MRI.getRegClass(SrcRegs[0].Reg);
1231 const TargetRegisterClass *DefRC = MRI->getRegClass(Def.Reg);
lib/CodeGen/PostRASchedulerList.cpp 150 SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs);
209 SmallVectorImpl<const TargetRegisterClass *> &CriticalPathRCs)
294 SmallVector<const TargetRegisterClass*, 4> CriticalPathRCs;
lib/CodeGen/PrologEpilogInserter.cpp 418 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
551 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
578 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
lib/CodeGen/RegAllocFast.cpp 255 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
321 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
347 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
667 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
761 const TargetRegisterClass &RC = *MRI->getRegClass(VirtReg);
lib/CodeGen/RegAllocGreedy.cpp 711 const TargetRegisterClass &RC = *MRI->getRegClass(Reg);
1127 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg.reg);
2065 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC,
2070 const TargetRegisterClass *ConstrainedRC =
2088 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
2105 const TargetRegisterClass *SuperRC =
2532 const TargetRegisterClass *CurRC = MRI->getRegClass(VirtReg.reg);
lib/CodeGen/RegAllocPBQP.cpp 604 const TargetRegisterClass *TRC = MRI.getRegClass(VReg);
756 const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg);
lib/CodeGen/RegisterClassInfo.cpp 90 void RegisterClassInfo::compute(const TargetRegisterClass *RC) const {
147 if (const TargetRegisterClass *Super =
170 const TargetRegisterClass *RC = nullptr;
172 for (const TargetRegisterClass *C : TRI->regclasses()) {
lib/CodeGen/RegisterCoalescer.cpp 436 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src);
437 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
1255 const TargetRegisterClass *DefRC = TII->getRegClass(MCID, 0, TRI, *MF);
1290 const TargetRegisterClass *NewRC = CP.getNewRC();
1296 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
1297 const TargetRegisterClass *CommonRC =
lib/CodeGen/RegisterCoalescer.h 55 const TargetRegisterClass *NewRC = nullptr;
107 const TargetRegisterClass *getNewRC() const { return NewRC; }
lib/CodeGen/RegisterScavenging.cpp 287 Register RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
298 BitVector RegScavenger::getRegsAvailable(const TargetRegisterClass *RC) {
460 RegScavenger::spill(Register Reg, const TargetRegisterClass &RC, int SPAdj,
534 Register RegScavenger::scavengeRegister(const TargetRegisterClass *RC,
579 Register RegScavenger::scavengeRegisterBackwards(const TargetRegisterClass &RC,
666 const TargetRegisterClass &RC = *MRI.getRegClass(VReg);
lib/CodeGen/RenameIndependentSubregs.cpp 133 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
lib/CodeGen/ScheduleDAGInstrs.cpp 365 const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
lib/CodeGen/SelectionDAG/DAGCombiner.cpp14426 const TargetRegisterClass *ResRC =
14428 const TargetRegisterClass *ArgRC =
lib/CodeGen/SelectionDAG/FastISel.cpp 1550 const TargetRegisterClass *SrcClass = TLI.getRegClassFor(SrcVT);
1551 const TargetRegisterClass *DstClass = TLI.getRegClassFor(DstVT);
2016 unsigned FastISel::createResultReg(const TargetRegisterClass *RC) {
2023 const TargetRegisterClass *RegClass =
2038 const TargetRegisterClass *RC) {
2047 const TargetRegisterClass *RC, unsigned Op0,
2068 const TargetRegisterClass *RC, unsigned Op0,
2092 const TargetRegisterClass *RC, unsigned Op0,
2120 const TargetRegisterClass *RC, unsigned Op0,
2142 const TargetRegisterClass *RC, unsigned Op0,
2167 const TargetRegisterClass *RC,
2186 const TargetRegisterClass *RC, unsigned Op0,
2212 const TargetRegisterClass *RC, uint64_t Imm) {
2232 const TargetRegisterClass *RC = MRI.getRegClass(Op0);
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp 191 std::pair<unsigned, const TargetRegisterClass *> PhysReg =
519 const Value *CPI, const TargetRegisterClass *RC) {
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 103 const TargetRegisterClass *UseRC = nullptr;
133 const TargetRegisterClass *RC = nullptr;
141 const TargetRegisterClass *ComRC =
156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr;
203 const TargetRegisterClass *RC =
210 const TargetRegisterClass *VTRC = TLI->getRegClassFor(
233 const TargetRegisterClass *RegRC = MRI->getRegClass(Reg);
273 const TargetRegisterClass *RC = TLI->getRegClassFor(
312 const TargetRegisterClass *OpRC = nullptr;
317 const TargetRegisterClass *ConstrainedRC
378 const TargetRegisterClass *IIRC =
381 const TargetRegisterClass *OpRC =
451 const TargetRegisterClass *VRC = MRI->getRegClass(VReg);
452 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx);
499 const TargetRegisterClass *TRC =
569 const TargetRegisterClass *SRC =
614 const TargetRegisterClass *DstRC =
632 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
654 const TargetRegisterClass *TRC = MRI->getRegClass(SubReg);
655 const TargetRegisterClass *SRC =
lib/CodeGen/SelectionDAG/ResourcePriorityQueue.cpp 59 for (const TargetRegisterClass *RC : TRI->regclasses())
360 for (const TargetRegisterClass *RC : TRI->regclasses())
364 for (const TargetRegisterClass *RC : TRI->regclasses()) {
478 const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
489 const TargetRegisterClass *RC = TLI->getRegClassFor(VT);
lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp 104 const TargetRegisterClass*,
105 const TargetRegisterClass*,
381 const TargetRegisterClass *DestRC,
382 const TargetRegisterClass *SrcRC,
573 const TargetRegisterClass *RC =
575 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 266 const TargetRegisterClass*,
267 const TargetRegisterClass*,
325 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
334 const TargetRegisterClass *RC = TRI->getRegClass(DstRCIdx);
342 const TargetRegisterClass *RC = TII->getRegClass(Desc, Idx, TRI, MF);
1223 const TargetRegisterClass *DestRC,
1224 const TargetRegisterClass *SrcRC,
1557 const TargetRegisterClass *RC =
1559 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
1767 for (const TargetRegisterClass *RC : TRI->regclasses())
2073 for (const TargetRegisterClass *RC : TRI->regclasses()) {
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp 133 const TargetRegisterClass *RC =
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 958 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front());
6699 const TargetRegisterClass *PtrRC = TLI.getRegClassFor(PtrVT);
7815 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
7818 std::pair<unsigned, const TargetRegisterClass *> InputRC =
7898 const TargetRegisterClass *RC;
7966 TargetRegisterClass::iterator I = RC->begin();
8267 if (const TargetRegisterClass *RC = TLI.getRegClassFor(RegVT)) {
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 1230 const TargetRegisterClass *PtrRC =
lib/CodeGen/SelectionDAG/TargetLowering.cpp 4115 std::pair<unsigned, const TargetRegisterClass *>
4126 std::pair<unsigned, const TargetRegisterClass *> R =
4130 for (const TargetRegisterClass *RC : RI->regclasses()) {
4136 for (TargetRegisterClass::iterator I = RC->begin(), E = RC->end();
4139 std::pair<unsigned, const TargetRegisterClass *> S =
4343 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
4346 std::pair<unsigned, const TargetRegisterClass *> InputRC =
lib/CodeGen/SplitKit.cpp 560 const TargetRegisterClass *RC = MRI.getRegClass(FromReg);
lib/CodeGen/StackMaps.cpp 153 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg());
lib/CodeGen/SwiftErrorValueTracking.cpp 36 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
58 const TargetRegisterClass *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
126 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
241 auto const *RC = TLI->getRegClassFor(TLI->getPointerTy(DL));
lib/CodeGen/TailDuplicator.cpp 348 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
391 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
405 const TargetRegisterClass *ConstrRC;
lib/CodeGen/TargetInstrInfo.cpp 44 const TargetRegisterClass*
378 bool TargetInstrInfo::getStackSlotRange(const TargetRegisterClass *RC,
433 static const TargetRegisterClass *canFoldCopy(const MachineInstr &MI,
452 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
514 const TargetRegisterClass *RC =
605 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
781 const TargetRegisterClass *RC = Root.getRegClassConstraint(0, TII, TRI);
lib/CodeGen/TargetLoweringBase.cpp 1009 const TargetRegisterClass &RC) const {
1135 std::pair<const TargetRegisterClass *, uint8_t>
1138 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1148 const TargetRegisterClass *BestRC = RC;
1150 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1368 const TargetRegisterClass* RRC;
lib/CodeGen/TargetRegisterInfo.cpp 172 const TargetRegisterClass *
173 TargetRegisterInfo::getAllocatableClass(const TargetRegisterClass *RC) const {
179 const TargetRegisterClass *SubRC = getRegClass(It.getID());
189 const TargetRegisterClass *
196 const TargetRegisterClass* BestRC = nullptr;
197 for (const TargetRegisterClass* RC : regclasses()) {
210 const TargetRegisterClass *RC, BitVector &R){
218 const TargetRegisterClass *RC) const {
222 const TargetRegisterClass *SubClass = getAllocatableClass(RC);
226 for (const TargetRegisterClass *C : regclasses())
239 const TargetRegisterClass *firstCommonClass(const uint32_t *A,
248 const TargetRegisterClass *
249 TargetRegisterInfo::getCommonSubClass(const TargetRegisterClass *A,
250 const TargetRegisterClass *B) const {
262 const TargetRegisterClass *
263 TargetRegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
264 const TargetRegisterClass *B,
278 const TargetRegisterClass *TargetRegisterInfo::
279 getCommonSuperRegClass(const TargetRegisterClass *RCA, unsigned SubA,
280 const TargetRegisterClass *RCB, unsigned SubB,
296 const TargetRegisterClass *BestRC = nullptr;
313 const TargetRegisterClass *RC =
343 const TargetRegisterClass *DefRC,
345 const TargetRegisterClass *SrcRC,
373 bool TargetRegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
375 const TargetRegisterClass *SrcRC,
474 const TargetRegisterClass *RC{};
lib/CodeGen/TwoAddressInstructionPass.cpp 1361 const TargetRegisterClass *RC =
1486 if (const TargetRegisterClass *RC = TII->getRegClass(MCID, SrcIdx,
1557 const TargetRegisterClass *RC = MRI->getRegClass(RegB);
lib/CodeGen/VirtRegMap.cpp 93 unsigned VirtRegMap::createSpillSlot(const TargetRegisterClass *RC) {
123 const TargetRegisterClass* RC = MF->getRegInfo().getRegClass(virtReg);
lib/Target/AArch64/AArch64AsmPrinter.cpp 154 const TargetRegisterClass *RC, unsigned AltName,
549 const TargetRegisterClass *RC,
594 const TargetRegisterClass *RC;
635 const TargetRegisterClass *RegClass;
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp 160 const TargetRegisterClass *RC = TII->getRegClass(Desc, I, TRI, MF);
lib/Target/AArch64/AArch64FastISel.cpp 388 const TargetRegisterClass *RC = (VT == MVT::i64) ? &AArch64::GPR64RegClass
420 const TargetRegisterClass *RC = Is64Bit ?
1335 const TargetRegisterClass *RC =
1377 const TargetRegisterClass *RC;
1422 const TargetRegisterClass *RC =
1464 const TargetRegisterClass *RC = nullptr;
1701 const TargetRegisterClass *RC;
1753 const TargetRegisterClass *RC;
1853 const TargetRegisterClass *RC;
2716 const TargetRegisterClass *RC;
3026 const TargetRegisterClass *RC;
4053 const TargetRegisterClass *RC =
4092 const TargetRegisterClass *RC =
4120 const TargetRegisterClass *RC =
4198 const TargetRegisterClass *RC =
4227 const TargetRegisterClass *RC =
4319 const TargetRegisterClass *RC =
4348 const TargetRegisterClass *RC =
4471 const TargetRegisterClass *RC =
4664 const TargetRegisterClass *RC =
4860 const TargetRegisterClass *RC = nullptr;
4956 const TargetRegisterClass *RC;
5095 const TargetRegisterClass *ResRC;
lib/Target/AArch64/AArch64FrameLowering.cpp 2291 const TargetRegisterClass &RC = AArch64::GPR64RegClass;
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 280 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF);
lib/Target/AArch64/AArch64ISelLowering.cpp 3205 const TargetRegisterClass *RC;
5974 std::pair<unsigned, const TargetRegisterClass *>
6028 std::pair<unsigned, const TargetRegisterClass *> Res;
12386 const TargetRegisterClass *RC = nullptr;
lib/Target/AArch64/AArch64ISelLowering.h 725 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/AArch64/AArch64InstrInfo.cpp 503 const TargetRegisterClass *RC =
623 const TargetRegisterClass *RC = nullptr;
1059 const TargetRegisterClass *OpRegCstraints =
3275 const TargetRegisterClass *SpillRC;
3320 const TargetRegisterClass *FillRC;
3986 unsigned MaddOpc, const TargetRegisterClass *RC,
4066 const TargetRegisterClass *RC) {
4109 const TargetRegisterClass *RC;
4154 const TargetRegisterClass *OrrRC;
4198 const TargetRegisterClass *SubRC;
4246 const TargetRegisterClass *OrrRC;
lib/Target/AArch64/AArch64InstructionSelector.cpp 99 const TargetRegisterClass *DstRC,
303 static const TargetRegisterClass *
334 static const TargetRegisterClass *
369 static bool getSubRegForClass(const TargetRegisterClass *RC,
594 const TargetRegisterClass *From,
595 const TargetRegisterClass *To,
616 static std::pair<const TargetRegisterClass *, const TargetRegisterClass *>
616 static std::pair<const TargetRegisterClass *, const TargetRegisterClass *>
652 const TargetRegisterClass *SrcRC;
653 const TargetRegisterClass *DstRC;
701 const TargetRegisterClass *SubregRC =
1056 const TargetRegisterClass *RC = nullptr;
1339 const TargetRegisterClass *DefRC
1340 = RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
1542 const TargetRegisterClass &GPRRC =
1544 const TargetRegisterClass &FPRRC =
1959 const TargetRegisterClass *DstRC =
1964 const TargetRegisterClass *SrcRC =
2284 const TargetRegisterClass *DstRC =
2652 const TargetRegisterClass *SrcRC =
2683 unsigned EltSize, const TargetRegisterClass *DstRC, Register Scalar,
2816 const TargetRegisterClass *DstRC =
2825 const TargetRegisterClass *VecRC =
3037 const TargetRegisterClass *RC =
3302 const TargetRegisterClass *DstRC =
3747 const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass;
3822 const TargetRegisterClass *RC =
3862 const TargetRegisterClass *DstRC = &AArch64::FPR128RegClass;
3887 const TargetRegisterClass *RC =
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 226 const TargetRegisterClass &RC) const {
lib/Target/AArch64/AArch64RegisterBankInfo.h 136 getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
lib/Target/AArch64/AArch64RegisterInfo.cpp 100 const TargetRegisterClass *
101 AArch64RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
248 const TargetRegisterClass *
254 const TargetRegisterClass *
255 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
538 unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
lib/Target/AArch64/AArch64RegisterInfo.h 59 const TargetRegisterClass *
60 getSubClassWithSubReg(const TargetRegisterClass *RC,
88 const TargetRegisterClass *
91 const TargetRegisterClass *
92 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
118 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 90 const TargetRegisterClass RC;
352 const TargetRegisterClass *RC = &AArch64::FPR128RegClass;
lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.cpp 80 std::pair<const ArgDescriptor *, const TargetRegisterClass *>
lib/Target/AMDGPU/AMDGPUArgumentUsageInfo.h 151 std::pair<const ArgDescriptor *, const TargetRegisterClass *>
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 179 const TargetRegisterClass *getOperandRegClass(SDNode *N, unsigned OpNo) const;
545 const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
578 const TargetRegisterClass *SuperRC =
2645 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
2664 const TargetRegisterClass *CommutedRC = getOperandRegClass(*U, CommutedOpNo);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 4087 const TargetRegisterClass *RC,
4153 const TargetRegisterClass *RC,
lib/Target/AMDGPU/AMDGPUISelLowering.h 278 const TargetRegisterClass *RC,
283 const TargetRegisterClass *RC,
290 const TargetRegisterClass *RC,
309 const TargetRegisterClass *RC,
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 77 const TargetRegisterClass *RC =
78 RegClassOrBank.dyn_cast<const TargetRegisterClass*>();
100 const TargetRegisterClass *RC =
101 RegClassOrBank.dyn_cast<const TargetRegisterClass*>();
124 const TargetRegisterClass *RC
146 const TargetRegisterClass *RC =
158 const TargetRegisterClass *SrcRC =
171 const TargetRegisterClass *RC =
189 const TargetRegisterClass *DefRC
190 = RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
216 const TargetRegisterClass &SubRC,
271 const TargetRegisterClass *RC = TRI.getBoolRC();
343 const TargetRegisterClass &RC
345 const TargetRegisterClass &HalfRC
364 const TargetRegisterClass *CarryRC = TRI.getWaveMaskRegClass();
450 const TargetRegisterClass *RC =
473 const TargetRegisterClass *DstRC =
486 const TargetRegisterClass *SrcRC
515 const TargetRegisterClass *SrcRC =
531 const TargetRegisterClass *DstRC =
550 const TargetRegisterClass *RC = TRI.getConstrainedRegClassForOperand(MO, *MRI);
580 const TargetRegisterClass *DstRC =
587 const TargetRegisterClass *Src0RC =
589 const TargetRegisterClass *Src1RC =
1181 const TargetRegisterClass *SrcRC
1183 const TargetRegisterClass *DstRC
1240 const TargetRegisterClass *DstRC =
1418 const TargetRegisterClass *RC = TRI.getRegClassForReg(*MRI, DstReg);
1442 const TargetRegisterClass *RC = IsSgpr ?
1463 const TargetRegisterClass *DstRC =
1564 const TargetRegisterClass *ConstrainRC;
1626 const TargetRegisterClass &RegRC
1631 const TargetRegisterClass *DstRC = TRI.getRegClassForTypeOnBank(Ty, *DstRB,
1633 const TargetRegisterClass *SrcRC = TRI.getRegClassForTypeOnBank(Ty, *SrcRB,
lib/Target/AMDGPU/AMDGPUInstructionSelector.h 76 const TargetRegisterClass &SubRC,
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1844 const TargetRegisterClass *RC;
2024 const TargetRegisterClass *RC;
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 1933 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectReg);
2000 const TargetRegisterClass *RegClass = MRI->getRegClass(DestReg);
2060 const TargetRegisterClass *RegClass = MRI->getRegClass(Reg);
2175 const TargetRegisterClass *RegClass =
2313 const TargetRegisterClass *RegClass = MRI->getRegClass(BBSelectRegIn);
2450 const TargetRegisterClass *RegClass = MRI->getRegClass(PHIDest);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 168 const TargetRegisterClass &RC) const {
673 const TargetRegisterClass *WaveRC = TRI->getWaveMaskRegClass();
1012 const TargetRegisterClass *Constrained =
lib/Target/AMDGPU/AMDGPURegisterBankInfo.h 153 getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
lib/Target/AMDGPU/AMDGPUSubtarget.h 1175 const TargetRegisterClass *getBoolRC() const {
lib/Target/AMDGPU/AMDILCFGStructurizer.cpp 1231 const TargetRegisterClass * I32RC = TRI->getCFGStructurizerRegClass(MVT::i32);
lib/Target/AMDGPU/GCNRegBankReassign.cpp 280 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
307 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
441 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysReg);
591 const TargetRegisterClass *RC = MRI->getRegClass(LI.reg);
lib/Target/AMDGPU/R600InstrInfo.cpp 1109 const TargetRegisterClass *R600InstrInfo::getIndirectAddrRegClass() const {
1192 const TargetRegisterClass *IndirectRC = getIndirectAddrRegClass();
lib/Target/AMDGPU/R600InstrInfo.h 231 const TargetRegisterClass *getIndirectAddrRegClass() const;
lib/Target/AMDGPU/R600MachineScheduler.cpp 211 const TargetRegisterClass *RC) const {
lib/Target/AMDGPU/R600MachineScheduler.h 83 bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const;
lib/Target/AMDGPU/R600RegisterInfo.cpp 52 for (TargetRegisterClass::iterator I = R600::R600_AddrRegClass.begin(),
82 const TargetRegisterClass * R600RegisterInfo::getCFGStructurizerRegClass(
91 const TargetRegisterClass *RC) const {
lib/Target/AMDGPU/R600RegisterInfo.h 38 const TargetRegisterClass *getCFGStructurizerRegClass(MVT VT) const;
41 getRegClassWeight(const TargetRegisterClass *RC) const override;
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 166 static std::pair<const TargetRegisterClass *, const TargetRegisterClass *>
166 static std::pair<const TargetRegisterClass *, const TargetRegisterClass *>
173 const TargetRegisterClass *SrcRC = Register::isVirtualRegister(SrcReg)
180 const TargetRegisterClass *DstRC = Register::isVirtualRegister(DstReg)
187 static bool isVGPRToSGPRCopy(const TargetRegisterClass *SrcRC,
188 const TargetRegisterClass *DstRC,
194 static bool isSGPRToVGPRCopy(const TargetRegisterClass *SrcRC,
195 const TargetRegisterClass *DstRC,
260 const TargetRegisterClass *SrcRC, *DstRC;
291 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
296 const TargetRegisterClass *NewSrcRC = TRI->getEquivalentVGPRClass(SrcRC);
305 const TargetRegisterClass *NewSrcRC = TRI->getEquivalentAGPRClass(SrcRC);
613 const TargetRegisterClass *SrcRC, *DstRC;
675 const TargetRegisterClass *DstRC, *Src0RC, *Src1RC;
786 const TargetRegisterClass *UseRC = MRI->getRegClass(Use.getReg());
793 const TargetRegisterClass *OpRC =
803 const TargetRegisterClass *RC0 = MRI->getRegClass(PHIRes);
816 const TargetRegisterClass *RC =
lib/Target/AMDGPU/SIFixupVectorISel.cpp 126 const TargetRegisterClass *IdxRC, *BaseRC;
lib/Target/AMDGPU/SIFoldOperands.cpp 257 const TargetRegisterClass *Dst0RC = MRI.getRegClass(Dst0.getReg());
621 const TargetRegisterClass *DestRC = MRI->getRegClass(DestReg);
625 const TargetRegisterClass * SrcRC = MRI->getRegClass(SrcReg);
841 const TargetRegisterClass *FoldRC =
847 const TargetRegisterClass *UseRC = MRI->getRegClass(UseReg);
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 161 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
lib/Target/AMDGPU/SIFrameLowering.cpp 52 const TargetRegisterClass &RC,
lib/Target/AMDGPU/SIISelLowering.cpp 1406 const TargetRegisterClass *RC;
1557 const TargetRegisterClass *RC;
1675 const TargetRegisterClass *RC,
1995 const TargetRegisterClass *RC = nullptr;
2167 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2469 const TargetRegisterClass *ArgRC;
2476 const TargetRegisterClass *IncomingArgRC;
2507 const TargetRegisterClass *ArgRC;
3183 const TargetRegisterClass *BoolRC = TRI->getBoolRC();
3285 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
3318 const TargetRegisterClass *SuperRC,
3343 const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
3401 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
3463 const TargetRegisterClass *VecRC) {
3493 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
3603 const TargetRegisterClass *BoolRC = TRI->getBoolRC();
3761 const auto *CondRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
10325 const TargetRegisterClass *RC =
10539 std::pair<unsigned, const TargetRegisterClass *>
10543 const TargetRegisterClass *RC = nullptr;
10936 const TargetRegisterClass *
10938 const TargetRegisterClass *RC = TargetLoweringBase::getRegClassFor(VT, false);
11025 const TargetRegisterClass *RC;
lib/Target/AMDGPU/SIISelLowering.h 371 std::pair<unsigned, const TargetRegisterClass *>
399 virtual const TargetRegisterClass *
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 494 const TargetRegisterClass *RC = TII->getOpRegClass(MIA, OpNo);
lib/Target/AMDGPU/SIInstrInfo.cpp 480 const TargetRegisterClass *DstRC = Register::isVirtualRegister(Reg)
528 const TargetRegisterClass *RC = RI.getPhysRegClass(DestReg);
756 const TargetRegisterClass *RegClass = MRI.getRegClass(DestReg);
807 const TargetRegisterClass *
821 const TargetRegisterClass *BoolXExecRC =
966 unsigned SIInstrInfo::getMovOpcode(const TargetRegisterClass *DstRC) const {
2126 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2140 const TargetRegisterClass *RC = MRI.getRegClass(TrueReg);
2168 const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
2210 const TargetRegisterClass *EltRC = &AMDGPU::VGPR_32RegClass;
3215 const TargetRegisterClass *RC = MI.getRegClassConstraint(I, this, &RI);
3292 const TargetRegisterClass *RC = RI.getRegClass(RegClass);
3415 const TargetRegisterClass *DstRC = getOpRegClass(MI, DstIdx);
3669 const TargetRegisterClass *RC = getOpRegClass(MI, VAddr0Idx);
3807 const TargetRegisterClass *SIInstrInfo::getOpRegClass(const MachineInstr &MI,
3832 const TargetRegisterClass *RC = RI.getRegClass(RCID);
3840 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(RC);
3920 const TargetRegisterClass *RC = Register::isVirtualRegister(Reg)
3924 const TargetRegisterClass *DRC = RI.getRegClass(OpInfo.RegClass);
3927 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF);
3956 const TargetRegisterClass *DefinedRC =
4213 const TargetRegisterClass *VRC = MRI.getRegClass(SrcReg);
4214 const TargetRegisterClass *SRC = RI.getEquivalentSGPRClass(VRC);
4281 const TargetRegisterClass *OpRC = RI.getSubClassWithSubReg(
4332 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4413 const auto *BoolXExecRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
4540 const TargetRegisterClass *RC = nullptr, *SRC = nullptr, *VRC = nullptr;
4545 const TargetRegisterClass *OpRC =
4597 const TargetRegisterClass *DstRC = getOpRegClass(MI, 0);
4607 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
4608 const TargetRegisterClass *VRC = RI.getEquivalentVGPRClass(OpRC);
4625 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst);
4626 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0);
4702 const auto *BoolXExecRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
5061 const TargetRegisterClass *NewDstRC = getDestEquivalentVGPRClass(Inst);
5299 const TargetRegisterClass *Src0RC = Src0.isReg() ?
5303 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
5308 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5309 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
5310 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
5347 const auto *CarryRC = RI.getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
5362 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
5363 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg());
5364 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
5365 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
5426 const TargetRegisterClass *Src0RC = Src0.isReg() ?
5430 const TargetRegisterClass *Src0SubRC = RI.getSubRegClass(Src0RC, AMDGPU::sub0);
5431 const TargetRegisterClass *Src1RC = Src1.isReg() ?
5435 const TargetRegisterClass *Src1SubRC = RI.getSubRegClass(Src1RC, AMDGPU::sub0);
5446 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5447 const TargetRegisterClass *NewDestRC = RI.getEquivalentVGPRClass(DestRC);
5448 const TargetRegisterClass *NewDestSubRC = RI.getSubRegClass(NewDestRC, AMDGPU::sub0);
5489 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5530 const TargetRegisterClass *SrcRC = Src.isReg() ?
5537 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0);
5734 const TargetRegisterClass *SIInstrInfo::getDestEquivalentVGPRClass(
5736 const TargetRegisterClass *NewDstRC = getOpRegClass(Inst, 0);
5749 const TargetRegisterClass *SrcRC = getOpRegClass(Inst, 1);
5814 const TargetRegisterClass *OpRC = RI.getRegClass(Desc.OpInfo[Idx].RegClass);
5821 const TargetRegisterClass *RegRC = MRI.getRegClass(Reg);
lib/Target/AMDGPU/SIInstrInfo.h 127 const TargetRegisterClass *
208 const TargetRegisterClass *getPreferredSelectRegClass(
243 unsigned getMovOpcode(const TargetRegisterClass *DstRC) const;
798 const TargetRegisterClass *getOpRegClass(const MachineInstr &MI,
1020 const TargetRegisterClass *getRegClass(const MCInstrDesc &TID, unsigned OpNum,
1034 const TargetRegisterClass &TRC,
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 217 const TargetRegisterClass *getTargetRegisterClass(const CombineInfo &CI);
901 const TargetRegisterClass *SuperRC =
1043 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI);
1097 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI);
1148 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI);
1266 const TargetRegisterClass *
1307 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI);
1390 const auto *CarryRC = TRI->getRegClass(AMDGPU::SReg_1_XEXECRegClassID);
lib/Target/AMDGPU/SILowerControlFlow.cpp 85 const TargetRegisterClass *BoolRC = nullptr;
lib/Target/AMDGPU/SILowerSGPRSpills.cpp 102 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
135 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
208 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
lib/Target/AMDGPU/SIMachineFunctionInfo.cpp 343 const TargetRegisterClass &RC =
lib/Target/AMDGPU/SIMachineFunctionInfo.h 662 std::pair<const ArgDescriptor *, const TargetRegisterClass *>
lib/Target/AMDGPU/SIRegisterInfo.cpp 424 const TargetRegisterClass *SIRegisterInfo::getPointerRegClass(
637 const TargetRegisterClass *RC = getRegClassForReg(MF->getRegInfo(), ValueReg);
777 const TargetRegisterClass *RC = getPhysRegClass(SuperReg);
889 const TargetRegisterClass *RC = getPhysRegClass(SuperReg);
1244 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
1247 static const TargetRegisterClass *const BaseClasses[] = {
1274 for (const TargetRegisterClass *BaseClass : BaseClasses) {
1284 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
1311 bool SIRegisterInfo::hasAGPRs(const TargetRegisterClass *RC) const {
1336 const TargetRegisterClass *SIRegisterInfo::getEquivalentVGPRClass(
1337 const TargetRegisterClass *SRC) const {
1362 const TargetRegisterClass *SIRegisterInfo::getEquivalentAGPRClass(
1363 const TargetRegisterClass *SRC) const {
1380 const TargetRegisterClass *SIRegisterInfo::getEquivalentSGPRClass(
1381 const TargetRegisterClass *VRC) const {
1404 const TargetRegisterClass *SIRegisterInfo::getSubRegClass(
1405 const TargetRegisterClass *RC, unsigned SubIdx) const {
1478 const TargetRegisterClass *DefRC,
1480 const TargetRegisterClass *SrcRC,
1506 const TargetRegisterClass *RC,
1515 ArrayRef<int16_t> SIRegisterInfo::getRegSplitParts(const TargetRegisterClass *RC,
1689 const TargetRegisterClass*
1700 const TargetRegisterClass * RC = getRegClassForReg(MRI, Reg);
1707 const TargetRegisterClass * RC = getRegClassForReg(MRI, Reg);
1713 const TargetRegisterClass *SrcRC,
1715 const TargetRegisterClass *DstRC,
1717 const TargetRegisterClass *NewRC,
1733 unsigned SIRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
1775 const TargetRegisterClass *
1833 const TargetRegisterClass *
1840 const TargetRegisterClass *RC = RCOrRB.get<const TargetRegisterClass*>();
1840 const TargetRegisterClass *RC = RCOrRB.get<const TargetRegisterClass*>();
1848 const TargetRegisterClass *
lib/Target/AMDGPU/SIRegisterInfo.h 99 const TargetRegisterClass *getPointerRegClass(
126 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
129 bool isSGPRClass(const TargetRegisterClass *RC) const {
139 const TargetRegisterClass *RC;
148 bool hasVGPRs(const TargetRegisterClass *RC) const;
151 bool hasAGPRs(const TargetRegisterClass *RC) const;
154 bool hasVectorRegisters(const TargetRegisterClass *RC) const {
159 const TargetRegisterClass *getEquivalentVGPRClass(
160 const TargetRegisterClass *SRC) const;
163 const TargetRegisterClass *getEquivalentAGPRClass(
164 const TargetRegisterClass *SRC) const;
167 const TargetRegisterClass *getEquivalentSGPRClass(
168 const TargetRegisterClass *VRC) const;
173 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
173 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
176 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
178 const TargetRegisterClass *SrcRC,
195 const TargetRegisterClass *RC,
202 const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
211 isDivergentRegClass(const TargetRegisterClass *RC) const override {
228 ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC,
232 const TargetRegisterClass *SrcRC,
234 const TargetRegisterClass *DstRC,
236 const TargetRegisterClass *NewRC,
239 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
249 const TargetRegisterClass *
254 const TargetRegisterClass *
261 const TargetRegisterClass *
265 const TargetRegisterClass *getBoolRC() const {
270 const TargetRegisterClass *getWaveMaskRegClass() const {
277 const TargetRegisterClass *getRegClass(unsigned RCID) const;
lib/Target/AMDGPU/SIShrinkInstructions.cpp 233 const TargetRegisterClass *RC;
lib/Target/AMDGPU/SIWholeQuadMode.cpp 711 const TargetRegisterClass *BoolRC = TRI->getBoolRC();
861 const TargetRegisterClass *regClass = Register::isVirtualRegister(Reg)
lib/Target/ARC/ARCFrameLowering.cpp 442 const TargetRegisterClass *RC = &ARC::GPR32RegClass;
lib/Target/ARM/A15SDOptimizer.cpp 97 bool usesRegClass(MachineOperand &MO, const TargetRegisterClass *TRC);
133 const TargetRegisterClass *TRC) {
271 const TargetRegisterClass *TRC =
lib/Target/ARM/ARMBaseInstrInfo.cpp 2250 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
2436 const TargetRegisterClass *RegClass;
lib/Target/ARM/ARMBaseRegisterInfo.cpp 210 const TargetRegisterClass &RC = ARM::GPRPairRegClass;
227 const TargetRegisterClass *
228 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
230 const TargetRegisterClass *Super = RC;
231 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
250 const TargetRegisterClass *
256 const TargetRegisterClass *
257 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
264 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
814 const TargetRegisterClass *RegClass =
837 const TargetRegisterClass *SrcRC,
839 const TargetRegisterClass *DstRC,
841 const TargetRegisterClass *NewRC,
lib/Target/ARM/ARMBaseRegisterInfo.h 139 const TargetRegisterClass *
142 const TargetRegisterClass *
143 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
145 const TargetRegisterClass *
146 getLargestLegalSuperClass(const TargetRegisterClass *RC,
149 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
207 const TargetRegisterClass *SrcRC,
209 const TargetRegisterClass *DstRC,
211 const TargetRegisterClass *NewRC,
lib/Target/ARM/ARMFastISel.cpp 140 const TargetRegisterClass *RC,
143 const TargetRegisterClass *RC,
147 const TargetRegisterClass *RC,
151 const TargetRegisterClass *RC,
302 const TargetRegisterClass *RC,
324 const TargetRegisterClass *RC,
352 const TargetRegisterClass *RC,
378 const TargetRegisterClass *RC,
473 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
489 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass :
546 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
675 const TargetRegisterClass* RC = TLI.getRegClassFor(VT);
849 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
921 const TargetRegisterClass *RC;
1485 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass
1657 const TargetRegisterClass *RC;
2054 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT);
2074 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT);
2158 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg);
2494 const TargetRegisterClass *RC = isThumb2 ? &ARM::tGPRRegClass
2621 static const TargetRegisterClass *RCTbl[2][2] = {
2686 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr];
3055 const TargetRegisterClass *RC = &ARM::rGPRRegClass;
lib/Target/ARM/ARMFrameLowering.cpp 1533 const TargetRegisterClass *RegClass = TII.getRegClass(MCID, i, TRI, MF);
2118 const TargetRegisterClass &RC = ARM::GPRRegClass;
lib/Target/ARM/ARMISelLowering.cpp 1472 std::pair<const TargetRegisterClass *, uint8_t>
1475 const TargetRegisterClass *RRC = nullptr;
1691 const TargetRegisterClass *
3840 const TargetRegisterClass *RC;
3913 const TargetRegisterClass *RC =
4051 const TargetRegisterClass *RC;
9359 const TargetRegisterClass *TRC = isThumb ? &ARM::tGPRRegClass
9473 const TargetRegisterClass *TRC = Subtarget->isThumb() ? &ARM::tGPRRegClass
10026 const TargetRegisterClass *TRC = nullptr;
10027 const TargetRegisterClass *VecTRC = nullptr;
15673 using RCPair = std::pair<unsigned, const TargetRegisterClass *>;
17107 const TargetRegisterClass *RC = nullptr;
lib/Target/ARM/ARMISelLowering.h 428 std::pair<unsigned, const TargetRegisterClass *>
479 const TargetRegisterClass *
632 std::pair<const TargetRegisterClass *, uint8_t>
lib/Target/ARM/ARMInstructionSelector.cpp 184 static const TargetRegisterClass *guessRegClass(unsigned Reg,
217 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI);
1162 const TargetRegisterClass *RC = guessRegClass(DstReg, MRI, TRI, RBI);
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 167 unsigned findFreeReg(const TargetRegisterClass &RegClass);
581 unsigned ARMLoadStoreOpt::findFreeReg(const TargetRegisterClass &RegClass) {
2323 const TargetRegisterClass *TRC = TII->getRegClass(MCID, 0, TRI, *MF);
lib/Target/ARM/ARMRegisterBankInfo.cpp 176 const TargetRegisterClass &RC) const {
lib/Target/ARM/ARMRegisterBankInfo.h 36 getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
lib/Target/ARM/Thumb2InstrInfo.cpp 474 const TargetRegisterClass *RegClass =
lib/Target/ARM/ThumbRegisterInfo.cpp 42 const TargetRegisterClass *
43 ThumbRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
53 const TargetRegisterClass *
lib/Target/ARM/ThumbRegisterInfo.h 29 const TargetRegisterClass *
30 getLargestLegalSuperClass(const TargetRegisterClass *RC,
33 const TargetRegisterClass *
lib/Target/AVR/AVRAsmPrinter.cpp 111 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg);
lib/Target/AVR/AVRISelLowering.cpp 1071 const TargetRegisterClass *RC;
1439 const TargetRegisterClass *RC;
1851 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/AVR/AVRISelLowering.h 118 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/AVR/AVRRegisterInfo.cpp 82 const TargetRegisterClass *
83 AVRRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
258 const TargetRegisterClass *
277 const TargetRegisterClass *SrcRC,
279 const TargetRegisterClass *DstRC,
281 const TargetRegisterClass *NewRC,
lib/Target/AVR/AVRRegisterInfo.h 35 const TargetRegisterClass *
36 getLargestLegalSuperClass(const TargetRegisterClass *RC,
46 const TargetRegisterClass *
59 const TargetRegisterClass *SrcRC,
61 const TargetRegisterClass *DstRC,
63 const TargetRegisterClass *NewRC,
lib/Target/BPF/BPFISelLowering.cpp 174 std::pair<unsigned, const TargetRegisterClass *>
567 const TargetRegisterClass *RC = getRegClassFor(MVT::i64);
lib/Target/BPF/BPFISelLowering.h 49 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/Hexagon/BitTracker.cpp 339 const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub);
360 const TargetRegisterClass *C = MRI.getRegClass(RR.Reg);
716 const TargetRegisterClass &PC = *TRI.getMinimalPhysRegClass(Reg);
lib/Target/Hexagon/BitTracker.h 466 virtual bool track(const TargetRegisterClass *RC) const { return true; }
480 virtual const TargetRegisterClass&
481 composeWithSubRegIndex(const TargetRegisterClass &RC, unsigned Idx) const {
lib/Target/Hexagon/HexagonBitSimplify.cpp 225 static const TargetRegisterClass *getFinalVRegClass(
406 const TargetRegisterClass *RC = MRI.getRegClass(RR.Reg);
894 const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass(
1260 const TargetRegisterClass *RC = HBS::getFinalVRegClass(RR, MRI);
1344 const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI);
1382 unsigned genTfrConst(const TargetRegisterClass *RC, int64_t C,
1410 unsigned ConstGeneration::genTfrConst(const TargetRegisterClass *RC, int64_t C,
1685 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg);
1695 const TargetRegisterClass &RC = *MRI.getRegClass(RD.Reg);
2342 const TargetRegisterClass *TC = MRI.getRegClass(V.RefI.Reg);
2402 const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI);
2584 const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI);
2728 const TargetRegisterClass *FRC = HBS::getFinalVRegClass(RD, MRI);
3070 const TargetRegisterClass *PhiRC = MRI->getRegClass(NewPredR);
3082 const TargetRegisterClass *RC = MRI->getRegClass(DR);
3282 const TargetRegisterClass *RC = MRI->getRegClass(G.Inp.Reg);
lib/Target/Hexagon/HexagonBitTracker.cpp 92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
125 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg))
132 const TargetRegisterClass &HexagonEvaluator::composeWithSubRegIndex(
133 const TargetRegisterClass &RC, unsigned Idx) const {
lib/Target/Hexagon/HexagonBitTracker.h 43 const TargetRegisterClass &composeWithSubRegIndex(
44 const TargetRegisterClass &RC, unsigned Idx) const override;
lib/Target/Hexagon/HexagonBlockRanges.cpp 224 for (const TargetRegisterClass *RC : TRI.regclasses()) {
lib/Target/Hexagon/HexagonConstPropagation.cpp 1944 const TargetRegisterClass &DefRC = *MRI->getRegClass(DefR.Reg);
2200 const TargetRegisterClass *RC = MRI->getRegClass(R.Reg);
2352 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
2857 const TargetRegisterClass *RC = MRI->getRegClass(R);
2868 const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
2886 const TargetRegisterClass *NewRC;
2982 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3011 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3048 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
3080 const TargetRegisterClass *RC = MRI->getRegClass(DefR.Reg);
lib/Target/Hexagon/HexagonCopyToCombine.cpp 588 const TargetRegisterClass *SuperRC = nullptr;
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 698 const TargetRegisterClass *RC = MRI->getRegClass(R);
841 const TargetRegisterClass *RC = MRI->getRegClass(DR);
999 const TargetRegisterClass *RC = MRI->getRegClass(DefR);
lib/Target/Hexagon/HexagonExpandCondsets.cpp 585 const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
593 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(PhysS);
1096 const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);
lib/Target/Hexagon/HexagonFrameLowering.cpp 1270 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1334 const TargetRegisterClass *RC = HRI.getMinimalPhysRegClass(Reg);
1396 const HexagonRegisterInfo &HRI, const TargetRegisterClass *RC) {
1516 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(S->Reg);
1528 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(R);
1953 SetVector<const TargetRegisterClass*> SpillRCs;
1980 const TargetRegisterClass *RC) const {
2025 const TargetRegisterClass *RC = nullptr;
lib/Target/Hexagon/HexagonFrameLowering.h 161 const TargetRegisterClass *RC) const;
lib/Target/Hexagon/HexagonGenInsert.cpp 526 bool isIntClass(const TargetRegisterClass *RC) const;
640 inline bool HexagonGenInsert::isIntClass(const TargetRegisterClass *RC) const {
681 const TargetRegisterClass *DstRC = MRI->getRegClass(DstR);
682 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcR);
683 const TargetRegisterClass *InsRC = MRI->getRegClass(InsR);
1401 const TargetRegisterClass *RC = MRI->getRegClass(VR);
lib/Target/Hexagon/HexagonGenPredicate.cpp 138 const TargetRegisterClass *RC = MRI->getRegClass(R);
267 const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
334 const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
420 const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
434 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R);
454 const TargetRegisterClass *PredRC = &Hexagon::PredRegsRegClass;
lib/Target/Hexagon/HexagonHardwareLoops.cpp 894 const TargetRegisterClass *RC = MRI->getRegClass(R);
899 const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
1588 const TargetRegisterClass *RC = MRI->getRegClass(R);
1907 const TargetRegisterClass *RC = MRI->getRegClass(PR);
lib/Target/Hexagon/HexagonISelLowering.cpp 738 const TargetRegisterClass *RC = getRegClassFor(RegVT);
2994 std::pair<unsigned, const TargetRegisterClass*>
3202 std::pair<const TargetRegisterClass*, uint8_t>
lib/Target/Hexagon/HexagonISelLowering.h 268 std::pair<unsigned, const TargetRegisterClass *>
460 std::pair<const TargetRegisterClass*, uint8_t>
lib/Target/Hexagon/HexagonInstrInfo.cpp 1626 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1985 const TargetRegisterClass *TRC;
lib/Target/Hexagon/HexagonPeephole.cpp 241 const TargetRegisterClass *RC0 = MRI->getRegClass(Reg0);
lib/Target/Hexagon/HexagonRegisterInfo.cpp 56 const TargetRegisterClass *RC) const {
236 const TargetRegisterClass *SrcRC, unsigned SubReg,
237 const TargetRegisterClass *DstRC, unsigned DstSubReg,
238 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const {
309 const TargetRegisterClass &RC, unsigned GenIdx) const {
326 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses())
337 const TargetRegisterClass *
lib/Target/Hexagon/HexagonRegisterInfo.h 63 bool shouldCoalesce(MachineInstr *MI, const TargetRegisterClass *SrcRC,
64 unsigned SubReg, const TargetRegisterClass *DstRC, unsigned DstSubReg,
65 const TargetRegisterClass *NewRC, LiveIntervals &LIS) const override;
73 unsigned getHexagonSubRegIndex(const TargetRegisterClass &RC,
77 const TargetRegisterClass *RC) const;
81 const TargetRegisterClass *
lib/Target/Hexagon/HexagonSplitDouble.cpp 82 static const TargetRegisterClass *const DoubleRC;
129 const TargetRegisterClass *const HexagonSplitDoubleRegs::DoubleRC =
676 const TargetRegisterClass *RC = MRI->getRegClass(UpdOp.getReg());
815 const TargetRegisterClass *IntRC = &IntRegsRegClass;
924 const TargetRegisterClass *IntRC = &IntRegsRegClass;
1129 const TargetRegisterClass *IntRC = &Hexagon::IntRegsRegClass;
lib/Target/Hexagon/HexagonStoreWidening.cpp 443 const TargetRegisterClass *RC = TII->getRegClass(TfrD, 0, TRI, *MF);
lib/Target/Hexagon/HexagonVExtract.cpp 124 const auto &VecRC = *MRI.getRegClass(VecR);
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 353 const TargetRegisterClass *NewRC) {
657 const TargetRegisterClass *PacketRC = HII->getRegClass(MCID, 0, HRI, MF);
700 const TargetRegisterClass* predRegClass = nullptr;
870 const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF);
1419 const TargetRegisterClass *RC = nullptr;
lib/Target/Hexagon/HexagonVLIWPacketizer.h 136 bool isNewifiable(const MachineInstr &MI, const TargetRegisterClass *NewRC);
lib/Target/Hexagon/RDFCopy.cpp 123 const TargetRegisterClass &RC = *TRI.getMinimalPhysRegClass(RR.Reg);
lib/Target/Hexagon/RDFRegisters.cpp 33 for (const TargetRegisterClass *RC : TRI.regclasses()) {
66 if (const TargetRegisterClass *RC = RegInfos[F].RegClass)
171 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass;
lib/Target/Hexagon/RDFRegisters.h 136 const TargetRegisterClass *RegClass = nullptr;
lib/Target/Lanai/LanaiISelLowering.cpp 235 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/Lanai/LanaiISelLowering.h 95 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/Lanai/LanaiInstrInfo.cpp 508 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
lib/Target/MSP430/MSP430ISelLowering.cpp 378 std::pair<unsigned, const TargetRegisterClass *>
1419 const TargetRegisterClass * RC;
lib/Target/MSP430/MSP430ISelLowering.h 105 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/MSP430/MSP430RegisterInfo.cpp 96 const TargetRegisterClass *
lib/Target/MSP430/MSP430RegisterInfo.h 31 const TargetRegisterClass*
lib/Target/Mips/Mips16ISelDAGToDAG.cpp 76 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
lib/Target/Mips/Mips16RegisterInfo.cpp 69 const TargetRegisterClass *
lib/Target/Mips/Mips16RegisterInfo.h 37 const TargetRegisterClass *intRegClass(unsigned Size) const override;
lib/Target/Mips/MipsFastISel.cpp 207 unsigned materialize32BitInt(int64_t Imm, const TargetRegisterClass *RC);
230 const TargetRegisterClass *RC,
236 unsigned fastEmitInst_riir(uint64_t inst, const TargetRegisterClass *RC,
359 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
365 const TargetRegisterClass *RC) {
394 const TargetRegisterClass *RC = &Mips::FGR32RegClass;
400 const TargetRegisterClass *RC = &Mips::AFGR64RegClass;
415 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
437 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
1031 const TargetRegisterClass *RC;
1343 const TargetRegisterClass *RC;
1345 AllocatedReg(const TargetRegisterClass *RC, unsigned Reg)
2126 const TargetRegisterClass *RC,
lib/Target/Mips/MipsISelLowering.cpp 1256 addLiveIn(MachineFunction &MF, unsigned PReg, const TargetRegisterClass *RC)
1556 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1575 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1577 const TargetRegisterClass *RCp =
1732 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8));
1784 const TargetRegisterClass *RC = getRegClassFor(MVT::i32);
1786 const TargetRegisterClass *RCp =
3525 const TargetRegisterClass *RC = getRegClassFor(RegVT);
3875 std::pair<unsigned, const TargetRegisterClass *> MipsTargetLowering::
3879 const TargetRegisterClass *RC;
3952 std::pair<unsigned, const TargetRegisterClass *>
4009 std::pair<unsigned, const TargetRegisterClass *> R;
4211 const TargetRegisterClass *RC = getRegClassFor(RegTy);
4330 const TargetRegisterClass *RC = getRegClassFor(RegTy);
lib/Target/Mips/MipsISelLowering.h 639 std::pair<unsigned, const TargetRegisterClass *>
642 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/Mips/MipsInstructionSelector.cpp 45 const TargetRegisterClass *
96 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
113 const TargetRegisterClass *MipsInstructionSelector::getRegClassForTypeOnBank(
374 const TargetRegisterClass *DefRC = nullptr;
lib/Target/Mips/MipsMachineFunction.cpp 31 static const TargetRegisterClass &getGlobalBaseRegClass(MachineFunction &MF) {
72 const TargetRegisterClass *RC;
153 const TargetRegisterClass &RC =
168 const TargetRegisterClass &RC = Mips::GPR32RegClass;
192 int MipsFunctionInfo::getMoveF64ViaSpillFI(const TargetRegisterClass *RC) {
lib/Target/Mips/MipsMachineFunction.h 79 int getMoveF64ViaSpillFI(const TargetRegisterClass *RC);
lib/Target/Mips/MipsOptimizePICCall.cpp 139 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
lib/Target/Mips/MipsRegisterBankInfo.cpp 80 const TargetRegisterClass &RC) const {
lib/Target/Mips/MipsRegisterBankInfo.h 36 getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
lib/Target/Mips/MipsRegisterInfo.cpp 46 const TargetRegisterClass *
67 MipsRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
lib/Target/Mips/MipsRegisterInfo.h 47 const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
50 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
75 virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
lib/Target/Mips/MipsSEFrameLowering.cpp 173 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
188 const TargetRegisterClass *RC = RegInfo.intRegClass(4);
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize);
262 const TargetRegisterClass *DstRC = RegInfo.getMinimalPhysRegClass(Dst);
264 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize);
317 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
318 const TargetRegisterClass *RC2 =
383 const TargetRegisterClass *RC =
385 const TargetRegisterClass *RC2 = &Mips::GPR32RegClass;
421 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ?
591 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
719 const TargetRegisterClass *RC =
754 const TargetRegisterClass *PtrRC = &Mips::GPR32RegClass;
834 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
895 const TargetRegisterClass &RC = STI.isGP64bit() ?
912 const TargetRegisterClass &RC =
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 1187 const TargetRegisterClass *RC =
1256 const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
lib/Target/Mips/MipsSEISelLowering.cpp 307 const TargetRegisterClass *
317 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
371 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
3038 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3107 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
3336 const TargetRegisterClass *VecRC = nullptr;
3338 const TargetRegisterClass *GPRRC =
3522 const TargetRegisterClass *RC =
3574 const TargetRegisterClass *RC =
3668 const TargetRegisterClass *GPRRC =
3772 const TargetRegisterClass *GPRRC =
3821 const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
3850 const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
lib/Target/Mips/MipsSEISelLowering.h 36 void addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC);
41 const TargetRegisterClass *RC);
60 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
lib/Target/Mips/MipsSEInstrInfo.cpp 618 const TargetRegisterClass *RC = STI.isABI_N64() ?
lib/Target/Mips/MipsSERegisterInfo.cpp 53 const TargetRegisterClass *
222 const TargetRegisterClass *PtrRC =
lib/Target/Mips/MipsSERegisterInfo.h 30 const TargetRegisterClass *intRegClass(unsigned Size) const override;
lib/Target/NVPTX/NVPTXAsmPrinter.cpp 286 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
579 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
1655 const TargetRegisterClass *RC = MRI->getRegClass(vr);
1674 const TargetRegisterClass *RC = TRI->getRegClass(i);
lib/Target/NVPTX/NVPTXAsmPrinter.h 252 typedef DenseMap<const TargetRegisterClass *, VRegMap> VRegRCMap;
lib/Target/NVPTX/NVPTXISelLowering.cpp 4274 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/NVPTX/NVPTXISelLowering.h 479 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/NVPTX/NVPTXInstrInfo.cpp 37 const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
lib/Target/NVPTX/NVPTXRegisterInfo.cpp 28 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) {
72 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) {
lib/Target/NVPTX/NVPTXRegisterInfo.h 59 std::string getNVPTXRegClassName(const TargetRegisterClass *RC);
60 std::string getNVPTXRegClassStr(const TargetRegisterClass *RC);
lib/Target/PowerPC/PPCFastISel.cpp 115 const TargetRegisterClass *RC,
119 const TargetRegisterClass *RC,
122 const TargetRegisterClass *RC,
148 bool isVSFRCRegClass(const TargetRegisterClass *RC) const {
151 bool isVSSRCRegClass(const TargetRegisterClass *RC) const {
154 unsigned copyRegToRegClass(const TargetRegisterClass *ToRC,
166 const TargetRegisterClass *RC, bool IsZExt = true,
179 const TargetRegisterClass *RC);
181 const TargetRegisterClass *RC);
455 const TargetRegisterClass *RC,
468 const TargetRegisterClass *UseRC =
612 const TargetRegisterClass *RC =
629 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg);
1053 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1132 const TargetRegisterClass *RC = &PPC::F8RCRegClass;
1176 const TargetRegisterClass *RC =
1217 const TargetRegisterClass *InRC = MRI.getRegClass(SrcReg);
1281 const TargetRegisterClass *RC =
1443 const TargetRegisterClass *RC =
1455 const TargetRegisterClass *RC =
1521 const TargetRegisterClass *CpyRC = TLI.getRegClassFor(CopyVT);
1765 const TargetRegisterClass *RC =
1774 const TargetRegisterClass *RC =
1922 const TargetRegisterClass *RC =
2003 const TargetRegisterClass *RC;
2060 const TargetRegisterClass *RC = &PPC::G8RC_and_G8RC_NOX0RegClass;
2112 const TargetRegisterClass *RC) {
2144 const TargetRegisterClass *RC) {
2214 const TargetRegisterClass *RC =
2396 const TargetRegisterClass *RC = ((VT == MVT::i64) ? &PPC::G8RCRegClass :
2416 const TargetRegisterClass *RC,
2424 const TargetRegisterClass *UseRC =
2436 const TargetRegisterClass* RC,
2438 const TargetRegisterClass *UseRC =
2449 const TargetRegisterClass* RC,
2452 const TargetRegisterClass *UseRC =
lib/Target/PowerPC/PPCFrameLowering.cpp 2107 const TargetRegisterClass &GPRC = PPC::GPRCRegClass;
2108 const TargetRegisterClass &G8RC = PPC::G8RCRegClass;
2109 const TargetRegisterClass &RC = Subtarget.isPPC64() ? G8RC : GPRC;
2260 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
2418 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 321 const TargetRegisterClass *TRC = TRI->getPointerRegClass(*MF, /*Kind=*/1);
lib/Target/PowerPC/PPCISelLowering.cpp 3482 const TargetRegisterClass *RC;
4023 const TargetRegisterClass *RC;
10458 const TargetRegisterClass *RC =
10460 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
10623 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
10677 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
10764 const TargetRegisterClass *RC =
11273 const TargetRegisterClass *RC =
11275 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
11529 const TargetRegisterClass *RC = RegInfo.getRegClass(SrcReg);
14305 std::pair<unsigned, const TargetRegisterClass *>
14366 std::pair<unsigned, const TargetRegisterClass *> R =
15035 const TargetRegisterClass *RC = nullptr;
lib/Target/PowerPC/PPCISelLowering.h 788 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/PowerPC/PPCInstrInfo.cpp 769 const TargetRegisterClass *RC =
802 const TargetRegisterClass *RC =
863 const TargetRegisterClass *FirstRC =
1028 const TargetRegisterClass *RC)
1115 const TargetRegisterClass *RC) const {
1201 const TargetRegisterClass *RC,
1257 const TargetRegisterClass *RC,
1562 const TargetRegisterClass *RCs[] =
1570 const TargetRegisterClass *RC = RCs[c];
1577 for (TargetRegisterClass::iterator I = RC->begin(),
3838 const TargetRegisterClass *NewRC =
3855 const TargetRegisterClass *
3856 PPCInstrInfo::updatedRC(const TargetRegisterClass *RC) const {
lib/Target/PowerPC/PPCInstrInfo.h 117 int FrameIdx, const TargetRegisterClass *RC,
121 const TargetRegisterClass *RC,
299 const TargetRegisterClass *RC = nullptr) const;
302 const TargetRegisterClass *RC = nullptr) const;
403 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
403 const TargetRegisterClass *updatedRC(const TargetRegisterClass *RC) const;
lib/Target/PowerPC/PPCMIPeephole.cpp 761 const TargetRegisterClass *TRC = MI.getOpcode() == PPC::ADD8
lib/Target/PowerPC/PPCRegisterInfo.cpp 125 const TargetRegisterClass *
339 for (TargetRegisterClass::iterator I = PPC::VRRCRegClass.begin(),
417 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
451 const TargetRegisterClass *
452 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
527 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
528 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
654 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
655 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
699 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
700 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
743 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
744 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
822 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
823 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
871 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
897 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1093 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1094 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1095 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
lib/Target/PowerPC/PPCRegisterInfo.h 75 const TargetRegisterClass *
78 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
81 const TargetRegisterClass *
82 getLargestLegalSuperClass(const TargetRegisterClass *RC,
lib/Target/PowerPC/PPCVSXCopy.cpp 51 bool IsRegInClass(unsigned Reg, const TargetRegisterClass *RC,
99 const TargetRegisterClass *SrcRC = &PPC::VSLRCRegClass;
120 const TargetRegisterClass *DstRC = &PPC::VSLRCRegClass;
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 160 bool isRegInClass(unsigned Reg, const TargetRegisterClass *RC) {
898 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg);
lib/Target/RISCV/RISCVFrameLowering.cpp 417 const TargetRegisterClass *RC = &RISCV::GPRRegClass;
lib/Target/RISCV/RISCVISelLowering.cpp 1162 const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass;
1194 const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass;
1693 const TargetRegisterClass *RC;
1946 const TargetRegisterClass *RC = &RISCV::GPRRegClass;
2554 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/RISCV/RISCVISelLowering.h 99 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/RISCV/RISCVRegisterInfo.h 58 const TargetRegisterClass *
lib/Target/Sparc/SparcISelLowering.cpp 3254 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/Sparc/SparcISelLowering.h 92 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/Sparc/SparcInstrInfo.cpp 483 const TargetRegisterClass *PtrRC =
lib/Target/Sparc/SparcRegisterInfo.cpp 104 const TargetRegisterClass*
lib/Target/Sparc/SparcRegisterInfo.h 34 const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
lib/Target/SystemZ/SystemZHazardRecognizer.cpp 123 const TargetRegisterClass *RC = TII->getRegClass(MID, OpIdx, TRI, MF);
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 1665 const TargetRegisterClass *TRC =
lib/Target/SystemZ/SystemZISelLowering.cpp 1055 static std::pair<unsigned, const TargetRegisterClass *>
1056 parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC,
1069 std::pair<unsigned, const TargetRegisterClass *>
1323 const TargetRegisterClass *RC;
6827 const TargetRegisterClass *RC = (BitSize <= 32 ?
6945 const TargetRegisterClass *RC = (BitSize <= 32 ?
7058 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
7250 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
7415 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
7520 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
7803 const TargetRegisterClass *
lib/Target/SystemZ/SystemZISelLowering.h 422 std::pair<unsigned, const TargetRegisterClass *>
658 const TargetRegisterClass *getRepRegClassFor(MVT VT) const override;
lib/Target/SystemZ/SystemZInstrInfo.cpp 546 const TargetRegisterClass *RC =
573 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
1458 void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
lib/Target/SystemZ/SystemZInstrInfo.h 288 void getLoadStoreOpcodes(const TargetRegisterClass *RC,
lib/Target/SystemZ/SystemZRegisterInfo.cpp 29 static const TargetRegisterClass *getRC32(MachineOperand &MO,
32 const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
61 const TargetRegisterClass *RC,
108 const TargetRegisterClass *RC =
337 const TargetRegisterClass *SrcRC,
339 const TargetRegisterClass *DstRC,
341 const TargetRegisterClass *NewRC,
413 const TargetRegisterClass *
414 SystemZRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
lib/Target/SystemZ/SystemZRegisterInfo.h 49 const TargetRegisterClass *
58 const TargetRegisterClass *
59 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
88 const TargetRegisterClass *SrcRC,
90 const TargetRegisterClass *DstRC,
92 const TargetRegisterClass *NewRC,
lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp 59 const TargetRegisterClass *TRC = MRI->getRegClass(RegNo);
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 82 static unsigned getDropOpcode(const TargetRegisterClass *RC) {
99 static unsigned getLocalGetOpcode(const TargetRegisterClass *RC) {
116 static unsigned getLocalSetOpcode(const TargetRegisterClass *RC) {
133 static unsigned getLocalTeeOpcode(const TargetRegisterClass *RC) {
150 static MVT typeForRegClass(const TargetRegisterClass *RC) {
242 const TargetRegisterClass *RC = MRI.getRegClass(OldReg);
275 const TargetRegisterClass *RC = MRI.getRegClass(OldReg);
347 const TargetRegisterClass *RC = MRI.getRegClass(OldReg);
lib/Target/WebAssembly/WebAssemblyFastISel.cpp 660 const TargetRegisterClass *RC;
907 const TargetRegisterClass *RC;
1170 const TargetRegisterClass *RC;
lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp 172 const TargetRegisterClass *PtrRC =
245 const TargetRegisterClass *PtrRC =
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 474 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/WebAssembly/WebAssemblyISelLowering.h 54 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp 62 const TargetRegisterClass *RC =
lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp 182 static wasm::ValType getType(const TargetRegisterClass *RC) {
lib/Target/WebAssembly/WebAssemblyPeephole.cpp 97 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
lib/Target/WebAssembly/WebAssemblyRegColoring.cpp 140 const TargetRegisterClass *RC = MRI->getRegClass(Old);
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg());
459 static unsigned getTeeOpcode(const TargetRegisterClass *RC) {
609 const auto *RegClass = MRI.getRegClass(Reg);
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 118 const TargetRegisterClass *PtrRC =
143 const TargetRegisterClass *
lib/Target/WebAssembly/WebAssemblyRegisterInfo.h 44 const TargetRegisterClass *
lib/Target/WebAssembly/WebAssemblyReplacePhysRegs.cpp 86 const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(PReg);
lib/Target/X86/X86CmovConversion.cpp 755 const TargetRegisterClass *RC = MRI->getRegClass(MI.getOperand(0).getReg());
lib/Target/X86/X86DomainReassignment.cpp 44 static bool isGPR(const TargetRegisterClass *RC) {
51 static bool isMask(const TargetRegisterClass *RC,
56 static RegDomain getDomain(const TargetRegisterClass *RC,
66 static const TargetRegisterClass *getDstRC(const TargetRegisterClass *SrcRC,
66 static const TargetRegisterClass *getDstRC(const TargetRegisterClass *SrcRC,
lib/Target/X86/X86FastISel.cpp 131 const TargetRegisterClass *RC);
178 const TargetRegisterClass *RC, unsigned Op0,
467 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
770 const TargetRegisterClass *RC = nullptr;
1247 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
1781 const TargetRegisterClass *RC = nullptr;
1865 const TargetRegisterClass *RC;
2024 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2199 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2204 const TargetRegisterClass *VR128X = &X86::VR128XRegClass;
2205 const TargetRegisterClass *VK1 = &X86::VK1RegClass;
2231 const TargetRegisterClass *VR128 = &X86::VR128RegClass;
2264 const TargetRegisterClass *VR128 = &X86::VR128RegClass;
2351 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2379 const TargetRegisterClass *RC = TLI.getRegClassFor(RetVT);
2449 const TargetRegisterClass *RC = TLI.getRegClassFor(DstVT);
2470 const TargetRegisterClass *RC) {
2625 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::v8i16);
2680 const TargetRegisterClass *RC = nullptr;
2837 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
3132 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
3884 const TargetRegisterClass *RC = TLI.getRegClassFor(TLI.getPointerTy(DL));
3975 const TargetRegisterClass *RC,
lib/Target/X86/X86FixupSetCC.cpp 136 const TargetRegisterClass *RC = MF.getSubtarget<X86Subtarget>().is64Bit()
lib/Target/X86/X86FlagsCopyLowering.cpp 94 const TargetRegisterClass *PromoteRC;
lib/Target/X86/X86FrameLowering.cpp 153 const TargetRegisterClass &AvailableRegs = *TRI->getGPRsForTailCall(*MF);
586 const TargetRegisterClass *RegClass = &X86::GR64RegClass;
2041 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2124 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
2203 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
lib/Target/X86/X86ISelLowering.cpp 2253 std::pair<const TargetRegisterClass *, uint8_t>
2256 const TargetRegisterClass *RRC = nullptr;
2750 const TargetRegisterClass *RC = &X86::GR32RegClass;
3233 const TargetRegisterClass *RC;
22244 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
29213 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
29295 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64);
29296 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32);
30049 const TargetRegisterClass *AddrRegClass =
30436 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
30486 const TargetRegisterClass *RC = MRI.getRegClass(DstReg);
30540 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
30637 const TargetRegisterClass *PtrRC = getRegClassFor(PVT);
30816 const TargetRegisterClass *RC =
30904 const TargetRegisterClass *TRC =
31378 const TargetRegisterClass *AddrRegClass = getRegClassFor(SPTy);
45757 static bool isGRClass(const TargetRegisterClass &RC) {
45767 static bool isFRClass(const TargetRegisterClass &RC) {
45777 static bool isVKClass(const TargetRegisterClass &RC) {
45787 std::pair<unsigned, const TargetRegisterClass *>
45972 std::pair<unsigned, const TargetRegisterClass*> Res;
46035 const TargetRegisterClass *Class = Res.second;
46046 const TargetRegisterClass *RC =
46186 const TargetRegisterClass *RC = nullptr;
lib/Target/X86/X86ISelLowering.h 992 std::pair<unsigned, const TargetRegisterClass *>
1254 std::pair<const TargetRegisterClass *, uint8_t>
lib/Target/X86/X86InstrInfo.cpp 708 const TargetRegisterClass *RC;
2844 const TargetRegisterClass *RC =
2872 const TargetRegisterClass &RC = *MRI.getRegClass(DstReg);
3061 const TargetRegisterClass *RC,
3230 const TargetRegisterClass *RC,
3238 const TargetRegisterClass *RC,
4744 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4768 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4787 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum, &RI, MF);
4900 const TargetRegisterClass *RC = getRegClass(MI.getDesc(), OpNum,
5076 const TargetRegisterClass *RC =
5407 const TargetRegisterClass *RC,
5471 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5579 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
5613 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
5662 const TargetRegisterClass *DstRC = nullptr;
6001 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
lib/Target/X86/X86InstrInfo.h 403 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
lib/Target/X86/X86InstructionSelector.cpp 108 const TargetRegisterClass *DstRC,
110 const TargetRegisterClass *SrcRC) const;
126 const TargetRegisterClass *getRegClass(LLT Ty, const RegisterBank &RB) const;
127 const TargetRegisterClass *getRegClass(LLT Ty, unsigned Reg,
167 const TargetRegisterClass *
195 const TargetRegisterClass *
202 static unsigned getSubRegIndex(const TargetRegisterClass *RC) {
215 static const TargetRegisterClass *getRegClassFromGRPhysReg(unsigned Reg) {
246 const TargetRegisterClass *SrcRC =
248 const TargetRegisterClass *DstRC = getRegClassFromGRPhysReg(DstReg);
276 const TargetRegisterClass *DstRC =
284 const TargetRegisterClass *SrcRC = getRegClassFromGRPhysReg(SrcReg);
295 const TargetRegisterClass *OldRC = MRI.getRegClassOrNull(DstReg);
682 static bool canTurnIntoCOPY(const TargetRegisterClass *DstRC,
683 const TargetRegisterClass *SrcRC) {
691 const TargetRegisterClass *DstRC, const unsigned SrcReg,
692 const TargetRegisterClass *SrcRC) const {
726 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
727 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
808 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
809 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
901 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstRB);
902 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcRB);
1215 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI);
1216 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
1254 const TargetRegisterClass *SrcRC = getRegClass(SrcTy, SrcReg, MRI);
1255 const TargetRegisterClass *DstRC = getRegClass(DstTy, DstReg, MRI);
1499 const TargetRegisterClass *RC = getRegClass(DstTy, DstReg, MRI);
1633 const TargetRegisterClass *RegRC = getRegClass(RegTy, *RegRB);
lib/Target/X86/X86RegisterBankInfo.cpp 44 const TargetRegisterClass &RC) const {
lib/Target/X86/X86RegisterBankInfo.h 68 getRegBankFromRegClass(const TargetRegisterClass &RC) const override;
lib/Target/X86/X86RegisterInfo.cpp 86 const TargetRegisterClass *
87 X86RegisterInfo::getSubClassWithSubReg(const TargetRegisterClass *RC,
98 const TargetRegisterClass *
99 X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A,
100 const TargetRegisterClass *B,
111 const TargetRegisterClass *
112 X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
127 const TargetRegisterClass *Super = RC;
128 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
178 const TargetRegisterClass *
219 bool X86RegisterInfo::shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
221 const TargetRegisterClass *SrcRC,
234 const TargetRegisterClass *
248 const TargetRegisterClass *
249 X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
260 X86RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
lib/Target/X86/X86RegisterInfo.h 64 const TargetRegisterClass *
65 getMatchingSuperRegClass(const TargetRegisterClass *A,
66 const TargetRegisterClass *B,
69 const TargetRegisterClass *
70 getSubClassWithSubReg(const TargetRegisterClass *RC,
73 const TargetRegisterClass *
74 getLargestLegalSuperClass(const TargetRegisterClass *RC,
77 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
79 const TargetRegisterClass *SrcRC,
84 const TargetRegisterClass *
91 const TargetRegisterClass *
92 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
96 const TargetRegisterClass *
99 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
lib/Target/X86/X86SpeculativeLoadHardening.cpp 154 const TargetRegisterClass *RC;
157 PredState(MachineFunction &MF, const TargetRegisterClass *RC)
839 static const TargetRegisterClass *
2254 const TargetRegisterClass *NOREXRegClasses[] = {
2260 const TargetRegisterClass *GPRRegClasses[] = {
2470 const TargetRegisterClass *AddrRC = &X86::GR64RegClass;
lib/Target/X86/X86VZeroUpper.cpp 297 for (TargetRegisterClass::iterator i = RC->begin(), e = RC->end(); i != e;
lib/Target/XCore/XCoreFrameLowering.cpp 440 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
468 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
577 const TargetRegisterClass &RC = XCore::GRRegsRegClass;
lib/Target/XCore/XCoreISelLowering.cpp 1926 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/XCore/XCoreISelLowering.h 194 std::pair<unsigned, const TargetRegisterClass *>
lib/Target/XCore/XCoreMachineFunctionInfo.cpp 38 const TargetRegisterClass &RC = XCore::GRRegsRegClass;
56 const TargetRegisterClass &RC = XCore::GRRegsRegClass;
69 const TargetRegisterClass &RC = XCore::GRRegsRegClass;
unittests/CodeGen/MachineInstrTest.cpp 50 static TargetRegisterClass *const BogusRegisterClasses[] = {nullptr};
71 getRegClassWeight(const TargetRegisterClass *RC) const override {
85 getRegClassPressureSets(const TargetRegisterClass *RC) const override {
usr/include/c++/7.4.0/initializer_list 50 typedef _E value_type;
51 typedef const _E& reference;
52 typedef const _E& const_reference;
54 typedef const _E* iterator;
55 typedef const _E* const_iterator;