reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

Overridden By

lib/Target/AMDGPU/SIISelLowering.cpp

 1371 bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {

lib/Target/X86/X86ISelLowering.cpp

45039 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const {

References

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 1182   if (TLI.isTypeDesirableForOp(Opc, VT))
 1247   if (TLI.isTypeDesirableForOp(Opc, VT))
 1296   if (TLI.isTypeDesirableForOp(Opc, VT))
 1327   if (TLI.isTypeDesirableForOp(Opc, VT))
 4287         !TLI.isTypeDesirableForOp(LogicOpcode, XVT))
 4627             TLI.isTypeDesirableForOp(ISD::AND, HalfVT) &&
 4628             TLI.isTypeDesirableForOp(ISD::SRL, HalfVT) &&
 7207       TLI.isTypeDesirableForOp(ISD::AND, TruncVT)) {
 7823     if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
10627       TLI.isTypeDesirableForOp(ISD::SHL, VT)) {
10701   if (!LegalTypes || TLI.isTypeDesirableForOp(N0.getOpcode(), VT)) {

lib/CodeGen/SelectionDAG/TargetLowering.cpp

 1328             isTypeDesirableForOp(ISD::SHL, InnerVT)) {
 1751         if (TLO.LegalTypes() && !isTypeDesirableForOp(ISD::SRL, VT))
 3190         if (isTypeDesirableForOp(ISD::SETCC, MinVT)) {

lib/Target/AMDGPU/SIISelLowering.cpp

 1394   return TargetLowering::isTypeDesirableForOp(Op, VT);