reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
190 inline bool isUndef() const;
861 if (Op.isUndef()) 1977 if (!CanFoldNonConst && !NewCT.isUndef() && 1984 if (!CanFoldNonConst && !NewCF.isUndef() && 2093 if (N0.isUndef()) 2096 if (N1.isUndef()) 2334 if (N0.isUndef() || N1.isUndef()) 2334 if (N0.isUndef() || N1.isUndef()) 3028 if (N0.isUndef()) 3030 if (N1.isUndef()) 3178 if (N0.isUndef() || N1.isUndef()) 3178 if (N0.isUndef() || N1.isUndef()) 3302 if (N0.isUndef() || N1.isUndef()) 3302 if (N0.isUndef() || N1.isUndef()) 3323 if (N0.isUndef() || N1.isUndef()) 3323 if (N0.isUndef() || N1.isUndef()) 3597 if (N0.isUndef()) 3974 if (N0.isUndef() || N1.isUndef()) 3974 if (N0.isUndef() || N1.isUndef()) 4018 if (N0.isUndef() || N1.isUndef()) 4018 if (N0.isUndef() || N1.isUndef()) 4230 (N0.isUndef() || DAG.SignBitIsZero(N0)) && 4231 (N1.isUndef() || DAG.SignBitIsZero(N1))) { 4384 if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) 4397 if (LogicOpcode == ISD::XOR && !ShOp.isUndef()) 4567 if (N0.isUndef() || N1.isUndef()) 4567 if (N0.isUndef() || N1.isUndef()) 5609 if (!LegalOperations && (N0.isUndef() || N1.isUndef())) 5609 if (!LegalOperations && (N0.isUndef() || N1.isUndef())) 6696 assert(L->getOffset().isUndef() && "Unindexed load must have undef offset"); 6875 if (N0.isUndef() && N1.isUndef()) 6875 if (N0.isUndef() && N1.isUndef()) 6878 if (N0.isUndef()) 6880 if (N1.isUndef()) 7952 return V.isUndef() || isNullOrNullSplat(V, /*AllowUndefs*/ true); 8637 if (N1Elt.isUndef() || N2Elt.isUndef()) 8637 if (N1Elt.isUndef() || N2Elt.isUndef()) 8951 if (Op.isUndef()) { 10379 if (N0.isUndef()) 10509 if (N0.isUndef()) 10525 if (N0.isUndef()) 10731 if (!X.isUndef()) { 10954 if (N0.isUndef()) 11168 if (Op.isUndef() || ISD::isBuildVectorOfConstantSDNodes(Op.getNode()) || 11271 if (Op.isUndef()) continue; 11296 if (Op.isUndef()) { 12829 if (N0.isUndef()) 12890 if (N0.isUndef()) 12977 if (N0.isUndef()) 12992 if (N0.isUndef()) 14000 if (LD->getBasePtr().isUndef() || Offset != 0) 14317 if (!Origin->getOffset().isUndef()) 15276 if (BasePtr.getBase().isUndef()) 16151 if (Value.isUndef() && ST->isUnindexed()) 16245 !ST1->getBasePtr().isUndef()) { 16609 if (InVec.isUndef() && TLI.shouldSplatInsEltVarIndex(VT)) { 16654 } else if (InVec.isUndef()) { 16799 if (VecOp.isUndef()) 17079 if (In.isUndef()) continue; 17134 Cast.isUndef()) && "Invalid cast opcode"); 17136 if (Cast.isUndef()) 17291 if (Op.isUndef()) 17393 if (Op.isUndef()) 17660 assert(!V.isUndef() && "Splat of undef should have been handled earlier"); 17753 if (Op.isUndef()) 17783 if (Op.isUndef()) { 17800 if (ExtVec.isUndef()) { 17824 if (SV0.isUndef() || SV0 == ExtVec) { 17828 } else if (SV1.isUndef() || SV1 == ExtVec) { 17854 return Op.isUndef(); 17979 if (Op.isUndef()) 18227 if (V.isUndef()) 18370 !N0.getOperand(1).isUndef() || !N1.getOperand(1).isUndef()) 18370 !N0.getOperand(1).isUndef() || !N1.getOperand(1).isUndef()) 18429 if (NumElemsPerConcat * 2 == NumElts && N1.isUndef() && 18502 if (!N1.isUndef()) { 18545 if (!Op.isUndef() && !isa<ConstantSDNode>(Op) && !isa<ConstantFPSDNode>(Op)) 18690 if (!Shuf->getOperand(1).isUndef()) 18823 if (!Shuf0 || !Shuf->getOperand(1).isUndef()) 18854 if (N0.isUndef() && N1.isUndef()) 18854 if (N0.isUndef() && N1.isUndef()) 18871 if (N0.isUndef()) 18875 if (N1.isUndef()) { 18935 if (!V->getOperand(i).isUndef()) { 18985 (N1.isUndef() || 19002 N1.isUndef() && Level < AfterLegalizeVectorOps && 19078 bool IsSV1Undef = SV1.isUndef(); 19136 if (CurrentVec.isUndef()) { 19249 if (N1.isUndef()) 19254 if (N0.isUndef() && N1.getOpcode() == ISD::EXTRACT_SUBVECTOR && 19262 if (N0.isUndef() && N1.getOpcode() == ISD::BITCAST && 19302 if (N0.isUndef() && N1.getOpcode() == ISD::INSERT_SUBVECTOR && 19303 N1.getOperand(0).isUndef() && isNullConstant(N1.getOperand(2))) 19315 if ((N0.isUndef() || N0.getOpcode() == ISD::BITCAST) && 19321 if ((N0.isUndef() || N0SrcSVT == N1SrcSVT) && 19476 if (Elt.isUndef()) { 19565 count_if(N0->ops(), [](SDValue V) { return !V.isUndef(); }) == 1 && 19566 count_if(N1->ops(), [](SDValue V) { return !V.isUndef(); }) == 1) { 19608 LHS.getOperand(1).isUndef() && RHS.getOperand(1).isUndef() && 19608 LHS.getOperand(1).isUndef() && RHS.getOperand(1).isUndef() && 19622 if (LHS.getOpcode() == ISD::INSERT_SUBVECTOR && LHS.getOperand(0).isUndef() && 19623 RHS.getOpcode() == ISD::INSERT_SUBVECTOR && RHS.getOperand(0).isUndef() && 19646 return Op.isUndef() || 20774 if (BasePtr.getBase().isUndef()) 20872 if (BasePtr.getBase().isUndef())lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
1406 if (Node->getOperand(i).isUndef()) continue; 1821 if (V.isUndef()) 1913 if (V.isUndef()) 1956 assert(Node->getOperand(i).isUndef()); 1973 if (Node->getOperand(i).isUndef()) 1983 if (V.isUndef()) 3491 if (Tmp2.isUndef() ||lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
536 if (Arg.isUndef()) 3619 if (!N->getOperand(i).isUndef()) 4394 if (!N->getOperand(i).isUndef())lib/CodeGen/SelectionDAG/SelectionDAG.cpp
162 while (i != e && N->getOperand(i).isUndef()) 191 if (N->getOperand(i) != NotZero && !N->getOperand(i).isUndef()) 205 if (Op.isUndef()) 238 if (Op.isUndef()) 251 if (Op.isUndef()) 265 return all_of(N->op_values(), [](SDValue Op) { return Op.isUndef(); }); 281 if (AllowUndefs && Op.getOperand(i).isUndef()) { 315 bool LHSUndef = AllowUndefs && LHSOp.isUndef(); 316 bool RHSUndef = AllowUndefs && RHSOp.isUndef(); 1577 if (N1.isUndef() && N2.isUndef()) 1577 if (N1.isUndef() && N2.isUndef()) 1598 if (N1.isUndef()) 1634 bool N2Undef = N2.isUndef(); 1654 N2Undef = N2.isUndef(); 1656 if (N1.isUndef() && N2Undef) 1682 if (Splat && Splat.isUndef()) 1999 if ((N1.isUndef() || N2.isUndef()) && 1999 if ((N1.isUndef() || N2.isUndef()) && 2005 if (N1.isUndef() && N2.isUndef()) 2005 if (N1.isUndef() && N2.isUndef()) 2094 } else if (N1CFP && OpVT.isSimple() && !N2.isUndef()) { 2101 (OpVT.isFloatingPoint() && (N1.isUndef() || N2.isUndef()))) { 2101 (OpVT.isFloatingPoint() && (N1.isUndef() || N2.isUndef()))) { 2259 if (Op.isUndef()) { 4160 if (llvm::all_of(Ops, [](SDValue Op) { return Op.isUndef(); })) 4202 if (llvm::all_of(Ops, [](SDValue Op) { return Op.isUndef(); })) 4237 if (Op.isUndef()) 4482 if (Operand.isUndef()) 4487 if (Operand.isUndef()) 4493 if (Operand.isUndef()) 4779 if (Divisor.isUndef() || isNullConstant(Divisor)) 4784 [](SDValue V) { return V.isUndef() || 4865 if (!ScalarResult.isUndef() && ScalarResult.getOpcode() != ISD::Constant && 4908 return (Op.isUndef()) || (Op.getOpcode() == ISD::CONDCODE) || 4941 if (Op.isUndef()) 4967 if (!ScalarResult.isUndef() && ScalarResult.getOpcode() != ISD::Constant && 5028 if (N1.isUndef() && N2.isUndef()) 5028 if (N1.isUndef() && N2.isUndef()) 5030 if (N1.isUndef() || N2.isUndef()) 5030 if (N1.isUndef() || N2.isUndef()) 5216 if (Op.isUndef()) { 5234 if (N1.isUndef() || N2.isUndef()) 5234 if (N1.isUndef() || N2.isUndef()) 5340 if (N1.isUndef()) 5370 if (N1.isUndef()) { 5390 if (N2.isUndef()) { 5393 if (N1.isUndef()) 5513 if (N3.isUndef()) 5517 if (N2.isUndef()) 5524 if (N1.isUndef() && N2.isUndef()) 5524 if (N1.isUndef() && N2.isUndef()) 5549 if (N1.isUndef() && N2.getOpcode() == ISD::EXTRACT_SUBVECTOR && 5629 assert(!Value.isUndef()); 5777 if (Src.isUndef()) 5962 if (Src.isUndef()) 6070 if (Src.isUndef()) 6688 if (OffsetOp.isUndef()) 6740 assert((Indexed || Offset.isUndef()) && "Unindexed load with an offset!"); 6807 assert(LD->getOffset().isUndef() && "Load is already a indexed load!"); 6940 assert(ST->getOffset().isUndef() && "Store is already a indexed store!"); 7105 if (Cond.isUndef()) 7107 if (T.isUndef()) 7109 if (F.isUndef()) 7133 if (X.isUndef()) 7136 if (Y.isUndef()) 9389 if (OpVal.isUndef()) 9441 if (Op.isUndef()) { 9453 assert(getOperand(FirstDemandedIdx).isUndef() &&lib/CodeGen/SelectionDAG/TargetLowering.cpp
592 if (Op.isUndef()) 775 if (Op.isUndef()) 2059 if (isa<ConstantFPSDNode>(Elt) || Elt.isUndef() || (C && !C->isOpaque())) 2077 if (DAG.getNode(BO.getOpcode(), SDLoc(BO), EltVT, C0, C1).isUndef()) 2097 if (Op.isUndef()) { 2222 if (!DemandedElts[i] && !Ops[i].isUndef()) { 2234 if (SrcOp.isUndef()) { 2279 if (!BaseElts && !Base.isUndef()) 2329 if (Scl.isUndef()) 5375 return !N.isUndef() && !isa<ConstantFPSDNode>(N); 5384 return N.isUndef() || 5479 if (C.isUndef()) {lib/Target/AArch64/AArch64ISelLowering.cpp
6288 if (V.isUndef()) 6417 if (Entry.isUndef()) 7592 if (V.isUndef()) 7801 if (!Op0.isUndef()) { 7810 if (V.isUndef())lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
74 if (V.isUndef()) 84 if (N.isUndef()) { 2040 if (Cond.isUndef()) { 2612 if (In.isUndef())lib/Target/AMDGPU/R600ISelLowering.cpp
1166 if (!Offset.isUndef()) { 1397 if (!Offset.isUndef()) { 1701 if (NewBldVec[i].isUndef()) 1716 if (NewBldVec[i].isUndef()) 1904 if (InVal.isUndef()) 1925 } else if (InVec.isUndef()) {lib/Target/AMDGPU/SIISelLowering.cpp
2684 if (Callee.isUndef() || isNullConstant(Callee)) { 4988 if (Hi.isUndef()) { 4999 if (Lo.isUndef()) 8690 if (N->getOperand(0).isUndef()) 8701 if (N0.isUndef()) 8899 return Op.isUndef() || isa<ConstantFPSDNode>(Op); 8910 if (N0.isUndef()) { 8941 } else if (Op.isUndef()) { 8952 if (NewElts[0].isUndef()) { 8958 if (NewElts[1].isUndef()) { 9245 if (Src0.isUndef() && Src1.isUndef()) 9245 if (Src0.isUndef() && Src1.isUndef()) 10019 if (Src.isUndef())lib/Target/ARM/ARMISelLowering.cpp
7059 return U.get().isUndef() || U.get() == FirstOp; 7070 if (!isa<ConstantSDNode>(V) && !V.isUndef()) 7072 bool BitSet = V.isUndef() ? false : cast<ConstantSDNode>(V)->getZExtValue(); 7082 if (isa<ConstantSDNode>(V) || V.isUndef()) 7164 if (V.isUndef()) 7318 if (V.isUndef()) 7363 if (V.isUndef()) 7489 if (Entry.isUndef()) 7835 if (!V1.getOperand(i).isUndef()) { 8163 if (!Op0.isUndef()) 8167 if (!Op1.isUndef()) 9011 if (!PassThru.isUndef() && 12724 } else if (Elt.isUndef() || isa<ConstantSDNode>(Elt)) 12751 if (V.isUndef()) 12837 if (!Concat0Op1.isUndef() || !Concat1Op1.isUndef()) 12837 if (!Concat0Op1.isUndef() || !Concat1Op1.isUndef())lib/Target/AVR/AVRISelDAGToDAG.cpp
331 BasePtr.isUndef()) {
lib/Target/Hexagon/HexagonISelLowering.cpp 2103 if (V.isUndef()) {
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp616 SDValue Ext = !V.isUndef() ? DAG.getZExtOrTrunc(V, dl, MVT::i8) 629 if (!Values[I+B].isUndef()) 642 assert(Values[I+B].isUndef() || Values[I+B] == F); 1079 else if (V.isUndef())lib/Target/PowerPC/PPCISelDAGToDAG.cpp
633 if (!Offset.isUndef()) 676 if (!Offset.isUndef()) 5502 if (!TrueRes || TrueRes.isUndef()) 5505 if (!FalseRes || FalseRes.isUndef())lib/Target/PowerPC/PPCISelLowering.cpp
1910 if (N->getOperand(1).isUndef()) { 1950 if (N->getOperand(1).isUndef()) { 2048 if (N->getOperand(1).isUndef()) { 2119 if (N->getOperand(i).isUndef()) continue; 2164 if (N->getOperand(i).isUndef()) continue; 7528 if (LD->isIndexed() && !LD->getOffset().isUndef()) { 8206 if (V->getOperand(i).isUndef()) 8283 if (BVN->getOperand(i).isUndef()) continue; 8298 if (BVN->getOperand(i).isUndef()) 8319 if (BVN->getOperand(i).isUndef()) continue; 8706 if (V2.isUndef() && CurrentElement != VINSERTBSrcElem) 8719 (!V2.isUndef() && CurrentElement < BytesInVector) ? BytesInVector : 0; 8730 if (V2.isUndef()) { 8752 if (V2.isUndef()) 8821 if (V2.isUndef()) { 8858 if (V2.isUndef()) 8896 if (InputLoad && Subtarget.hasVSX() && V2.isUndef() && 8964 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, V2.isUndef() ? V1 : V2); 8977 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2.isUndef() ? V1 : V2); 9005 if (V2.isUndef() && PPC::isSplatShuffleMask(SVOp, 4)) { 9015 if (V2.isUndef() && PPC::isVSLDOIShuffleMask(SVOp, 1, DAG) == 8) { 9026 if (V2.isUndef()) V2 = V1; 9061 if (V2.isUndef()) { 9159 if (V2.isUndef()) V2 = V1; 12680 if (In.isUndef()) 12689 Ops.push_back(In.isUndef() ? DAG.getUNDEF(SrcVT) : In.getOperand(0));lib/Target/Sparc/SparcISelLowering.cpp
2729 assert(LdNode && LdNode->getOffset().isUndef() 2783 assert(StNode && StNode->getOffset().isUndef()lib/Target/SystemZ/SystemZISelLowering.cpp
4355 } else if (Op.isUndef()) { 4460 if (!Op.getOperand(I).isUndef()) 4476 if (Value.isUndef()) 4485 if (Op0.isUndef()) { 4486 if (Op1.isUndef()) 4490 if (Op1.isUndef()) 4501 if (Op0.isUndef() && Op1.isUndef()) 4501 if (Op0.isUndef() && Op1.isUndef()) 4505 if (Op0.isUndef()) 4507 else if (Op1.isUndef()) 4542 } else if (Op.isUndef()) { 4586 if (!Elem.isUndef()) { 4639 if (Op01.isUndef()) 4641 else if (Op23.isUndef()) 4700 bool Def1 = !Elems[I1].isUndef(); 4701 bool Def2 = !Elems[I2].isUndef(); 4716 if (!Done[I] && !Elems[I].isUndef() && Elems[I] != ReplicatedVal) 5893 Vec.getOpcode() == ISD::BSWAP || Vec.isUndef() || 5895 Elt.getOpcode() == ISD::BSWAP || Elt.isUndef() || 5924 Op0.getOpcode() == ISD::BSWAP || Op0.isUndef() || 5926 Op1.getOpcode() == ISD::BSWAP || Op1.isUndef()) {lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
1366 if (Lane.isUndef()) 1440 if (!Lane.isUndef() && !IsLaneConstructed(I, Lane))lib/Target/X86/X86ISelDAGToDAG.cpp
708 (Root->getOperand(0).isUndef() ||
lib/Target/X86/X86ISelLowering.cpp5509 if (Vec.isUndef()) 5662 if (SubVec.isUndef()) 5666 if (IdxVal == 0 && Vec.isUndef()) // the operation is legal 5716 if (Vec.isUndef()) { 6045 if (Op.isUndef()) { 6073 if (Src.isUndef()) { 6090 if (Src.isUndef()) { 6776 if (V.isUndef()) { 7124 if ((!N0.isUndef() && 7126 (!N1.isUndef() && 7131 if ((!N0.isUndef() && 7133 (!N1.isUndef() && 7245 if (Inputs[i].isUndef()) 7556 Undefs[i] = Elt.isUndef(); 7557 Zeroable[i] = (Elt.isUndef() || X86::isZeroNode(Elt)); 7813 if (Elt.isUndef()) { 8013 if (RepeatedLoads[i % SubElems].isUndef()) 8020 Match &= !RepeatedLoads.front().isUndef(); 8021 Match &= !RepeatedLoads.back().isUndef(); 8127 if (!(Op->getOperand(i).isUndef() || isNullConstant(Op->getOperand(i)))) 8138 Op->getOperand(i).isUndef())) 8488 if (!In.isUndef()) 8515 if (In.isUndef()) 8646 if (V0.isUndef()) { 8652 if (V1.isUndef()) { 8806 if (InVec0.isUndef()) { 8811 if (InVec1.isUndef()) { 8841 InVec0.isUndef() || InVec1.isUndef()) 8841 InVec0.isUndef() || InVec1.isUndef()) 8960 if (Op.isUndef()) 8991 if (V0.isUndef()) 8994 if (V1.isUndef()) 9048 if (BV->getOperand(i).isUndef()) 9070 count_if(BV->op_values(), [](SDValue V) { return !V.isUndef(); }); 9115 ((InVec0.isUndef() || InVec2.isUndef()) || InVec0 == InVec2) && 9115 ((InVec0.isUndef() || InVec2.isUndef()) || InVec0 == InVec2) && 9116 ((InVec1.isUndef() || InVec3.isUndef()) || InVec1 == InVec3)) 9116 ((InVec1.isUndef() || InVec3.isUndef()) || InVec1 == InVec3)) 9122 ((InVec0.isUndef() || InVec2.isUndef()) || InVec0 == InVec2) && 9122 ((InVec0.isUndef() || InVec2.isUndef()) || InVec0 == InVec2) && 9123 ((InVec1.isUndef() || InVec3.isUndef()) || InVec1 == InVec3)) 9123 ((InVec1.isUndef() || InVec3.isUndef()) || InVec1 == InVec3)) 9137 SDValue V0 = InVec0.isUndef() ? InVec2 : InVec0; 9138 SDValue V1 = InVec1.isUndef() ? InVec3 : InVec1; 9139 assert((!V0.isUndef() || !V1.isUndef()) && "Horizontal-op of undefs?"); 9139 assert((!V0.isUndef() || !V1.isUndef()) && "Horizontal-op of undefs?"); 9617 if (Elt.isUndef()) 9660 else if (!Elt.isUndef()) { 9905 if (!Op.getOperand(0).isUndef()) 9911 if (Op.getOperand(i).isUndef()) continue; 9923 if (!Op.getOperand(i).isUndef()) 9965 if (SubVec.isUndef()) 10023 if (SubVec.isUndef()) 10341 if (CondElt.isUndef() || isNullConstant(CondElt)) 10469 if (Op.isUndef() || X86::isZeroNode(Op)) 10494 AllZeroable &= (Op.isUndef() || X86::isZeroNode(Op)); 10841 if ((N1.isUndef() || DAG.MaskedValueIsZero(VV1, ZeroMask)) && 10842 (N2.isUndef() || DAG.MaskedValueIsZero(VV2, ZeroMask))) { 10850 if ((N1.isUndef() || DAG.ComputeNumSignBits(VV1) > BitSize) && 10851 (N2.isUndef() || DAG.ComputeNumSignBits(VV2) > BitSize)) { 10980 V1.isUndef() || ISD::isBuildVectorAllZeros(V1.getNode()); 10982 V2.isUndef() || ISD::isBuildVectorAllZeros(V2.getNode()); 11247 if (M < NumElts && (Op.isUndef() || Op == V1)) 11249 else if (NumElts <= M && (Op.isUndef() || Op == V2)) 12800 assert(!V2.isUndef() && 12916 if (V2.isUndef()) { 13000 if (V2.isUndef()) { 14155 if (V2.isUndef()) 14396 bool IsSingleInput = V2.isUndef(); 14642 assert(!V2.isUndef() && "This routine must not be used to lower single-input " 14787 assert(V2.isUndef() && 14817 if (Subtarget.hasAVX2() && V2.isUndef()) 14917 assert(!V2.isUndef() && "This is only useful with multiple inputs."); 15247 if (EltWidth == 64 && V2.isUndef()) 15587 if (V2.isUndef()) { 15705 if (V2.isUndef()) { 15811 if (V2.isUndef()) 15832 if (V2.isUndef()) { 15899 if (isUnpackWdShuffleMask(Mask, MVT::v8i32) && !V2.isUndef() && 15922 if (V2.isUndef()) 15960 if (V2.isUndef()) { 16041 if (V2.isUndef()) { 16143 if (V2.isUndef() && is128BitLaneCrossingShuffleMask(MVT::v32i8, Mask)) { 16339 if (Ops[OpIndex].isUndef()) 16362 if (V2.isUndef()) { 16428 if (V2.isUndef()) 16446 if (V2.isUndef() && 16469 if (V2.isUndef()) { 16547 if (V2.isUndef()) 16623 if (V2.isUndef()) { 16701 if (!V2.isUndef()) 16771 if (!V2.isUndef()) 17056 bool V1IsUndef = V1.isUndef(); 17057 bool V2IsUndef = V2.isUndef(); 22638 if (PreservedSrc.isUndef()) 22671 if (PreservedSrc.isUndef()) 23220 if (PassThru.isUndef()) 23346 if (PassThru.isUndef()) 23688 if (Src.isUndef() || ISD::isBuildVectorAllOnes(Mask.getNode())) 23725 if (Src.isUndef() || ISD::isBuildVectorAllOnes(Mask.getNode())) 25841 if (A.isUndef()) { 27342 if (InOp.isUndef()) 27358 N1.isUndef()) { 27464 if (PassThru.isUndef() || ISD::isBuildVectorAllZeros(PassThru.getNode())) 32344 Src.getOperand(0).isUndef() && 33622 if (((ZeroMask | (1u << DstIdx)) == 0xF) && !Op0.isUndef()) 33627 if ((ZeroMask & (1u << DstIdx)) && !Op1.isUndef()) 33997 N1.getNumOperands() != 2 || !N0.getOperand(1).isUndef() || 33998 !N1.getOperand(1).isUndef()) 34020 if (Opcode != ISD::VECTOR_SHUFFLE || !N->getOperand(1).isUndef()) 34044 if (!HOp.getOperand(0).isUndef() && !HOp.getOperand(1).isUndef() && 34044 if (!HOp.getOperand(0).isUndef() && !HOp.getOperand(1).isUndef() && 34054 if (HorizOp.getOperand(0).isUndef()) { 34055 assert(!HorizOp.getOperand(1).isUndef() && "Not expecting foldable h-op"); 34057 } else if (HorizOp.getOperand(1).isUndef()) { 34058 assert(!HorizOp.getOperand(0).isUndef() && "Not expecting foldable h-op"); 34223 N->getOperand(0).getOperand(0).isUndef() && 35324 if (!In.isUndef() && (cast<ConstantSDNode>(In)->getZExtValue() & 0x1)) 35395 if (V.isUndef()) 35415 if (Splat.isUndef()) 35590 LowUndef &= Op.isUndef() || (i >= e/2); 35591 AllUndefOrZero &= (Op.isUndef() || isNullConstant(Op)); 38434 if ((N0.isUndef() || N->isOnlyUserOf(N0.getNode())) && 38435 (N1.isUndef() || N->isOnlyUserOf(N1.getNode())) && 38489 N0.getOpcode() == ISD::TRUNCATE && N1.isUndef() && VT == MVT::v16i8 && 40283 if (Op.isUndef()) 40384 if (ML->getPassThru().isUndef()) 40766 if (LHS.isUndef() || RHS.isUndef()) 40766 if (LHS.isUndef() || RHS.isUndef()) 40787 if (!Op.getOperand(0).isUndef()) 40789 if (!Op.getOperand(1).isUndef()) 41436 if (!SVOp->getOperand(1).isUndef()) 41450 if (!InsVector.isUndef()) 42638 if ((N00.isUndef() || DAG.MaskedValueIsZero(N00, ZeroMask)) && 42639 (N01.isUndef() || DAG.MaskedValueIsZero(N01, ZeroMask))) { 42910 if (!Src.getOperand(Idx).isUndef() && 44274 if (llvm::all_of(Ops, [](SDValue Op) { return Op.isUndef(); })) 44417 if (Vec.isUndef() && SubVec.isUndef()) 44417 if (Vec.isUndef() && SubVec.isUndef()) 44421 if ((Vec.isUndef() || ISD::isBuildVectorAllZeros(Vec.getNode())) && 44422 (SubVec.isUndef() || ISD::isBuildVectorAllZeros(SubVec.getNode()))) 44462 (IdxVal != 0 || !Vec.isUndef())) { 44499 if (Vec.isUndef() && IdxVal != 0 && SubVec.getOpcode() == X86ISD::VBROADCAST) 44504 if (Vec.isUndef() && IdxVal != 0 && SubVec.hasOneUse() &&