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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc21156 return N->getFlags().hasNoUnsignedWrap();
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 946 if (N0->getFlags().hasVectorReduction())
1681 N->getFlags());
1990 SelectOp->setFlags(BO->getFlags());
2162 if (SDValue RADD = reassociateOps(ISD::ADD, DL, N0, N1, N->getFlags()))
2907 if (N->getFlags().hasNoUnsignedWrap())
2913 if (N->getFlags().hasNoSignedWrap())
3481 if (SDValue RMUL = reassociateOps(ISD::MUL, SDLoc(N), N0, N1, N->getFlags()))
3708 if (!N->getFlags().hasExact() && ISD::matchUnaryPredicate(N1, IsPowerOfTwo)) {
5087 if (SDValue RAND = reassociateOps(ISD::AND, SDLoc(N), N0, N1, N->getFlags()))
5797 if (SDValue ROR = reassociateOps(ISD::OR, SDLoc(N), N0, N1, N->getFlags()))
6899 if (SDValue RXOR = reassociateOps(ISD::XOR, DL, N0, N1, N->getFlags()))
7445 N0->getFlags().hasExact()) {
8330 SDNodeFlags Flags = N->getFlags();
8497 Flags = N0.getNode()->getFlags();
8824 SelectOp->setFlags(SCC->getFlags());
11319 SDNodeFlags F = N->getFlags();
11344 SDNodeFlags Flags = N->getFlags();
11555 const SDNodeFlags Flags = N->getFlags();
11832 const SDNodeFlags Flags = N->getFlags();
11927 const SDNodeFlags Flags = N->getFlags();
12106 const SDNodeFlags Flags = N->getFlags();
12198 const SDNodeFlags Flags = N->getFlags();
12335 const SDNodeFlags Flags = N->getFlags();
12451 const SDNodeFlags Flags = N->getFlags();
12483 if (UnsafeMath || U->getFlags().hasAllowReciprocal())
12521 SDNodeFlags Flags = N->getFlags();
12626 return DAG.getNode(ISD::FREM, SDLoc(N), VT, N0, N1, N->getFlags());
12635 SDNodeFlags Flags = N->getFlags();
12730 SDNodeFlags Flags = N->getFlags();
12759 SDNodeFlags Flags = N->getFlags();
13208 N0->getFlags());
18065 BinOp->getFlags());
18136 BinOp.getNode()->getFlags());
18912 N0.getNode()->getFlags());
19560 SDValue ScalarBO = DAG.getNode(Opcode, DL, EltVT, X, Y, N->getFlags());
19592 Opcode, SDLoc(LHS), LHS.getValueType(), Ops, N->getFlags()))
19612 RHS.getOperand(0), N->getFlags());
19694 const SDNodeFlags Flags = N0.getNode()->getFlags();
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 854 const SDNodeFlags Flags = Node->getFlags();
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3177 const SDNodeFlags Flags = Node->getFlags();
3434 Tmp1->setFlags(Node->getFlags());
3518 Tmp1, Tmp2, Tmp3, Node->getFlags());
3546 Tmp1->setFlags(Node->getFlags());
3567 SDValue Cond = DAG.getNode(ISD::SETCC, dl, CCVT, Tmp1, Tmp2, CC, Node->getFlags());
3583 Tmp1->setFlags(Node->getFlags());
3593 Tmp1->setFlags(Node->getFlags());
3620 Tmp1->setFlags(Node->getFlags());
4297 Tmp1->setFlags(Node->getFlags());
4329 Tmp2, Node->getOperand(2), Node->getFlags()));
4357 Node->getFlags());
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 2233 return DAG.getNode(N->getOpcode(), SDLoc(N), NVT, Op0, Op1, N->getFlags());
lib/CodeGen/SelectionDAG/LegalizeTypes.cpp 694 Result->setFlags(Op->getFlags());
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 560 Op = DAG.getNode(Op.getOpcode(), dl, NVT, Operands, Op.getNode()->getFlags());
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 203 LHS.getValueType(), LHS, RHS, N->getFlags());
1022 const SDNodeFlags Flags = N->getFlags();
1386 Scalar.getNode()->setFlags(N->getFlags());
2119 bool NoNaN = N->getFlags().hasNoNaNs();
2145 SDValue Partial = DAG.getNode(CombineOpc, dl, LoOpVT, Lo, Hi, N->getFlags());
2146 return DAG.getNode(N->getOpcode(), dl, ResVT, Partial, N->getFlags());
2923 return DAG.getNode(N->getOpcode(), dl, WidenVT, InOp1, InOp2, N->getFlags());
2934 N->getFlags());
3026 const SDNodeFlags Flags = N->getFlags();
3270 const SDNodeFlags Flags = N->getFlags();
4636 return DAG.getNode(N->getOpcode(), dl, N->getValueType(0), Op, N->getFlags());
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 946 Node->intersectFlagsWith(N->getFlags());
966 Node->intersectFlagsWith(N->getFlags());
984 Node->intersectFlagsWith(N->getFlags());
3982 if (getTarget().Options.NoNaNsFPMath || Op->getFlags().hasNoNaNs())
9034 SDNodeFlags Flags = Op->getFlags();
9148 N->getFlags()));
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 1101 if (!Node->getFlags().isDefined())
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 511 if (getFlags().hasNoUnsignedWrap())
514 if (getFlags().hasNoSignedWrap())
517 if (getFlags().hasExact())
520 if (getFlags().hasNoNaNs())
523 if (getFlags().hasNoInfs())
526 if (getFlags().hasNoSignedZeros())
529 if (getFlags().hasAllowReciprocal())
532 if (getFlags().hasAllowContract())
535 if (getFlags().hasApproximateFuncs())
538 if (getFlags().hasAllowReassociation())
541 if (getFlags().hasVectorReduction())
lib/CodeGen/SelectionDAG/TargetLowering.cpp 1388 if (Op->getFlags().hasExact())
1453 if (Op->getFlags().hasExact())
1473 Flags.setExact(Op->getFlags().hasExact());
1924 SDNodeFlags Flags = Op.getNode()->getFlags();
4651 if (N->getFlags().hasExact())
5351 const SDNodeFlags Flags = Op->getFlags();
5468 const SDNodeFlags Flags = Op->getFlags();
6129 if (!Node->getFlags().hasNoNaNs()) {
6134 Node->getFlags());
6138 Node->getFlags());
6142 return DAG.getNode(NewOp, dl, VT, Quiet0, Quiet1, Node->getFlags());
6147 if (Node->getFlags().hasNoNaNs()) {
6152 Node->getOperand(1), Node->getFlags());
7317 bool NoNaN = Node->getFlags().hasNoNaNs();
7365 Res = DAG.getNode(BaseOpcode, dl, EltVT, Res, Ops[i], Node->getFlags());
lib/Target/AArch64/AArch64ISelLowering.cpp 8232 assert(Op->getFlags().hasNoNaNs() && "fmax vector reduction needs NoNaN flag");
8239 assert(Op->getFlags().hasNoNaNs() && "fmin vector reduction needs NoNaN flag");
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 511 if (N->getFlags().isDefined())
512 return N->getFlags().hasNoNaNs();
1810 Addr->getFlags().hasNoUnsignedWrap()) &&
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 2303 SDValue Mul = DAG.getNode(ISD::FMUL, SL, VT, Src, K, Op->getFlags());
2304 return DAG.getNode(ISD::FEXP2, SL, VT, Mul, Op->getFlags());
3674 SDValue Res = DAG.getNode(ISD::FADD, SL, VT, LHS, RHS, N0->getFlags());
3695 SDValue Res = DAG.getNode(Opc, SL, VT, LHS, RHS, N0->getFlags());
3754 SDValue Res = DAG.getNode(Opposite, SL, VT, NegLHS, NegRHS, N0->getFlags());
3764 Ops[I] = DAG.getNode(ISD::FNEG, SL, VT, N0->getOperand(I), N0->getFlags());
3766 SDValue Res = DAG.getNode(AMDGPUISD::FMED3, SL, VT, Ops, N0->getFlags());
3796 return DAG.getNode(Opc, SL, VT, Neg, N0->getFlags());
lib/Target/AMDGPU/AMDGPUISelLowering.h 153 const auto Flags = Op.getNode()->getFlags();
lib/Target/AMDGPU/SIISelLowering.cpp 3959 Op->getFlags());
3961 Op->getFlags());
3982 Op->getFlags());
3984 Op->getFlags());
4005 Op->getFlags());
4007 Op->getFlags());
7522 const SDNodeFlags Flags = Op->getFlags();
8085 Flags.setNoUnsignedWrap(N->getFlags().hasNoUnsignedWrap() &&
8087 N0->getFlags().hasNoUnsignedWrap()));
8707 N->getFlags());
9302 return DAG.getNode(Opc, SL, EltVT, Elt0, Elt1, Vec->getFlags());
9421 (N0->getFlags().hasAllowContract() &&
9422 N1->getFlags().hasAllowContract())) &&
9719 (N->getFlags().hasAllowContract() &&
9720 FMA->getFlags().hasAllowContract())) {
lib/Target/PowerPC/PPCISelLowering.cpp10093 NewLoad[1], Op0.getNode()->getFlags());
lib/Target/X86/X86ISelLowering.cpp20041 if (Op.getNode()->getFlags().hasNoSignedWrap())
41560 Arg->getFlags().hasNoSignedZeros() && Subtarget.hasAnyFMA()) {
41932 if (DAG.getTarget().Options.NoNaNsFPMath || N->getFlags().hasNoNaNs())
41933 return DAG.getNode(MinMaxOp, DL, VT, Op0, Op1, N->getFlags());
41938 return DAG.getNode(MinMaxOp, DL, VT, Op0, Op1, N->getFlags());
41940 return DAG.getNode(MinMaxOp, DL, VT, Op1, Op0, N->getFlags());
42217 bool NSW = Add->getFlags().hasNoSignedWrap();
42218 bool NUW = Add->getFlags().hasNoUnsignedWrap();
44062 const SDNodeFlags Flags = N->getFlags();