reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/MachinePipeliner.cpp

  696           if (TII->getMemOperandWithOffset(LdMI, BaseOp1, Offset1, TRI) &&
  697               TII->getMemOperandWithOffset(MI, BaseOp2, Offset2, TRI)) {
 1616                    << TRI->getRegPressureSetName(RPDelta.Excess.getPSet())

lib/CodeGen/MachineScheduler.cpp

 1022                dumpRegSetPressure(BotRPTracker.getLiveThru(), TRI));
 1037              dumpRegSetPressure(TopRPTracker.getRegSetPressureAtPos(), TRI);
 1039              dumpRegSetPressure(BotRPTracker.getRegSetPressureAtPos(), TRI););
 1054       LLVM_DEBUG(dbgs() << TRI->getRegPressureSetName(i) << " Limit " << Limit
 1062              << TRI->getRegPressureSetName(RCPS.getPSet()) << " ";
 1084       LLVM_DEBUG(dbgs() << "  " << TRI->getRegPressureSetName(ID) << ": "
 1119                           << printReg(Reg, TRI) << ':'
 1121                    dbgs() << "              to "; PDiff.dump(*TRI););
 1125       LLVM_DEBUG(dbgs() << "  LiveReg: " << printVRegOrUnit(Reg, TRI) << "\n");
 1155                        dbgs() << "              to "; PDiff.dump(*TRI););
 1171       getPressureDiff(&SU).dump(*TRI);
 1402       RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
 1415                      TopRPTracker.getRegSetPressureAtPos(), TRI););
 1436       RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
 1452                      BotRPTracker.getRegSetPressureAtPos(), TRI););
 2719   TRI = DAG->TRI;
 3308   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));
 3327   TRI = DAG->TRI;

lib/CodeGen/ScheduleDAG.cpp

  372       Dep.dump(TRI);
  382       Dep.dump(TRI);

lib/CodeGen/ScheduleDAGInstrs.cpp

  241   for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
  299   for (MCRegAliasIterator Alias(Reg, TRI, true); Alias.isValid(); ++Alias) {
  333     for (MCSubRegIterator SubReg(Reg, TRI, true); SubReg.isValid(); ++SubReg) {
  372   return TRI->getSubRegIndexLaneMask(SubReg);
  778   Defs.setUniverse(TRI->getNumRegs());
  779   Uses.setUniverse(TRI->getNumRegs());
  813       RegOpers.collect(MI, *TRI, MRI, TrackLaneMasks, false);
 1106   LiveRegs.init(*TRI);

lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp

  121   LiveRegDefs.resize(TRI->getNumRegs(), nullptr);
  122   LiveRegCycles.resize(TRI->getNumRegs(), 0);
  477                          RegAdded, LRegs, TRI);
  502               CheckForLiveRegDef(SU, Reg, LiveRegDefs, RegAdded, LRegs, TRI);
  515       CheckForLiveRegDef(SU, *Reg, LiveRegDefs, RegAdded, LRegs, TRI);
  574           TRI->getMinimalPhysRegClass(Reg, VT);
  575         const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

  365   LiveRegDefs.reset(new SUnit*[TRI->getNumRegs() + 1]());
  366   LiveRegGens.reset(new SUnit*[TRI->getNumRegs() + 1]());
  577   unsigned CallResource = TRI->getNumRegs();
  782   unsigned CallResource = TRI->getNumRegs();
  854   unsigned CallResource = TRI->getNumRegs();
 1358                          RegAdded, LRegs, TRI);
 1382               CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
 1397       unsigned CallResource = TRI->getNumRegs();
 1409                                makeArrayRef(LiveRegDefs.get(), TRI->getNumRegs()),
 1422           CheckForLiveRegDef(SU, Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
 1428       CheckForLiveRegDef(SU, *Reg, LiveRegDefs.get(), RegAdded, LRegs, TRI);
 1471                  if (LRegs[0] == TRI->getNumRegs()) dbgs() << "CallResource";
 1472                  else dbgs() << printReg(LRegs[0], TRI);
 1558       TRI->getMinimalPhysRegClass(Reg, VT);
 1559     const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);

lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

  486         CheckForPhysRegDependency(OpN, N, i, TRI, TII, PhysReg, Cost);

lib/Target/AArch64/AArch64TargetMachine.cpp

  364     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
  365     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));

lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

  262   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
  263   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
  272   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
  273   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
  286   DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
  287   DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));
  559     DAG->addMutation(createLoadClusterDAGMutation(DAG->TII, DAG->TRI));
  560     DAG->addMutation(createStoreClusterDAGMutation(DAG->TII, DAG->TRI));

lib/Target/AMDGPU/GCNIterativeScheduler.cpp

  396       RegOpers.collect(*MI, *TRI, MRI, /*ShouldTrackLaneMasks*/true,

lib/Target/AMDGPU/GCNSchedStrategy.cpp

  413     RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);

lib/Target/AMDGPU/R600MachineScheduler.cpp

   32   TRI = static_cast<const R600RegisterInfo*>(DAG->TRI);

lib/Target/AMDGPU/SIMachineScheduler.cpp

 1806   SITRI = static_cast<const SIRegisterInfo*>(TRI);
 1964                                          TRI))

lib/Target/AMDGPU/SIMachineScheduler.h

  460   const TargetRegisterInfo *getTRI() { return TRI; }

lib/Target/Hexagon/HexagonMachineScheduler.cpp

  488     dbgs() << DAG->TRI->getRegPressureSetName(P.getPSet()) << ":"

lib/Target/Hexagon/HexagonTargetMachine.cpp

  118   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));

lib/Target/PowerPC/PPCTargetMachine.cpp

  275   DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI));