reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/ScheduleDAG.cpp

  141     assert(N->NumSuccs < std::numeric_limits<unsigned>::max() &&
  144     ++N->NumSuccs;
  191     assert(N->NumSuccs > 0 && "NumSuccs will underflow!");
  193     --N->NumSuccs;
  395       if (SUnit.NumPreds == 0 && SUnit.NumSuccs == 0) {

lib/CodeGen/ScheduleDAGInstrs.cpp

  872     if (SU->NumSuccs == 0 && SU->Latency > 1 && (HasVRegDef || MI.mayLoad())) {

lib/CodeGen/ScheduleDAGPrinter.cpp

   39       return (Node->NumPreds > 10 || Node->NumSuccs > 10);

lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp

 2043   if (SU->NumSuccs == 0 && SU->NumPreds != 0)
 2050   if (SU->NumPreds == 0 && SU->NumSuccs != 0)
 2111   if (!N->isMachineOpcode() || !SU->NumSuccs)
 2157   if (!N || !N->isMachineOpcode() || !SU->NumSuccs)
 2305   if (SU->NumSuccs && N->isMachineOpcode()) {
 2724   if (SU->NumPreds == 0 && SU->NumSuccs != 0)
 2946     if (SU.NumSuccs != 0)
 2996     if (PredSU->NumSuccs == 1)
 3012       if (PredSuccSU->NumSuccs == 0)

lib/Target/AMDGPU/GCNILPSched.cpp

   89   if (SU->NumSuccs == 0 && SU->NumPreds != 0)
   97   if (SU->NumPreds == 0 && SU->NumSuccs != 0)

lib/Target/Hexagon/HexagonSubtarget.cpp

  346   if ((DstInst->isRegSequence() || DstInst->isCopy()) && Dst->NumSuccs == 1) {