reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/MachinePipeliner.cpp

  776                  UI = MRI.use_instr_begin(Reg),
  777                  UE = MRI.use_instr_end();
  797         MachineInstr *DefMI = MRI.getUniqueVRegDef(Reg);
  852     MachineInstr *DefMI = MRI.getUniqueVRegDef(OrigBase);
  859     MachineInstr *LastMI = MRI.getUniqueVRegDef(NewBase);
 2188   MachineInstr *Def = MRI.getVRegDef(Reg);
 2194         Def = MRI.getVRegDef(Def->getOperand(i).getReg());
 2248   MachineInstr *Def = MRI.getVRegDef(BaseOpS->getReg());
 2254   MachineInstr *LoopDef = MRI.getVRegDef(LoopVal);

lib/CodeGen/MachineScheduler.cpp

  994   VRegUses.setUniverse(MRI.getNumVirtRegs());
 1117         PDiff.addPressureChange(Reg, Decrement, &MRI);
 1152             PDiff.addPressureChange(Reg, true, &MRI);
 1402       RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
 1406         RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);
 1436       RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
 1440         RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);

lib/CodeGen/PostRASchedulerList.cpp

  220           MRI.tracksLiveness()) &&

lib/CodeGen/ScheduleDAGInstrs.cpp

  289   if (MRI.isConstantPhysReg(Reg))
  365   const TargetRegisterClass &RC = *MRI.getRegClass(Reg);
  457   if (MRI.hasOneDef(Reg))
  783   unsigned NumVirtRegs = MRI.getNumVirtRegs();
  813       RegOpers.collect(MI, *TRI, MRI, TrackLaneMasks, false);
  816         RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx);
  819         PDiffs->addInstruction(SU->NodeNum, RegOpers, MRI);
 1133       toggleKills(MRI, LiveRegs, MI, true);
 1137         toggleKills(MRI, LiveRegs, MI, false);
 1147           toggleKills(MRI, LiveRegs, *I, true);

lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp

  811       Register VRBase = MRI.createVirtualRegister(SU->CopyDstRC);

lib/Target/AMDGPU/GCNIterativeScheduler.cpp

  396       RegOpers.collect(*MI, *TRI, MRI, /*ShouldTrackLaneMasks*/true,
  400       RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);

lib/Target/AMDGPU/GCNSchedStrategy.cpp

  341                GCNRPTracker::printLiveRegs(dbgs(), LiveIns[RegionIdx], MRI);
  343                llvm::getRegPressure(MRI, LiveIns[RegionIdx]).print(dbgs());
  413     RegOpers.collect(*MI, *TRI, MRI, ShouldTrackLaneMasks, false);
  418         RegOpers.adjustLaneLiveness(*LIS, MRI, SlotIdx, MI);

lib/Target/AMDGPU/R600MachineScheduler.cpp

   34   MRI = &DAG->MRI;

lib/Target/AMDGPU/SIMachineScheduler.cpp

 1918     PSetIterator PSetI = MRI.getPressureSets(Reg);

lib/Target/AMDGPU/SIMachineScheduler.h

  459   MachineRegisterInfo *getMRI() { return &MRI; }