reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
306 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit); 319 unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);lib/CodeGen/MachineScheduler.cpp
1098 unsigned Reg = P.RegUnit; 1323 unsigned Reg = P.RegUnit;lib/CodeGen/RegisterPressure.cpp
100 dbgs() << printVRegOrUnit(P.RegUnit, TRI); 108 dbgs() << printVRegOrUnit(P.RegUnit, TRI); 363 unsigned RegUnit = Pair.RegUnit; 374 return Other.RegUnit == RegUnit; 383 unsigned RegUnit = Pair.RegUnit; 386 return Other.RegUnit == RegUnit; 398 return Other.RegUnit == RegUnit; 409 unsigned RegUnit = Pair.RegUnit; 412 return Other.RegUnit == RegUnit; 583 unsigned Reg = RI->RegUnit; 604 LaneBitmask LiveAfter = getLiveLanesAt(LIS, MRI, true, I->RegUnit, 608 unsigned RegUnit = I->RegUnit; 622 LaneBitmask LiveBefore = getLiveLanesAt(LIS, MRI, true, I->RegUnit, 634 unsigned RegUnit = P.RegUnit; 663 PDiff.addPressureChange(P.RegUnit, true, &MRI); 666 PDiff.addPressureChange(P.RegUnit, false, &MRI); 709 increaseRegPressure(P.RegUnit, PrevMask, NewMask); 717 unsigned RegUnit = Pair.RegUnit; 719 return Other.RegUnit == RegUnit; 745 unsigned Reg = P.RegUnit; 751 unsigned Reg = P.RegUnit; 773 unsigned Reg = Def.RegUnit; 803 unsigned Reg = Use.RegUnit; 818 return Other.RegUnit == Reg; 843 unsigned RegUnit = Def.RegUnit; 914 unsigned Reg = Use.RegUnit; 936 increaseRegPressure(Def.RegUnit, PreviousMask, NewMask); 1063 unsigned Reg = P.RegUnit; 1072 unsigned Reg = P.RegUnit; 1297 unsigned Reg = Use.RegUnit; 1320 unsigned Reg = Def.RegUnit;lib/Target/AMDGPU/GCNRegPressure.cpp
243 return RM.RegUnit == Reg; 324 auto LiveMask = LiveRegs[U.RegUnit]; 325 AtMIPressure.inc(U.RegUnit, LiveMask, LiveMask | U.LaneMask, *MRI); 346 auto &LiveMask = LiveRegs[U.RegUnit]; 349 CurPressure.inc(U.RegUnit, PrevMask, LiveMask, *MRI);lib/Target/AMDGPU/SIMachineScheduler.cpp
351 if (Register::isVirtualRegister(RegMaskPair.RegUnit)) 352 LiveInRegs.insert(RegMaskPair.RegUnit); 378 unsigned Reg = RegMaskPair.RegUnit;lib/Target/AMDGPU/SIMachineScheduler.h
475 InRegs.insert(RegMaskPair.RegUnit); 483 OutRegs.insert(RegMaskPair.RegUnit);