|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/ARM/ARMGenSubtargetInfo.inc19932 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19936 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19940 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19944 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19948 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19952 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19956 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19960 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19964 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
20007 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20013 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20016 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20019 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20022 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20025 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20028 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20031 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20034 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21450 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21456 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21459 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21462 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21465 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21468 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21471 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21474 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21477 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21508 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21514 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21517 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21520 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21523 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21526 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21529 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21532 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21535 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21680 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21684 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21688 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21692 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21696 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21700 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21704 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21708 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21712 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
22385 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22391 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22394 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22397 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22400 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22403 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22406 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22409 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22412 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
include/llvm/CodeGen/MachineRegisterInfo.h 730 if (Register::isVirtualRegister(Reg) && VRegToType.inBounds(Reg))
763 assert(Register::isVirtualRegister(VReg));
772 assert(Register::isVirtualRegister(VReg));
812 assert(Register::isVirtualRegister(VReg));
1179 if (Register::isVirtualRegister(RegUnit)) {
include/llvm/CodeGen/Register.h 77 assert(isVirtualRegister(Reg) && "Not a virtual register");
90 return isVirtualRegister(Reg);
include/llvm/CodeGen/RegisterPressure.h 279 if (Register::isVirtualRegister(Reg))
lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp 278 if (Register::isVirtualRegister(MO.getReg()))
lib/CodeGen/BranchFolding.cpp 2090 if (!Reg || Register::isVirtualRegister(Reg))
lib/CodeGen/CalcSpillWeights.cpp 69 if (Register::isVirtualRegister(hreg))
116 if (!Register::isVirtualRegister(Reg) ||
255 if (Register::isVirtualRegister(hint) || mri.isAllocatable(hint))
lib/CodeGen/DetectDeadLanes.cpp 198 if (!Register::isVirtualRegister(MOReg))
222 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
289 if (!Register::isVirtualRegister(DefReg))
390 assert(Register::isVirtualRegister(MOReg));
434 if (Register::isVirtualRegister(DefReg)) {
474 if (!Register::isVirtualRegister(DefReg))
486 if (Register::isVirtualRegister(MOReg)) {
540 if (!Register::isVirtualRegister(Reg))
lib/CodeGen/EarlyIfConversion.cpp 269 if (!MO.readsReg() || !Register::isVirtualRegister(Reg))
518 assert(Register::isVirtualRegister(PI.TReg) && "Bad PHI");
519 assert(Register::isVirtualRegister(PI.FReg) && "Bad PHI");
lib/CodeGen/GlobalISel/InstructionSelect.cpp 172 if (Register::isVirtualRegister(SrcReg) &&
173 Register::isVirtualRegister(DstReg)) {
lib/CodeGen/GlobalISel/Utils.cpp 48 assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
77 assert(Register::isVirtualRegister(Reg) && "PhysReg not implemented");
lib/CodeGen/InlineSpiller.cpp 349 return Register::isVirtualRegister(Reg) && VRM.getOriginal(Reg) == Original;
848 if (!Reg || Register::isVirtualRegister(Reg) || MRI.isReserved(Reg)) {
lib/CodeGen/LiveDebugVariables.cpp 569 Register::isVirtualRegister(locations[i].getReg()))
586 assert(Register::isVirtualRegister(VirtReg) && "Only map VirtRegs");
617 Register::isVirtualRegister(MI.getOperand(0).getReg())) {
768 if (!Register::isVirtualRegister(LI->reg))
784 if (!Register::isVirtualRegister(DstReg))
855 if (Register::isVirtualRegister(LocMO.getReg())) {
1172 Register::isVirtualRegister(Loc.getReg())) {
lib/CodeGen/LiveInterval.cpp 889 if (!Register::isVirtualRegister(Reg) || !Reg)
971 assert(Register::isVirtualRegister(reg));
lib/CodeGen/LiveIntervals.cpp 444 assert(Register::isVirtualRegister(li->reg) &&
544 assert(Register::isVirtualRegister(Reg) &&
992 if (Register::isVirtualRegister(Reg)) {
1026 if (Register::isVirtualRegister(Reg)) {
1402 if (Register::isVirtualRegister(Reg)) {
1603 if (MOI->isReg() && Register::isVirtualRegister(MOI->getReg()) &&
1611 if (!Register::isVirtualRegister(Reg))
lib/CodeGen/LiveRangeEdit.cpp 312 if (!Register::isVirtualRegister(Reg)) {
lib/CodeGen/LiveRangeShrink.cpp 178 if (!Register::isVirtualRegister(Reg)) {
lib/CodeGen/LiveVariables.cpp 86 assert(Register::isVirtualRegister(RegIdx) &&
543 if (Register::isVirtualRegister(MOReg))
556 if (Register::isVirtualRegister(MOReg))
695 if (Register::isVirtualRegister(Reg)) {
785 if (I->isReg() && Register::isVirtualRegister(I->getReg())) {
lib/CodeGen/MIRCanonicalizerPass.cpp 173 if (Register::isVirtualRegister(MO.getReg()))
190 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
203 if (!Register::isVirtualRegister(II->getOperand(i).getReg()))
326 if (!Register::isVirtualRegister(Dst))
328 if (!Register::isVirtualRegister(Src))
lib/CodeGen/MIRParser/MIParser.cpp 1412 if (!Register::isVirtualRegister(Reg))
1416 if (!Register::isVirtualRegister(Reg))
1446 if (!Register::isVirtualRegister(Reg))
1461 } else if (Register::isVirtualRegister(Reg)) {
lib/CodeGen/MIRVRegNamerUtils.cpp 62 DoesMISideEffect |= !Register::isVirtualRegister(Dst);
103 if (Register::isVirtualRegister(Reg)) {
185 } else if (!Register::isVirtualRegister(vreg.getReg())) {
279 if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
lib/CodeGen/MachineBasicBlock.cpp 999 if (Register::isVirtualRegister(Reg))
lib/CodeGen/MachineCSE.cpp 171 if (!Register::isVirtualRegister(Reg))
178 if (!Register::isVirtualRegister(SrcReg))
288 if (Register::isVirtualRegister(Reg))
307 if (Register::isVirtualRegister(Reg))
382 if (Register::isVirtualRegister(MOReg))
438 if (Register::isVirtualRegister(CSReg) && Register::isVirtualRegister(Reg)) {
438 if (Register::isVirtualRegister(CSReg) && Register::isVirtualRegister(Reg)) {
466 if (MO.isReg() && MO.isUse() && Register::isVirtualRegister(MO.getReg())) {
616 assert(Register::isVirtualRegister(OldReg) &&
617 Register::isVirtualRegister(NewReg) &&
781 if (!Register::isVirtualRegister(def.getReg()))
785 if (use.isReg() && !Register::isVirtualRegister(use.getReg()))
lib/CodeGen/MachineCombiner.cpp 140 if (MO.isReg() && Register::isVirtualRegister(MO.getReg()))
171 if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
226 if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
lib/CodeGen/MachineCopyPropagation.cpp 474 assert(!Register::isVirtualRegister(Def) &&
475 !Register::isVirtualRegister(Src) &&
567 assert(!Register::isVirtualRegister(Reg) &&
lib/CodeGen/MachineInstr.cpp 630 if (!Register::isVirtualRegister(MO.getReg()) ||
631 !Register::isVirtualRegister(OMO.getReg()))
1983 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
lib/CodeGen/MachineLICM.cpp 855 if (!Register::isVirtualRegister(Reg))
927 if (Register::isVirtualRegister(Reg))
929 if (Register::isVirtualRegister(Reg))
958 if (Register::isVirtualRegister(CopySrcReg))
966 assert(Register::isVirtualRegister(CopyDstReg) &&
1064 if (!Register::isVirtualRegister(Reg))
1228 if (!Register::isVirtualRegister(Reg))
lib/CodeGen/MachineOperand.cpp 773 if (Register::isVirtualRegister(Reg)) {
788 if (Register::isVirtualRegister(Reg)) {
lib/CodeGen/MachinePipeliner.cpp 1557 if (Register::isVirtualRegister(Reg))
1568 if (Register::isVirtualRegister(Reg)) {
2474 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
lib/CodeGen/MachineRegisterInfo.cpp 501 assert(Register::isVirtualRegister(Reg));
lib/CodeGen/MachineScheduler.cpp 939 if (!Register::isVirtualRegister(Reg))
1100 if (!Register::isVirtualRegister(Reg))
1324 if (!Register::isVirtualRegister(Reg))
1693 if (!Register::isVirtualRegister(SrcReg) || !SrcOp.readsReg())
1698 if (!Register::isVirtualRegister(DstReg) || DstOp.isDead())
lib/CodeGen/MachineSink.cpp 208 if (!Register::isVirtualRegister(SrcReg) ||
209 !Register::isVirtualRegister(DstReg) || !MRI->hasOneNonDBGUse(SrcReg))
243 assert(Register::isVirtualRegister(Reg) && "Only makes sense for vregs");
lib/CodeGen/MachineTraceMetrics.cpp 637 assert(Register::isVirtualRegister(VirtReg));
768 if (!Register::isVirtualRegister(LIR.Reg))
982 assert(Register::isVirtualRegister(Reg));
1029 if (Register::isVirtualRegister(LI.Reg)) {
lib/CodeGen/MachineVerifier.cpp 162 if (!Register::isVirtualRegister(Reg))
181 if (!Register::isVirtualRegister(Reg))
555 if (Register::isVirtualRegister(VRegOrUnit)) {
1921 assert(Register::isVirtualRegister(VRegOrUnit) &&
1949 if (LiveVars && Register::isVirtualRegister(Reg) && MO->isKill()) {
1968 if (Register::isVirtualRegister(Reg)) {
2063 if (MRI->isSSA() && Register::isVirtualRegister(Reg) &&
2072 if (Register::isVirtualRegister(Reg)) {
2223 if (!Register::isVirtualRegister(DefReg))
2418 if (Register::isVirtualRegister(Reg)) {
2505 if (!Register::isVirtualRegister(Reg) && VNI->isPHIDef() &&
2549 if (Register::isVirtualRegister(Reg)) {
2622 if (!Register::isVirtualRegister(Reg) && MFI->isEHPad()) {
2682 assert(Register::isVirtualRegister(Reg));
lib/CodeGen/ModuloSchedule.cpp 626 !Register::isVirtualRegister(MO.getReg()))
1027 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
lib/CodeGen/OptimizePHIs.cpp 120 Register::isVirtualRegister(SrcMI->getOperand(1).getReg())) {
145 assert(Register::isVirtualRegister(DstReg) &&
lib/CodeGen/PHIElimination.cpp 380 assert(Register::isVirtualRegister(SrcReg) &&
lib/CodeGen/PeepholeOptimizer.cpp 1322 if (!MI.getOperand(0).getSubReg() && Register::isVirtualRegister(Reg) &&
1339 if (Register::isVirtualRegister(Reg)) {
1362 if (!Register::isVirtualRegister(Reg))
1396 if (!Register::isVirtualRegister(SrcReg))
1400 if (!Register::isVirtualRegister(DstReg))
1447 if (isNAPhysCopy(SrcReg) && Register::isVirtualRegister(DstReg)) {
1455 if (!(Register::isVirtualRegister(SrcReg) && isNAPhysCopy(DstReg)))
1490 return Register::isVirtualRegister(MO.getReg());
lib/CodeGen/ProcessImplicitDefs.cpp 78 if (Register::isVirtualRegister(Reg)) {
lib/CodeGen/RegAllocBase.cpp 157 assert(Register::isVirtualRegister(SplitVirtReg->reg) &&
lib/CodeGen/RegAllocFast.cpp 397 assert(Register::isVirtualRegister(VirtReg) &&
408 assert(Register::isVirtualRegister(VirtReg) &&
630 assert(Register::isVirtualRegister(Reg));
664 assert(Register::isVirtualRegister(VirtReg) &&
754 assert(Register::isVirtualRegister(VirtReg) && "Expected virtreg");
779 assert(Register::isVirtualRegister(VirtReg) && "Not a virtual register");
812 assert(Register::isVirtualRegister(VirtReg) && "Not a virtual register");
893 if (!Register::isVirtualRegister(Reg))
923 if (!Register::isVirtualRegister(Reg))
949 if (!Register::isVirtualRegister(Reg))
1005 assert(Register::isVirtualRegister(i->VirtReg) && "Bad map key");
1048 if (Register::isVirtualRegister(Reg)) {
1098 if (!Register::isVirtualRegister(Reg))
1127 if (!Register::isVirtualRegister(Reg))
1218 if (!Register::isVirtualRegister(Reg))
lib/CodeGen/RegAllocGreedy.cpp 688 assert(Register::isVirtualRegister(Reg) &&
902 assert(Register::isVirtualRegister(Intf->reg) &&
987 if (!Register::isVirtualRegister(Intf->reg))
3024 assert(Register::isVirtualRegister(LI->reg) &&
lib/CodeGen/RegisterCoalescer.cpp 477 assert(Register::isVirtualRegister(Src) && "Src must be virtual");
838 if (Register::isVirtualRegister(IntA.reg) &&
839 Register::isVirtualRegister(IntB.reg) &&
1272 assert(Register::isVirtualRegister(DstReg) &&
1344 if (Register::isVirtualRegister(DstReg)) {
2415 if (!Register::isVirtualRegister(SrcReg))
3193 if (Register::isVirtualRegister(Reg) && Reg != CP.getSrcReg() &&
lib/CodeGen/RegisterPressure.cpp 238 if (Register::isVirtualRegister(Reg))
364 if (Register::isVirtualRegister(RegUnit)
425 if (Register::isVirtualRegister(RegUnit)) {
522 if (Register::isVirtualRegister(Reg)) {
554 if (Register::isVirtualRegister(Reg)) {
609 if (Register::isVirtualRegister(RegUnit) &&
635 if (!Register::isVirtualRegister(RegUnit))
844 if (Register::isVirtualRegister(RegUnit) &&
lib/CodeGen/RegisterScavenging.cpp 332 if (Register::isVirtualRegister(MO.getReg())) {
433 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
545 !Register::isVirtualRegister(MO.getReg()))
701 if (!Register::isVirtualRegister(Reg) ||
721 if (!Register::isVirtualRegister(Reg) ||
740 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
lib/CodeGen/ScheduleDAGInstrs.cpp 210 } else if (Register::isVirtualRegister(Reg) && MO.readsReg()) {
844 } else if (Register::isVirtualRegister(Reg)) {
861 } else if (Register::isVirtualRegister(Reg) && MO.readsReg()) {
lib/CodeGen/SelectionDAG/FastISel.cpp 177 } else if (Register::isVirtualRegister(MO.getReg())) {
2022 if (Register::isVirtualRegister(Op)) {
2230 assert(Register::isVirtualRegister(Op0) &&
lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp 428 if (!Register::isVirtualRegister(DestReg))
449 if (!Register::isVirtualRegister(SrcReg)) {
484 if (!Register::isVirtualRegister(SrcReg)) {
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 89 if (Register::isVirtualRegister(SrcReg)) {
117 if (Register::isVirtualRegister(DestReg)) {
232 if (Register::isVirtualRegister(Reg)) {
388 if (OpRC && IIRC && OpRC != IIRC && Register::isVirtualRegister(VReg)) {
487 if (Register::isVirtualRegister(DestReg)) {
531 if (Register::isVirtualRegister(Reg))
543 if (Register::isVirtualRegister(Reg))
996 if (Register::isVirtualRegister(DestReg) && SrcVal.isMachineOpcode() &&
lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp 2365 if (Register::isVirtualRegister(Reg)) {
2386 if (Register::isVirtualRegister(Reg)) {
2955 Register::isVirtualRegister(
3002 Register::isVirtualRegister(
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp 118 if (Register::isVirtualRegister(Reg))
659 if (Register::isVirtualRegister(Reg))
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 836 if (!Register::isVirtualRegister(Regs[Part + i]) ||
951 else if (!Regs.empty() && Register::isVirtualRegister(Regs.front())) {
9873 if (Register::isVirtualRegister(Reg))
9885 if (Register::isVirtualRegister(Reg)) {
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 528 if (Register::isVirtualRegister(From) && Register::isVirtualRegister(To))
528 if (Register::isVirtualRegister(From) && Register::isVirtualRegister(To))
674 if (Register::isVirtualRegister(From) && Register::isVirtualRegister(To))
674 if (Register::isVirtualRegister(From) && Register::isVirtualRegister(To))
762 if (!Register::isVirtualRegister(DestReg))
lib/CodeGen/TailDuplicator.cpp 388 if (!Register::isVirtualRegister(Reg))
lib/CodeGen/TargetInstrInfo.cpp 449 assert(Register::isVirtualRegister(FoldReg) && "Cannot fold physregs");
677 if (Op1.isReg() && Register::isVirtualRegister(Op1.getReg()))
679 if (Op2.isReg() && Register::isVirtualRegister(Op2.getReg()))
814 if (Register::isVirtualRegister(RegA))
816 if (Register::isVirtualRegister(RegB))
818 if (Register::isVirtualRegister(RegX))
820 if (Register::isVirtualRegister(RegY))
822 if (Register::isVirtualRegister(RegC))
896 if (Register::isVirtualRegister(DefReg) && MI.getOperand(0).getSubReg() &&
lib/CodeGen/TargetRegisterInfo.cpp 96 else if (Register::isVirtualRegister(Reg)) {
145 if (Register::isVirtualRegister(Unit)) {
404 if (VRM && Register::isVirtualRegister(Phys))
510 if (!Register::isVirtualRegister(CopySrcReg))
lib/CodeGen/TwoAddressInstructionPass.cpp 430 if (LIS && Register::isVirtualRegister(Reg) && !LIS->isNotInMIMap(*MI)) {
548 while (Register::isVirtualRegister(Reg)) {
1280 assert(Register::isVirtualRegister(regB) &&
1284 if (Register::isVirtualRegister(regA))
1400 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
1485 if (Register::isVirtualRegister(DstReg))
1538 assert(Register::isVirtualRegister(RegB) &&
1559 if (Register::isVirtualRegister(RegA)) {
1580 if (Register::isVirtualRegister(RegA)) {
1600 if (Register::isVirtualRegister(RegA) && Register::isVirtualRegister(RegB))
1600 if (Register::isVirtualRegister(RegA) && Register::isVirtualRegister(RegB))
lib/CodeGen/VirtRegMap.cpp 114 if (Register::isVirtualRegister(Hint.second))
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 108 if (Register::isVirtualRegister(Reg))
115 if (Register::isVirtualRegister(Reg))
lib/Target/AArch64/AArch64CondBrTuning.cpp 81 if (!Register::isVirtualRegister(MO.getReg()))
lib/Target/AArch64/AArch64ConditionalCompares.cpp 262 if (!Register::isVirtualRegister(DstReg))
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp 149 if (!Register::isVirtualRegister(Reg) ||
lib/Target/AArch64/AArch64InstrInfo.cpp 418 while (Register::isVirtualRegister(VReg)) {
433 if (!Register::isVirtualRegister(VReg))
2830 if (Register::isVirtualRegister(SrcReg))
2840 if (Register::isVirtualRegister(SrcReg))
2961 if (Register::isVirtualRegister(DestReg))
2971 if (Register::isVirtualRegister(DestReg))
3197 if (SrcReg == AArch64::SP && Register::isVirtualRegister(DstReg)) {
3201 if (DstReg == AArch64::SP && Register::isVirtualRegister(SrcReg)) {
3246 return Register::isVirtualRegister(Reg) ? MRI.getRegClass(Reg)
3600 if (MO.isReg() && Register::isVirtualRegister(MO.getReg()))
4010 if (Register::isVirtualRegister(ResultReg))
4012 if (Register::isVirtualRegister(SrcReg0))
4014 if (Register::isVirtualRegister(SrcReg1))
4016 if (Register::isVirtualRegister(SrcReg2))
4076 if (Register::isVirtualRegister(ResultReg))
4078 if (Register::isVirtualRegister(SrcReg0))
4080 if (Register::isVirtualRegister(SrcReg1))
4082 if (Register::isVirtualRegister(VR))
4787 if (!Register::isVirtualRegister(VReg))
4823 if (!Register::isVirtualRegister(NewReg))
lib/Target/AArch64/AArch64InstructionSelector.cpp 424 if (!Register::isVirtualRegister(MO.getReg())) {
lib/Target/AArch64/AArch64StackTaggingPreRA.cpp 160 Register::isVirtualRegister(UseI->getOperand(0).getReg())) {
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 550 if (Register::isVirtualRegister(Reg)) {
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 697 if (Register::isVirtualRegister(Reg)) {
737 if (Register::isVirtualRegister(Reg)) {
1027 if (Register::isVirtualRegister(Reg)) {
lib/Target/AMDGPU/GCNRegBankReassign.cpp 296 if (Register::isVirtualRegister(Reg)) {
lib/Target/AMDGPU/GCNRegPressure.cpp 87 assert(Register::isVirtualRegister(Reg));
200 assert(MO.isDef() && MO.isReg() && Register::isVirtualRegister(MO.getReg()));
213 assert(MO.isUse() && MO.isReg() && Register::isVirtualRegister(MO.getReg()));
234 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
331 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()) || MO.isDead())
410 if (!Register::isVirtualRegister(Reg))
lib/Target/AMDGPU/R600ISelLowering.cpp 339 assert(Register::isVirtualRegister(maskedRegister));
lib/Target/AMDGPU/R600InstrInfo.cpp 100 if (I->isReg() && !Register::isVirtualRegister(I->getReg()) && I->isUse() &&
245 if (!I->isReg() || !I->isUse() || Register::isVirtualRegister(I->getReg()))
1195 if (Register::isVirtualRegister(Reg) || !IndirectRC->contains(Reg))
lib/Target/AMDGPU/R600MachineScheduler.cpp 186 return !Register::isVirtualRegister(MI->getOperand(1).getReg());
212 if (!Register::isVirtualRegister(Reg)) {
lib/Target/AMDGPU/R600RegisterInfo.cpp 96 assert(!Register::isVirtualRegister(Reg));
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 157 !Register::isVirtualRegister(MI.getOperand(i).getReg()))
173 const TargetRegisterClass *SrcRC = Register::isVirtualRegister(SrcReg)
180 const TargetRegisterClass *DstRC = Register::isVirtualRegister(DstReg)
208 if (!Register::isVirtualRegister(SrcReg) ||
209 !Register::isVirtualRegister(DstReg))
616 if (!Register::isVirtualRegister(DstReg)) {
636 if (!Register::isVirtualRegister(SrcReg)) {
718 if (Register::isVirtualRegister(MO->getReg())) {
lib/Target/AMDGPU/SIFixupVectorISel.cpp 94 if (!WOp->isReg() || !Register::isVirtualRegister(WOp->getReg()))
lib/Target/AMDGPU/SIFoldOperands.cpp 506 if (!Register::isVirtualRegister(UseReg))
948 !Register::isVirtualRegister(Op.getReg()))
1211 if (Fold.isReg() && Register::isVirtualRegister(Fold.OpToFold->getReg())) {
1506 if (OpToFold.isReg() && !Register::isVirtualRegister(OpToFold.getReg()))
1516 if (Dst.isReg() && !Register::isVirtualRegister(Dst.getReg()))
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 272 LaneBitmask Mask = Register::isVirtualRegister(Reg)
lib/Target/AMDGPU/SIISelLowering.cpp10409 !Register::isVirtualRegister(Op.getReg()) ||
lib/Target/AMDGPU/SIInstrInfo.cpp 480 const TargetRegisterClass *DstRC = Register::isVirtualRegister(Reg)
1072 if (Register::isVirtualRegister(SrcReg) && SpillSize == 4) {
1197 if (Register::isVirtualRegister(DestReg) && SpillSize == 4) {
2442 (Register::isVirtualRegister(Src0->getReg()) &&
2459 (Register::isVirtualRegister(Src1->getReg()) &&
3114 if (Register::isVirtualRegister(MO.getReg()))
3224 if (!Register::isVirtualRegister(Reg) && !RC->contains(Reg)) {
3289 if (Reg == AMDGPU::NoRegister || Register::isVirtualRegister(Reg))
3815 if (Register::isVirtualRegister(Reg))
3920 const TargetRegisterClass *RC = Register::isVirtualRegister(Reg)
4543 !Register::isVirtualRegister(MI.getOperand(i).getReg()))
4579 if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg()))
4604 if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg()))
5066 Register::isVirtualRegister(Inst.getOperand(1).getReg()) &&
6419 if (!Register::isVirtualRegister(P.Reg))
6430 if (Op1.isReg() && Register::isVirtualRegister(Op1.getReg())) {
lib/Target/AMDGPU/SILowerControlFlow.cpp 444 if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg())) {
464 (Register::isVirtualRegister(SrcOp.getReg()) || SrcOp.getReg() == Exec))
lib/Target/AMDGPU/SILowerI1Copies.cpp 99 return Register::isVirtualRegister(Reg) &&
700 if (!Register::isVirtualRegister(SrcReg) ||
745 if (!Register::isVirtualRegister(Reg))
lib/Target/AMDGPU/SIMachineScheduler.cpp 351 if (Register::isVirtualRegister(RegMaskPair.RegUnit))
379 if (Register::isVirtualRegister(Reg) &&
1693 if (!Register::isVirtualRegister(Reg))
1753 if (!Register::isVirtualRegister(Reg))
1765 if (!Register::isVirtualRegister(Reg))
1916 if (!Register::isVirtualRegister(Reg))
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 270 if ((Register::isVirtualRegister(CmpReg) && MRI.use_nodbg_empty(CmpReg)) ||
282 if (Register::isVirtualRegister(SelReg) && MRI.use_nodbg_empty(SelReg)) {
437 if (Register::isVirtualRegister(Reg)) {
lib/Target/AMDGPU/SIRegisterInfo.cpp 1245 assert(!Register::isVirtualRegister(Reg));
1692 if (Register::isVirtualRegister(Reg))
1872 if (Register::isVirtualRegister(Reg)) {
lib/Target/AMDGPU/SIRegisterInfo.h 140 if (Register::isVirtualRegister(Reg))
lib/Target/AMDGPU/SIShrinkInstructions.cpp 81 if (Register::isVirtualRegister(Reg) && MRI.hasOneUse(Reg)) {
363 if (Register::isVirtualRegister(Dest->getReg()) && SrcReg->isReg()) {
400 } else if (MO.getReg() == Reg && Register::isVirtualRegister(Reg)) {
644 if (Register::isVirtualRegister(Dest->getReg()) && Src0->isReg()) {
721 if (Register::isVirtualRegister(DstReg)) {
745 if (Register::isVirtualRegister(SReg)) {
765 if (Register::isVirtualRegister(SDst->getReg()))
773 if (Register::isVirtualRegister(Src2->getReg()))
lib/Target/AMDGPU/SIWholeQuadMode.cpp 281 if (!Register::isVirtualRegister(Reg)) {
365 if (Register::isVirtualRegister(Reg)) {
395 if (!Register::isVirtualRegister(Reg) &&
861 const TargetRegisterClass *regClass = Register::isVirtualRegister(Reg)
lib/Target/ARC/ARCOptAddrMode.cpp 142 assert(Register::isVirtualRegister(VReg) && "Expected virtual register!");
208 if (Register::isStackSlot(B) || !Register::isVirtualRegister(B)) {
lib/Target/ARM/A15SDOptimizer.cpp 138 if (Register::isVirtualRegister(Reg))
154 if (!Register::isVirtualRegister(SReg))
169 if (Register::isVirtualRegister(SReg)) {
195 if (!Register::isVirtualRegister(Reg))
217 if (!Register::isVirtualRegister(DefReg)) {
251 if (Register::isVirtualRegister(DPRReg) && Register::isVirtualRegister(SPRReg)) {
251 if (Register::isVirtualRegister(DPRReg) && Register::isVirtualRegister(SPRReg)) {
301 if (!Register::isVirtualRegister(OpReg))
345 if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
373 if (!Register::isVirtualRegister(Reg)) {
382 if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
605 if (!Register::isVirtualRegister(*I))
lib/Target/ARM/ARMBaseInstrInfo.cpp 279 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
1804 if (!MRI || !Register::isVirtualRegister(Addr0) ||
1805 !Register::isVirtualRegister(Addr1))
2179 if (!Register::isVirtualRegister(Reg))
5178 if (Register::isVirtualRegister(Reg)) {
lib/Target/ARM/ARMBaseRegisterInfo.cpp 361 Register::isVirtualRegister(Hint.second)) {
371 if (Register::isVirtualRegister(NewReg))
818 (Register::isVirtualRegister(FrameReg) || RegClass->contains(FrameReg)))
lib/Target/ARM/ARMISelLowering.cpp 2515 if (!Register::isVirtualRegister(VR))
lib/Target/ARM/MLxExpansionPass.cpp 100 if (Register::isVirtualRegister(Reg)) {
106 if (Register::isVirtualRegister(Reg)) {
156 if (Register::isVirtualRegister(SrcReg)) {
164 if (Register::isVirtualRegister(Reg)) {
170 if (Register::isVirtualRegister(Reg)) {
lib/Target/ARM/Thumb2InstrInfo.cpp 162 if (Register::isVirtualRegister(SrcReg)) {
203 if (Register::isVirtualRegister(DestReg)) {
652 (Register::isVirtualRegister(FrameReg) ||
654 if (Register::isVirtualRegister(FrameReg)) {
693 return Offset == 0 && (Register::isVirtualRegister(FrameReg) ||
lib/Target/ARM/ThumbRegisterInfo.cpp 111 (isARMLowRegister(DestReg) || Register::isVirtualRegister(DestReg)) &&
145 if (!isARMLowRegister(DestReg) && !Register::isVirtualRegister(DestReg))
lib/Target/AVR/AVRExpandPseudoInsts.cpp 877 !Register::isVirtualRegister(MO.getReg()))
lib/Target/AVR/AVRISelDAGToDAG.cpp 254 CanHandleRegImmOpt &= (Register::isVirtualRegister(Reg) ||
lib/Target/BPF/BPFMIPeephole.cpp 109 if ((Register::isVirtualRegister(Reg) &&
lib/Target/Hexagon/BitTracker.cpp 204 assert(SelfR == 0 || Register::isVirtualRegister(SelfR));
338 if (Register::isVirtualRegister(RR.Reg)) {
357 assert(Register::isVirtualRegister(RR.Reg));
380 if (!Register::isVirtualRegister(RR.Reg))
878 if (!Register::isVirtualRegister(RD.Reg))
lib/Target/Hexagon/HexagonBitSimplify.cpp 294 if (!Register::isVirtualRegister(R))
306 if (!Register::isVirtualRegister(R))
356 if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
356 if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
369 if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
369 if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
385 if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
385 if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
896 if (!Register::isVirtualRegister(RR.Reg))
927 if (!Register::isVirtualRegister(RD.Reg) ||
928 !Register::isVirtualRegister(RS.Reg))
1019 if (!Register::isVirtualRegister(R) || !isDead(R)) {
1221 if (!Register::isVirtualRegister(DefR))
1470 if (!Register::isVirtualRegister(DR))
1819 if (!Register::isVirtualRegister(Reg))
3162 if (!Register::isVirtualRegister(DefR))
lib/Target/Hexagon/HexagonBitTracker.cpp 1046 if (!Register::isVirtualRegister(R))
lib/Target/Hexagon/HexagonBlockRanges.cpp 278 assert(Register::isVirtualRegister(R.Reg));
485 if (Register::isVirtualRegister(P.first.Reg))
lib/Target/Hexagon/HexagonConstExtenders.cpp 245 llvm::Register::isVirtualRegister(Reg);
lib/Target/Hexagon/HexagonConstPropagation.cpp 211 if (!Register::isVirtualRegister(R))
218 if (!Register::isVirtualRegister(R))
626 assert(Register::isVirtualRegister(DefR.Reg));
655 if (!Register::isVirtualRegister(UseR.Reg))
697 if (!Register::isVirtualRegister(DefR.Reg))
1073 if (!Register::isVirtualRegister(R.Reg))
1929 if (!Register::isVirtualRegister(DefR.Reg))
2796 if (!Register::isVirtualRegister(R.Reg))
2835 if (!Register::isVirtualRegister(R))
3114 assert(Register::isVirtualRegister(FromReg));
3115 assert(Register::isVirtualRegister(ToReg));
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 388 if (!Register::isVirtualRegister(R))
405 if (!Register::isVirtualRegister(R))
495 if (!Register::isVirtualRegister(R))
lib/Target/Hexagon/HexagonExpandCondsets.cpp 288 assert(Register::isVirtualRegister(Reg));
367 assert(Register::isVirtualRegister(Reg));
376 if (!Register::isVirtualRegister(DR) || DR != Reg)
554 if (!Register::isVirtualRegister(R)) {
584 if (Register::isVirtualRegister(RS.Reg)) {
805 if (!Register::isVirtualRegister(RR.Reg))
1002 if (!Register::isVirtualRegister(RR.Reg))
1094 if (!Register::isVirtualRegister(RR.Reg))
lib/Target/Hexagon/HexagonFrameLowering.cpp 309 if (Register::isVirtualRegister(R))
lib/Target/Hexagon/HexagonGenInsert.cpp 611 if (Register::isVirtualRegister(R))
728 if (!Register::isVirtualRegister(R))
741 if (!Register::isVirtualRegister(R))
1481 if (!Register::isVirtualRegister(R) || !MRI->use_nodbg_empty(R)) {
lib/Target/Hexagon/HexagonGenPredicate.cpp 136 if (!Register::isVirtualRegister(R))
216 if (Register::isVirtualRegister(RD.R))
248 assert(Register::isVirtualRegister(Reg.R));
474 if (!Register::isVirtualRegister(DR.R))
476 if (!Register::isVirtualRegister(SR.R))
lib/Target/Hexagon/HexagonHardwareLoops.cpp 1434 if (!Register::isVirtualRegister(Reg))
1512 if (!Register::isVirtualRegister(R))
lib/Target/Hexagon/HexagonPeephole.cpp 142 if (Register::isVirtualRegister(DstReg) &&
143 Register::isVirtualRegister(SrcReg)) {
191 if (Register::isVirtualRegister(DstReg) &&
192 Register::isVirtualRegister(SrcReg)) {
213 if (Register::isVirtualRegister(DstReg) &&
214 Register::isVirtualRegister(SrcReg)) {
245 if (Register::isVirtualRegister(Reg0)) {
lib/Target/Hexagon/HexagonSplitDouble.cpp 214 if (!Register::isVirtualRegister(R))
262 if (!Register::isVirtualRegister(T)) {
403 assert(Register::isVirtualRegister(Reg));
608 bool isVirtReg = Register::isVirtualRegister(R);
1108 if (!Register::isVirtualRegister(R))
lib/Target/Lanai/LanaiInstrInfo.cpp 459 if (!Register::isVirtualRegister(Reg))
lib/Target/Mips/Mips16InstrInfo.cpp 361 !Register::isVirtualRegister(MO.getReg()))
lib/Target/Mips/MipsOptimizePICCall.cpp 130 if (!MO.isReg() || !MO.isUse() || !Register::isVirtualRegister(MO.getReg()))
lib/Target/NVPTX/NVPTXAsmPrinter.cpp 285 if (Register::isVirtualRegister(Reg)) {
511 if (Register::isVirtualRegister(RegNo)) {
lib/Target/NVPTX/NVPTXPeephole.cpp 84 if (Op.isReg() && Register::isVirtualRegister(Op.getReg())) {
lib/Target/PowerPC/PPCBranchCoalescing.cpp 359 Register::isVirtualRegister(Op1.getReg()) &&
360 Register::isVirtualRegister(Op2.getReg())) {
460 if (Use.isReg() && Register::isVirtualRegister(Use.getReg())) {
lib/Target/PowerPC/PPCInstrInfo.cpp 189 if (Register::isVirtualRegister(Reg)) {
1666 if (Register::isVirtualRegister(ActualSrc))
2355 if (!Register::isVirtualRegister(Reg))
2358 if (Register::isVirtualRegister(TrueReg)) {
3837 if (Register::isVirtualRegister(RegToModify)) {
4053 if (!Register::isVirtualRegister(SrcReg))
4077 if (!Register::isVirtualRegister(SrcReg))
4106 if (!Register::isVirtualRegister(SrcReg))
4131 if (!Register::isVirtualRegister(SrcReg1) ||
4132 !Register::isVirtualRegister(SrcReg2))
lib/Target/PowerPC/PPCMIPeephole.cpp 152 if (!Register::isVirtualRegister(Reg))
347 if (TrueReg1 == TrueReg2 && Register::isVirtualRegister(TrueReg1)) {
360 if (Register::isVirtualRegister(DefReg)) {
446 if (!Register::isVirtualRegister(TrueReg))
456 if (!Register::isVirtualRegister(ConvReg))
509 if (!Register::isVirtualRegister(TrueReg))
520 if (!Register::isVirtualRegister(DefsReg1) ||
521 !Register::isVirtualRegister(DefsReg2))
569 if (!Register::isVirtualRegister(NarrowReg))
613 if (!Register::isVirtualRegister(NarrowReg))
682 if (!Register::isVirtualRegister(SrcReg))
698 if (Register::isVirtualRegister(CopyReg))
929 if (NextReg == SrcReg || !Register::isVirtualRegister(NextReg))
952 if (!Register::isVirtualRegister(CndReg) || !MRI->hasOneNonDBGUse(CndReg))
962 if (MO.isReg() && !Register::isVirtualRegister(MO.getReg()))
1336 if (!Register::isVirtualRegister(SrcReg))
1416 if (!Register::isVirtualRegister(SrcReg))
1432 if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg()))
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 538 if (!Register::isVirtualRegister(Reg))
546 if (!Register::isVirtualRegister(CopySrc)) {
lib/Target/PowerPC/PPCVSXCopy.cpp 53 if (Register::isVirtualRegister(Reg)) {
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 130 if (Register::isVirtualRegister(AddendSrcReg)) {
211 if (Register::isVirtualRegister(AddendSrcReg) &&
317 if (!Register::isVirtualRegister(AddendSrcReg))
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 161 if (Register::isVirtualRegister(Reg))
569 if (!Register::isVirtualRegister(CopySrcReg)) {
608 if (!Register::isVirtualRegister(Reg)) {
lib/Target/SystemZ/SystemZInstrInfo.cpp 1170 (Register::isVirtualRegister(DstReg) ? VRM->getPhys(DstReg) : DstReg);
1176 Register::isVirtualRegister(SrcReg) &&
lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp 71 assert(Register::isVirtualRegister(RegNo) &&
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp 63 Register::isVirtualRegister(DestReg)
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 440 if (!Register::isVirtualRegister(DefReg) ||
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 95 if (Register::isVirtualRegister(OtherMOReg)) {
lib/Target/WebAssembly/WebAssemblyUtilities.cpp 36 return Register::isVirtualRegister(Reg) && MFI.isVRegStackified(Reg);
lib/Target/X86/X86CallFrameOptimization.cpp 611 if (!Register::isVirtualRegister(Reg))
lib/Target/X86/X86CmovConversion.cpp 440 auto &RDM = RegDefMaps[Register::isVirtualRegister(Reg)];
460 RegDefMaps[Register::isVirtualRegister(Reg)][Reg] = &MI;
lib/Target/X86/X86DomainReassignment.cpp 439 if (!Register::isVirtualRegister(Reg))
597 if (!Register::isVirtualRegister(DefReg)) {
lib/Target/X86/X86FlagsCopyLowering.cpp 726 Register::isVirtualRegister(MI.getOperand(0).getReg())) {
lib/Target/X86/X86ISelLowering.cpp 4235 if (!Register::isVirtualRegister(VR))
lib/Target/X86/X86InstrInfo.cpp 468 if (!Register::isVirtualRegister(BaseReg))
724 if (Register::isVirtualRegister(NewSrc) &&
928 if (Register::isVirtualRegister(Src.getReg()) &&
4349 if (Register::isVirtualRegister(Reg)) {
4644 if (!Register::isVirtualRegister(Reg))
lib/Target/X86/X86SpeculativeLoadHardening.cpp 2214 if (!Register::isVirtualRegister(UseDefReg) ||
2284 assert(Register::isVirtualRegister(Reg) && "Cannot harden a physical register!");