reference, declaration → definition definition → references, declarations, derived classes, virtual overrides reference to multiple definitions → definitions unreferenced |
860 SU = nullptr; 867 bool isValid() const { return SU; } 872 SU = Best.SU; 872 SU = Best.SU; 959 TopCand.SU = nullptr; 967 BotCand.SU = nullptr;lib/CodeGen/MachineScheduler.cpp
2454 const MCSchedClassDesc *SC = DAG->getSchedClass(SU); 2615 Latency = Cand.SU->getDepth(); 2618 Latency = Cand.SU->getHeight(); 2621 Latency = Cand.SU->getHeight(); 2624 Latency = Cand.SU->getDepth(); 2627 dbgs() << " Cand SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason); 2683 if (Cand.SU->getDepth() > Zone.getScheduledLatency()) { 2684 if (tryLess(TryCand.SU->getDepth(), Cand.SU->getDepth(), 2684 if (tryLess(TryCand.SU->getDepth(), Cand.SU->getDepth(), 2688 if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(), 2688 if (tryGreater(TryCand.SU->getHeight(), Cand.SU->getHeight(), 2692 if (Cand.SU->getHeight() > Zone.getScheduledLatency()) { 2693 if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(), 2693 if (tryLess(TryCand.SU->getHeight(), Cand.SU->getHeight(), 2697 if (tryGreater(TryCand.SU->getDepth(), Cand.SU->getDepth(), 2697 if (tryGreater(TryCand.SU->getDepth(), Cand.SU->getDepth(), 2740 TopCand.SU = nullptr; 2741 BotCand.SU = nullptr; 2952 Cand.SU = SU; 2957 Cand.SU->getInstr(), 2964 Cand.SU->getInstr(), 2965 &DAG->getPressureDiff(Cand.SU), 2971 Cand.SU->getInstr(), 2972 DAG->getPressureDiff(Cand.SU), 2980 << " Try SU(" << Cand.SU->NodeNum << ") " 3005 if (tryGreater(biasPhysReg(TryCand.SU, TryCand.AtTop), 3006 biasPhysReg(Cand.SU, Cand.AtTop), TryCand, Cand, PhysReg)) 3038 if (tryLess(Zone->getLatencyStallCycles(TryCand.SU), 3039 Zone->getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall)) 3053 if (tryGreater(TryCand.SU == TryCandNextClusterSU, 3054 Cand.SU == CandNextClusterSU, 3060 if (tryLess(getWeakLeft(TryCand.SU, TryCand.AtTop), 3061 getWeakLeft(Cand.SU, Cand.AtTop), 3091 if ((Zone->isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum) 3091 if ((Zone->isTop() && TryCand.SU->NodeNum < Cand.SU->NodeNum) 3092 || (!Zone->isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) { 3092 || (!Zone->isTop() && TryCand.SU->NodeNum > Cand.SU->NodeNum)) { 3153 if (!BotCand.isValid() || BotCand.SU->isScheduled || 3165 assert(TCand.SU == BotCand.SU && 3165 assert(TCand.SU == BotCand.SU && 3173 if (!TopCand.isValid() || TopCand.SU->isScheduled || 3185 assert(TCand.SU == TopCand.SU && 3185 assert(TCand.SU == TopCand.SU && 3204 return Cand.SU; 3224 SU = TopCand.SU; 3235 SU = BotCand.SU; 3370 if (tryLess(Top.getLatencyStallCycles(TryCand.SU), 3371 Top.getLatencyStallCycles(Cand.SU), TryCand, Cand, Stall)) 3375 if (tryGreater(TryCand.SU == DAG->getNextClusterSucc(), 3376 Cand.SU == DAG->getNextClusterSucc(), 3395 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) 3395 if (TryCand.SU->NodeNum < Cand.SU->NodeNum) 3403 TryCand.SU = SU; 3434 SU = TopCand.SU;lib/Target/AMDGPU/GCNSchedStrategy.cpp
67 Cand.SU = SU; 192 if (!BotCand.isValid() || BotCand.SU->isScheduled || 204 assert(TCand.SU == BotCand.SU && 204 assert(TCand.SU == BotCand.SU && 212 if (!TopCand.isValid() || TopCand.SU->isScheduled || 224 assert(TCand.SU == TopCand.SU && 224 assert(TCand.SU == TopCand.SU && 264 return Cand.SU; 284 SU = TopCand.SU; 294 SU = BotCand.SU;lib/Target/PowerPC/PPCMachineScheduler.cpp
31 if (isADDIInstr(*FirstCand.SU->getInstr()) && 32 SecondCand.SU->getInstr()->mayLoad()) { 36 if (FirstCand.SU->getInstr()->mayLoad() && 37 isADDIInstr(*SecondCand.SU->getInstr())) {