reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/MachineOperand.h

  758     Op.setImm(Val);

lib/CodeGen/GlobalISel/LegalizerHelper.cpp

 1387   MI.getOperand(2).setImm((WideTy.getSizeInBits() / SrcTy.getSizeInBits()) *

lib/CodeGen/MachinePipeliner.cpp

 2133   NewMI->getOperand(OffsetPosLd).setImm(LoadOffset + StoreOffset);
 2175       NewMI->getOperand(OffsetPos).setImm(NewOffset);
 2782             NewMI->getOperand(OffsetPos).setImm(NewOffset);

lib/CodeGen/ModuloSchedule.cpp

 1012     NewMI->getOperand(OffsetPos).setImm(NewOffset);

lib/CodeGen/PeepholeOptimizer.cpp

 1009     CopyLike.getOperand(CurrentSrcIdx + 1).setImm(NewSubReg);

lib/CodeGen/PrologEpilogInserter.cpp

 1257         Offset.setImm(Offset.getImm() + refOffset + SPAdj);

lib/CodeGen/TargetInstrInfo.cpp

  338         MO.setImm(Pred[j].getImm());

lib/Target/AArch64/AArch64CallLowering.cpp

  896     MIB->getOperand(1).setImm(FPDiff);

lib/Target/AArch64/AArch64FrameLowering.cpp

  619     ImmOpnd->setImm(ImmOpnd->getImm() + LocalStackSize);
  772   OffsetOpnd.setImm(OffsetOpnd.getImm() + LocalStackSize / Scale);

lib/Target/AArch64/AArch64InstrInfo.cpp

  300     Cond[0].setImm(AArch64CC::getInvertedCondCode(CC));
  307       Cond[1].setImm(AArch64::CBNZW);
  310       Cond[1].setImm(AArch64::CBZW);
  313       Cond[1].setImm(AArch64::CBNZX);
  316       Cond[1].setImm(AArch64::CBZX);
  319       Cond[1].setImm(AArch64::TBNZW);
  322       Cond[1].setImm(AArch64::TBZW);
  325       Cond[1].setImm(AArch64::TBNZX);
  328       Cond[1].setImm(AArch64::TBZX);
 5527     StackOffsetOperand.setImm(NewImm);

lib/Target/AArch64/AArch64InstructionSelector.cpp

 1651     I.getOperand(3).setImm((DstSize - LSB) % DstSize);
 1937     I.getOperand(2).setImm(AArch64_AM::encodeLogicalImmediate(Mask, 64));

lib/Target/AMDGPU/AMDILCFGStructurizer.cpp

  437         I->getOperand(2).setImm(R600::PRED_SETNE_INT);
  440         I->getOperand(2).setImm(R600::PRED_SETE_INT);
  443         I->getOperand(2).setImm(R600::PRED_SETNE);
  446         I->getOperand(2).setImm(R600::PRED_SETE);

lib/Target/AMDGPU/R600ClauseMergePass.cpp

  111     CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI));
  162     RootCFAlu.getOperand(Mode0Idx).setImm(
  164     RootCFAlu.getOperand(KBank0Idx).setImm(
  167         .setImm(LatrCFAlu.getOperand(KBank0LineIdx).getImm());
  170     RootCFAlu.getOperand(Mode1Idx).setImm(
  172     RootCFAlu.getOperand(KBank1Idx).setImm(
  175         .setImm(LatrCFAlu.getOperand(KBank1LineIdx).getImm());
  177   RootCFAlu.getOperand(CntIdx).setImm(CumuledInsts);

lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp

  464     ClauseHead.getOperand(7).setImm(ClauseContent.size() - 1);
  482     Clause.first->getOperand(0).setImm(0);
  493     MI.getOperand(0).setImm(Addr + MI.getOperand(0).getImm());
  637           IfOrElseInst->getOperand(1).setImm(1);

lib/Target/AMDGPU/R600InstrInfo.cpp

  773       PredSet->getOperand(2).setImm(Cond[1].getImm());
  789     PredSet->getOperand(2).setImm(Cond[1].getImm());
  937     MO.setImm(R600::PRED_SETNE_INT);
  940     MO.setImm(R600::PRED_SETE_INT);
  943     MO.setImm(R600::PRED_SETNE);
  946     MO.setImm(R600::PRED_SETE);
  976     MI.getOperand(8).setImm(0);
 1360   MIB->getOperand(20).setImm(0);
 1393   MI.getOperand(Idx).setImm(Imm);
 1478       FlagOp.setImm(1);
 1482       FlagOp.setImm(FlagOp.getImm() | (Flag << (NUM_MO_FLAGS * Operand)));
 1491     FlagOp.setImm(0);
 1496     FlagOp.setImm(InstFlags);

lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp

  275         MI.getOperand(i + Offset).setImm(RemapChan[j].second - 1);

lib/Target/AMDGPU/R600Packetizer.cpp

  223     MI->getOperand(LastOp).setImm(Bit);
  304         MI->getOperand(Op).setImm(BS[i]);
  308       MI.getOperand(Op).setImm(BS.back());

lib/Target/AMDGPU/SIFoldOperands.cpp

  225             Mod.setImm(Mod.getImm() | SISrcMods::OP_SEL_0);
  226             Mod.setImm(Mod.getImm() & ~SISrcMods::OP_SEL_1);
  230           Mod.setImm(Mod.getImm() & ~SISrcMods::OP_SEL_1);
 1314   DefClamp->setImm(1);
 1436   DefOMod->setImm(OMod);

lib/Target/AMDGPU/SIInsertWaitcnts.cpp

 1120           II->getOperand(0).setImm(NewEnc);
 1135           II->getOperand(1).setImm(Wait.VsCnt);

lib/Target/AMDGPU/SIInstrInfo.cpp

 1637   Src1Mods->setImm(Src0ModsVal);
 1638   Src0Mods->setImm(Src1ModsVal);
 2110     Cond[0].setImm(-Cond[0].getImm());

lib/Target/AMDGPU/SILoadStoreOptimizer.cpp

 1433   TII->getNamedOperand(MI, AMDGPU::OpName::offset)->setImm(NewOffset);

lib/Target/AMDGPU/SIMemoryLegalizer.cpp

  113   Bit.setImm(1);

lib/Target/AMDGPU/SIPeepholeSDWA.cpp

  436     SrcSel->setImm(getSrcSel());
  437     SrcMods->setImm(getSrcMods(TII, Src));
  481   DstSel->setImm(getDstSel());
  484   DstUnused->setImm(getDstUnused());

lib/Target/AMDGPU/SIRegisterInfo.cpp

  410   OffsetOp->setImm(NewOffset);

lib/Target/AMDGPU/SIShrinkInstructions.cpp

  378           SrcImm->setImm(NewImm);
  584             Src.setImm(ReverseImm);
  618           NextMI.getOperand(0).setImm(Nop0 + Nop1 - 1);
  678             Src.setImm(ReverseImm);

lib/Target/AMDGPU/SIWholeQuadMode.cpp

  763         MI.getOperand(3).setImm(1);

lib/Target/ARC/ARCInstrInfo.cpp

  353   Cond[2].setImm(GetOppositeBranchCondition((ARCCC::CondCode)Cond[2].getImm()));

lib/Target/ARC/ARCOptAddrMode.cpp

  384     MI->getOperand(OffPos).setImm(NewOffset);

lib/Target/ARM/ARMBaseInstrInfo.cpp

  478   Cond[0].setImm(ARMCC::getOppositeCondition(CC));
  512     PMO.setImm(Pred[0].getImm());
 1733       I->getOperand(2).setImm(PCLabelId);
 2167         .setImm(ARMCC::getOppositeCondition(CC));
 3176     OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);

lib/Target/ARM/ARMConstantIslandPass.cpp

 1688         MI->getOperand(1).setImm(CC);

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

  515           MO.setImm(Offset);
  531           MO.setImm(Offset);

lib/Target/ARM/Thumb2InstrInfo.cpp

   95           MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);

lib/Target/AVR/AVRInstrInfo.cpp

  471   Cond[0].setImm(getOppositeCondition(CC));

lib/Target/Hexagon/HexagonConstExtenders.cpp

 1878       ImmOp.setImm(ImmOp.getImm() + Diff);

lib/Target/Hexagon/HexagonHardwareLoops.cpp

 1580     MO.setImm(Val);

lib/Target/Hexagon/HexagonInstrInfo.cpp

  735       Loop->getOperand(1).setImm(TripCount);
 1533   Cond[0].setImm(NewOpcode);
 4144   Cond[0].setImm(Opc);
 4436     Operand.setImm(Operand.getImm() | memShufDisabledMask);

lib/Target/Hexagon/HexagonOptAddrMode.cpp

  424   OffsetOp.setImm(ImmOp.getImm() + OffsetOp.getImm());

lib/Target/Hexagon/HexagonRDFOpt.cpp

  273   MI.getOperand(OpNum+2).setImm(0);

lib/Target/Hexagon/HexagonVLIWPacketizer.cpp

  484     Off.setImm(NewOff);
  503   Off.setImm(Off.getImm() + FrameSize + HEXAGON_LRFP_SIZE);
  537   MI.getOperand(OPI).setImm(Offset + Incr);
  548   MI.getOperand(OP).setImm(ChangedOffset);

lib/Target/Lanai/LanaiInstrInfo.cpp

  653   Condition[0].setImm(getOppositeCondition(BranchCond));

lib/Target/Lanai/LanaiRegisterInfo.cpp

  217         MI.getOperand(3).setImm(LPAC::SUB);

lib/Target/MSP430/MSP430InstrInfo.cpp

  159   Cond[0].setImm(CC);

lib/Target/Mips/MipsInstrInfo.cpp

  186   Cond[0].setImm(getOppositeBranchOpc(Cond[0].getImm()));

lib/Target/PowerPC/PPCInstrInfo.cpp

  447   MI.getOperand(4).setImm((ME + 1) & 31);
  448   MI.getOperand(5).setImm((MB - 1) & 31);
 1317     Cond[0].setImm(Cond[0].getImm() == 0 ? 1 : 0);
 1320     Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
 1962         MI->getOperand(2).setImm(Mask);
 1971         MI->getOperand(2).setImm(Mask);
 1999     PredsToUpdate[i].first->setImm(PredsToUpdate[i].second);
 2624   ADDIMI->getOperand(2).setImm(OffsetAddi + OffsetImm);
 2966           DefMI->getOperand(1).setImm(NewImm);
 4211       LoopCount->getOperand(1).setImm(TripCount);

lib/Target/PowerPC/PPCMIPeephole.cpp

  409                 MI.getOperand(3).setImm(3 - Immed);
  500             MI.getOperand(2).setImm(NewElem);
 1259       BI1->getOperand(0).setImm(NewPredicate1);
 1262       BI2->getOperand(0).setImm(NewPredicate2);
 1265       CMPI1->getOperand(2).setImm(NewImm1);
 1278         CMPI2->getOperand(2).setImm(NewImm2);
 1375   MI.getOperand(2).setImm(NewSH);
 1376   MI.getOperand(3).setImm(NewMB);

lib/Target/PowerPC/PPCVSXSwapRemoval.cpp

  846       MI->getOperand(2).setImm(EltNo);
  848       MI->getOperand(1).setImm(EltNo);
  870     MI->getOperand(3).setImm(Selector);

lib/Target/RISCV/RISCVInstrInfo.cpp

  417   Cond[0].setImm(getOppositeBranchOpcode(Cond[0].getImm()));

lib/Target/Sparc/SparcInstrInfo.cpp

  301   Cond[0].setImm(GetOppositeBranchCondition(CC));

lib/Target/SystemZ/SystemZElimCompare.cpp

  372       AlterMasks[I]->setImm(CCValues);
  375         AlterMasks[I + 1]->setImm((CCMask & ReusableCCMask) |

lib/Target/SystemZ/SystemZISelLowering.cpp

 7481   MI.getOperand(2).setImm(Control);

lib/Target/SystemZ/SystemZInstrInfo.cpp

   98   LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
  128   OffsetMO.setImm(Offset);
  144     MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
  295     WorkingMI.getOperand(4).setImm(CCMask ^ CCValid);
  473   Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
 1378       MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);

lib/Target/SystemZ/SystemZShortenInst.cpp

  102     MI.getOperand(1).setImm(Imm >> 16);
  352         ImmMO.setImm(ImmMO.getImm() & 0xfff);

lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp

 1251         EndToBegin[&MI]->getOperand(0).setImm(int32_t(RetType));

lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp

   82       MI.getOperand(OffsetOperandNum).setImm(Offset);
  103           ImmMO.setImm(ImmMO.getImm() + uint32_t(FrameOffset));

lib/Target/WebAssembly/WebAssemblySetP2AlignOperands.cpp

   74   MI.getOperand(OperandNo).setImm(P2Align);

lib/Target/X86/X86EvexToVex.cpp

  160     Imm.setImm(Imm.getImm() * Scale);
  177     Imm.setImm(0x20 | ((ImmVal & 2) << 3) | (ImmVal & 1));

lib/Target/X86/X86FlagsCopyLowering.cpp

  850       .setImm(Inverted ? X86::COND_E : X86::COND_NE);
  872   JmpI.getOperand(1).setImm(Inverted ? X86::COND_E : X86::COND_NE);

lib/Target/X86/X86InstrBuilder.h

  136   MI->getOperand(Operand + 1).setImm(1);

lib/Target/X86/X86InstrInfo.cpp

 1438   MI.getOperand(MI.getNumOperands()-1).setImm(NewImm);
 1557     WorkingMI.getOperand(3).setImm(Size - Amt);
 1623     WorkingMI.getOperand(3).setImm(Mask ^ Imm);
 1643       WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(AltImm);
 1702     WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
 1734     WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
 1746     WorkingMI.getOperand(3).setImm(Imm);
 1767     WorkingMI.getOperand(MI.getNumOperands() - 1).setImm(Imm);
 1778     WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
 1809     WorkingMI.getOperand(OpNo).setImm(X86::GetOppositeBranchCondition(CC));
 2661     Cond[0].setImm(BranchCode);
 3824         .setImm(Op.second);
 4755         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
 5996   Cond[0].setImm(GetOppositeBranchCondition(CC));
 6725       MI.getOperand(NumOperands - 1).setImm(NewImm & 255);
 6810       MI.getOperand(3).setImm(NewImm);

lib/Target/X86/X86InstrInfo.h

  167       I.getOperand(2).setImm(V);
  169       I.getOperand(1).setImm(V);

lib/Target/X86/X86InstructionSelector.cpp

 1189   I.getOperand(2).setImm(Index);
 1323   I.getOperand(3).setImm(Index);

lib/Target/X86/X86OptimizeLEAs.cpp

  645             Op.setImm(Op.getImm() + AddrDispShift);

lib/Target/XCore/XCoreInstrInfo.cpp

  406   Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm()));