|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/LiveRegUnits.h 66 assert(O->isUse() && "Reg operand not a def and not a use");
include/llvm/CodeGen/MachineInstr.h 1382 if (!MO.isReg() || !MO.isUse() || !MO.isTied())
include/llvm/CodeGen/MachineOperand.h 453 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
include/llvm/CodeGen/MachineRegisterInfo.h 980 if ((!ReturnUses && op->isUse()) ||
994 if (Op->isUse())
1086 if ((!ReturnUses && op->isUse()) ||
1100 if (Op->isUse())
lib/CodeGen/AggressiveAntiDepBreaker.cpp 473 if (!MO.isReg() || !MO.isUse()) continue;
lib/CodeGen/BranchFolding.cpp 1885 if (MO.isUse()) {
1918 if (!MO.isReg() || MO.isUse())
1951 if (MO.isUse()) {
2069 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
lib/CodeGen/BreakFalseDeps.cpp 205 if (MO.isUse())
lib/CodeGen/CriticalAntiDepBreaker.cpp 242 if (MO.isUse() && Special) {
308 if (!MO.isUse()) continue;
618 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) {
lib/CodeGen/DeadMachineInstructionElim.cpp 161 if (MO.isReg() && MO.isUse()) {
lib/CodeGen/DetectDeadLanes.cpp 467 if (!MO.isUse())
lib/CodeGen/ExecutionDomainFix.cpp 244 if (MO.isUse())
lib/CodeGen/ExpandPostRAPseudos.cpp 79 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) &&
lib/CodeGen/GlobalISel/Utils.cpp 56 if (RegMO.isUse()) {
92 assert((!isTargetSpecificOpcode(II.getOpcode()) || RegMO.isUse()) &&
149 if (MO.isUse()) {
lib/CodeGen/ImplicitNullChecks.cpp 645 if (MO.isUse()) {
lib/CodeGen/InlineSpiller.cpp 559 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
624 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
852 if (MO->isUse())
1045 if (MO.isUse()) {
lib/CodeGen/LiveDebugValues.cpp 864 if (!MO.isReg() || !MO.isUse()) {
lib/CodeGen/LiveIntervals.cpp 781 if (MO.isUse()) {
981 if (MO.isUse()) {
1065 if (MO->isReg() && MO->isUse())
1366 if (MO->isReg() && !MO->isUse())
1562 } else if (MO.isUse()) {
lib/CodeGen/LivePhysRegs.cpp 99 assert(O->isUse());
lib/CodeGen/LiveRangeCalc.cpp 168 if (MO.isUse())
lib/CodeGen/LiveRangeShrink.cpp 143 if (MO.isUse())
lib/CodeGen/LiveVariables.cpp 524 if (MO.isUse()) {
lib/CodeGen/MIRParser/MIParser.cpp 360 assert(Operand.isReg() && Operand.isUse() &&
lib/CodeGen/MachineBasicBlock.cpp 909 !OI->isUse() || !OI->isKill() || OI->isUndef())
lib/CodeGen/MachineCSE.cpp 168 if (!MO.isReg() || !MO.isUse())
241 if (MO.isUse())
466 if (MO.isReg() && MO.isUse() && Register::isVirtualRegister(MO.getReg())) {
lib/CodeGen/MachineCombiner.cpp 173 if (!MO.isUse())
lib/CodeGen/MachineCopyPropagation.cpp 373 MIUse.isUse() && TRI->regsOverlap(Use.getReg(), MIUse.getReg()))
lib/CodeGen/MachineInstr.cpp 280 if (NewMO->isUse()) {
847 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx))
934 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
947 if (!MO.isReg() || !MO.isUse())
975 if (MO.isUse())
1054 assert(UseMO.isUse() && "UseIdx must be a use operand");
1086 if (MO.isUse())
1091 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1)
1134 if (MO.isReg() && MO.isUse())
1388 if (!MO.isReg() || MO.isUse())
1794 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
1855 if (!MO.isReg() || !MO.isUse() || !MO.isKill())
lib/CodeGen/MachineLICM.cpp 1017 if (MO.isUse()) {
1038 if (!MO.isUse())
1104 if (!MO.isReg() || !MO.isUse())
lib/CodeGen/MachineOperand.cpp 129 assert(isUse() && "Reg is not def or use");
lib/CodeGen/MachinePipeliner.cpp 795 } else if (MOI->isUse()) {
1555 if (MO.isReg() && MO.isUse()) {
2494 } else if (MO.isUse() && Writes && stageScheduled(*I) == StageInst1) {
2503 } else if (MO.isUse() && Writes && stageScheduled(*I) > StageInst1) {
2511 } else if (MO.isUse() && Writes && stageScheduled(*I) < StageInst1) {
2516 } else if (MO.isUse() && stageScheduled(*I) == StageInst1 &&
2769 if (MO.isReg() && MO.isUse() && MO.getReg() == OverlapReg) {
lib/CodeGen/MachineScheduler.cpp 935 if (TrackLaneMasks && !MO.isUse())
lib/CodeGen/MachineSink.cpp 440 if (!MO.isReg() || !MO.isUse())
645 if (MO.isUse()) {
657 if (MO.isUse()) continue;
976 if (MO.isReg() && MO.isUse())
1202 } else if (MO.isUse()) {
lib/CodeGen/MachineVerifier.cpp 1677 if (!MRI->isSSA() && MO->isUse() &&
1706 if (MI->isDebugValue() && MO->isUse() && !MO->isDebug()) {
lib/CodeGen/ModuloSchedule.cpp 986 if (MO.isReg() && MO.isUse())
1038 } else if (MO.isUse()) {
lib/CodeGen/ProcessImplicitDefs.cpp 69 if (MO.isReg() && MO.isUse() && MO.readsReg())
109 if (MO.isUse())
lib/CodeGen/ReachingDefAnalysis.cpp 108 if (MO.isUse())
lib/CodeGen/RegAllocFast.cpp 371 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) {
796 if (LRI->LastUse != &MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse())
823 if (MO.isUse())
895 if (MO.isEarlyClobber() || (MO.isUse() && MO.isTied()) ||
925 if (MO.isUse()) {
1050 if (MO.isUse()) {
1062 if (MO.isUse()) {
1100 if (MO.isUse()) {
1124 if (!MO.isReg() || !MO.isUse())
lib/CodeGen/RegisterCoalescer.cpp 1555 if (MO.isReg() && MO.isUse())
1705 if (SubIdx != 0 && MO.isUse() && MRI->shouldTrackSubRegLiveness(DstReg)) {
lib/CodeGen/RegisterPressure.cpp 503 if (MO.isUse()) {
535 if (MO.isUse()) {
lib/CodeGen/RegisterScavenging.cpp 140 if (MO.isUse()) {
210 if (MO.isUse()) {
544 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
lib/CodeGen/ScheduleDAGInstrs.cpp 298 SDep::Kind Kind = MO.isUse() ? SDep::Anti : SDep::Output;
856 if (!MO.isReg() || !MO.isUse())
lib/CodeGen/SplitKit.cpp 1363 if (MO.isUse())
lib/CodeGen/TargetInstrInfo.cpp 626 assert(MI.getOperand(OpIdx).isUse() && "Folding load into def!");
933 if (MO.isUse()) {
954 if (MO.isUse())
lib/CodeGen/TwoAddressInstructionPass.cpp 236 if (MO.isUse() && MOReg != SavedReg)
395 if (MO.isUse() && DI->second < LastUse)
505 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
1096 if (MO.isUse()) {
1135 if (MO.isUse()) {
1401 if (MO.isUse()) {
1480 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid");
1592 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1617 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1657 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
lib/CodeGen/VirtRegMap.cpp 542 if (MO.isUse()) {
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 554 if (U.isReg() && U.isUse() && Substs.find(U.getReg()) != Substs.end()) {
lib/Target/AArch64/AArch64CollectLOH.cpp 535 assert(Op.isReg() && Op.isUse() && "Expected reg use");
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 99 if (MO.isUse())
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 862 if (RegOp0.isUse()) {
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 965 assert(MI.getOperand(Op).isUse());
lib/Target/AMDGPU/GCNRegPressure.cpp 213 assert(MO.isUse() && MO.isReg() && Register::isVirtualRegister(MO.getReg()));
236 if (!MO.isUse() || !MO.readsReg())
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 314 if (MO.isUse()) {
lib/Target/AMDGPU/R600InstrInfo.cpp 100 if (I->isReg() && !Register::isVirtualRegister(I->getReg()) && I->isUse() &&
245 if (!I->isReg() || !I->isUse() || Register::isVirtualRegister(I->getReg()))
lib/Target/AMDGPU/SIInstrInfo.cpp 3050 if (Use.isUse() && Use.getReg() == AMDGPU::VCC) {
3111 if (!MO.isUse())
3378 if (!TiedMO.isReg() || !TiedMO.isImplicit() || !TiedMO.isUse()) {
3590 if (!Dst->isUse()) {
3606 if (!ImpUse.isReg() || !ImpUse.isUse() ||
4423 if (MO.isReg() && MO.isUse()) {
lib/Target/AMDGPU/SILowerControlFlow.cpp 463 if (SrcOp.isReg() && SrcOp.isUse() &&
lib/Target/AMDGPU/SILowerI1Copies.cpp 776 if (MO.isUse())
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 280 if (To.isUse()) {
lib/Target/AMDGPU/SIWholeQuadMode.cpp 273 if (!Use.isReg() || !Use.isUse())
lib/Target/ARC/ARCOptAddrMode.cpp 406 if (!O.isReg() || !O.isUse())
lib/Target/ARM/A15SDOptimizer.cpp 192 if ((!MO.isReg()) || (!MO.isUse()))
404 if (!MO.isReg() || !MO.isUse())
lib/Target/ARM/ARMBaseInstrInfo.cpp 288 if (MO.isUse() && MO.isKill()) {
685 if (!MO.isReg() || MO.isUndef() || MO.isUse())
lib/Target/ARM/ARMConstantIslandPass.cpp 2066 if (MO.isUse() && MO.getReg() == BaseReg) {
2085 if (MO.isUse() && MO.getReg() == EntryReg)
2146 if (MO.isUse() && MO.getReg() == EntryReg)
lib/Target/ARM/ARMExpandPseudoInsts.cpp 99 if (MO.isUse())
lib/Target/ARM/ARMISelLowering.cpp10757 if (op.isReg() && op.isUse()) {
lib/Target/ARM/ARMLowOverheadLoops.cpp 136 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
lib/Target/ARM/Thumb2ITBlockPass.cpp 93 if (MO.isUse())
lib/Target/ARM/Thumb2SizeReduction.cpp 301 if (!MO.isReg() || MO.isUndef() || MO.isUse())
975 if (!MO.isReg() || MO.isUndef() || MO.isUse())
lib/Target/BPF/BPFMIChecking.cpp 115 if (!MO.isReg() || MO.isUse())
lib/Target/Hexagon/BitTracker.cpp 856 if (!MO.isReg() || !MO.isUse())
lib/Target/Hexagon/HexagonBitSimplify.cpp 303 if (!Op.isReg() || !Op.isUse())
3093 if (!Op.isUse())
lib/Target/Hexagon/HexagonBlockRanges.cpp 321 if (!Op.isReg() || !Op.isUse() || Op.isUndef())
lib/Target/Hexagon/HexagonConstExtenders.cpp 1925 if (!Op.isReg() || !Op.isUse() ||
lib/Target/Hexagon/HexagonConstPropagation.cpp 2793 if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
2814 if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
3095 if (MO.isReg() && MO.isUse())
lib/Target/Hexagon/HexagonCopyToCombine.cpp 409 if (!Op.isReg() || !Op.isUse() || !Op.getReg())
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 402 if (!MO.isReg() || !MO.isUse())
lib/Target/Hexagon/HexagonExpandCondsets.cpp 320 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg ||
1284 if (Op.isReg() && Op.isUse())
lib/Target/Hexagon/HexagonGenInsert.cpp 738 if (!MO.isReg() || !MO.isUse())
lib/Target/Hexagon/HexagonGenMux.cpp 365 if (!Op.isReg() || !Op.isUse())
lib/Target/Hexagon/HexagonGenPredicate.cpp 258 assert(DefI->getOperand(0).isDef() && DefI->getOperand(1).isUse());
354 if (MO.isReg() && MO.isUse())
375 if (!MO.isReg() || !MO.isUse())
lib/Target/Hexagon/HexagonHardwareLoops.cpp 1343 if (MO.isReg() && MO.isUse()) {
1725 if (MO.isUse()) {
lib/Target/Hexagon/HexagonInstrInfo.cpp 200 if (MO.isUse())
2955 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
lib/Target/Hexagon/HexagonNewValueJump.cpp 177 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) {
652 if (!MO.isReg() || !MO.isUse())
659 if (!Op.isReg() || !Op.isUse() || !Op.isKill())
lib/Target/Hexagon/HexagonOptAddrMode.cpp 756 if (op.isReg() && op.isUse() && DefR == op.getReg())
lib/Target/Hexagon/HexagonSplitDouble.cpp 1080 if (!Op.isReg() || !Op.isUse() || !Op.getSubReg())
1105 if (!Op.isReg() || !Op.isUse())
lib/Target/Hexagon/HexagonSubtarget.cpp 242 if (MO.isUse() && !MI->isCopy() &&
352 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) {
435 if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) {
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 581 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
803 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
947 if (Op.isReg() && Op.getReg() && Op.isUse() &&
lib/Target/Hexagon/RDFGraph.cpp 1272 if (!Op.isReg() || Op.getReg() == 0 || !Op.isUse() || Op.isUndef())
1366 if (!Op.isReg() || !Op.isUse())
lib/Target/Hexagon/RDFLiveness.cpp 899 if (!Op.isReg() || !Op.isUse() || Op.isUndef())
lib/Target/Lanai/LanaiDelaySlotFiller.cpp 215 if (MO.isUse()) {
241 else if (MO.isUse())
lib/Target/Mips/MipsOptimizePICCall.cpp 130 if (!MO.isReg() || !MO.isUse() || !Register::isVirtualRegister(MO.getReg()))
lib/Target/PowerPC/PPCBranchCoalescing.cpp 347 && !(Op1.isUse() && MRI->isConstantPhysReg(Op1.getReg()))) {
lib/Target/PowerPC/PPCInstrInfo.cpp 2395 if (MO.isReg() && MO.isUse() && !MO.isImplicit()) {
2468 if (MO.isReg() && MO.isUse() && MO.isKill() &&
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 614 if (!MO.isUse())
lib/Target/RISCV/RISCVISelLowering.cpp 1281 return MO.isReg() && MO.isUse() && SelectDests.count(MO.getReg());
lib/Target/Sparc/DelaySlotFiller.cpp 263 if (MO.isUse()) {
304 assert(Reg.isUse() && "CALL first operand is not a use.");
311 assert(Operand1.isUse() && "CALLrr second operand is not a use.");
332 if (MO.isUse()) {
lib/Target/SystemZ/SystemZElimCompare.cpp 157 if (MO.isUse())
lib/Target/SystemZ/SystemZInstrInfo.cpp 101 if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
lib/Target/WebAssembly/WebAssemblyRegColoring.cpp 70 Weight += LiveIntervals::getSpillWeight(MO.isDef(), MO.isUse(), MBFI,
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 811 assert(Op.isUse() && "explicit_uses() should only iterate over uses");
lib/Target/X86/X86CmovConversion.cpp 437 if (!MO.isReg() || !MO.isUse())
lib/Target/X86/X86DomainReassignment.cpp 577 if (!Op.isReg() || !Op.isUse())
lib/Target/X86/X86FixupBWInsts.cpp 253 assert((MO.isDef() || MO.isUse()) && "Expected Def or Use only!");
262 if (MO.isUse() && !TRI->isSubRegisterEq(OrigDestReg, MO.getReg()) &&
lib/Target/X86/X86FixupSetCC.cpp 89 if (Op.isReg() && (Op.getReg() == X86::EFLAGS) && Op.isUse())
lib/Target/X86/X86FloatingPoint.cpp 1023 assert(Op.isUse() &&
1611 if (Op.isUse() && Op.isKill())
lib/Target/X86/X86ISelLowering.cpp30381 if (MO.isReg() && MO.isUse())