|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/MachineInstrBuilder.h 500 getUndefRegState(RegOp.isUndef()) |
include/llvm/CodeGen/MachineOperand.h 453 return !isUndef() && !isInternalRead() && (isUse() || getSubReg());
lib/CodeGen/BranchFolding.cpp 877 if (MO.isReg() && MO.isUndef()) {
879 if (!OtherMO.isUndef())
lib/CodeGen/BreakFalseDeps.cpp 110 assert(MO.isUndef() && "Expected undef machine operand");
131 if (!CurrMO.isReg() || CurrMO.isDef() || CurrMO.isUndef() ||
lib/CodeGen/ExpandPostRAPseudos.cpp 147 if (IdentityCopy || SrcMO.isUndef()) {
152 if (SrcMO.isUndef() || MI->getNumOperands() > 2) {
lib/CodeGen/LiveInterval.cpp 976 if (!MO.isUndef())
lib/CodeGen/LiveIntervals.cpp 1405 if (MO.isUndef())
1446 if (MO->isReg() && !MO->isUndef() &&
1539 if (MO.getSubReg() && !MO.isUndef())
1558 if (MO.getSubReg() && !MO.isUndef())
lib/CodeGen/LiveRangeEdit.cpp 198 } else if (!MO.isUndef()) {
lib/CodeGen/MachineBasicBlock.cpp 909 !OI->isUse() || !OI->isKill() || OI->isUndef())
1034 if (MO.isUndef())
lib/CodeGen/MachineCopyPropagation.cpp 396 if (!MOUse.isReg() || MOUse.isTied() || MOUse.isUndef() || MOUse.isDef() ||
lib/CodeGen/MachineInstr.cpp 976 Use |= !MO.isUndef();
977 else if (MO.getSubReg() && !MO.isUndef())
1794 if (!MO.isReg() || !MO.isUse() || MO.isUndef())
lib/CodeGen/MachineInstrBundle.cpp 169 if (MO.isUndef())
lib/CodeGen/MachineOperand.cpp 763 if (isUndef())
lib/CodeGen/MachineVerifier.cpp 2251 if (!MO0.isUndef() && PrInfo.reachable &&
lib/CodeGen/PHIElimination.cpp 234 if (!isImplicitlyDefined(MO.getReg(), MRI) && !MO.isUndef())
378 bool SrcUndef = MPhi->getOperand(i*2+1).isUndef() ||
lib/CodeGen/PeepholeOptimizer.cpp 1823 if (Src.isUndef())
1873 if (Src.isUndef())
2040 if (MO.isUndef())
lib/CodeGen/RegAllocFast.cpp 455 if (MO.isUndef())
752 assert(MO.isUndef() && "expected undef use");
878 if (MO.isDef() && MO.isUndef())
1101 if (MO.isUndef()) {
1130 assert(MO.isUndef() && "Should only have undef virtreg uses left");
lib/CodeGen/RegisterCoalescer.cpp 864 if (UseMO.isUndef())
1198 if (Op.getSubReg() == 0 || Op.isUndef())
1244 if (DstOperand.getSubReg() && !DstOperand.isUndef())
1660 if (SubReg == 0 || MO.isUndef())
2945 if (MO.getSubReg() != 0 && MO.isUndef() && !EraseImpDef)
3463 if (Copy->getOperand(1).isUndef())
lib/CodeGen/RegisterPressure.cpp 504 if (!MO.isUndef() && !MO.isInternalRead())
536 if (!MO.isUndef() && !MO.isInternalRead())
541 if (MO.isUndef())
1228 if (MO.isUndef())
lib/CodeGen/RegisterScavenging.cpp 142 if (MO.isUndef())
211 if (MO.isUndef())
330 if (!MO.isReg() || MO.isUndef() || !MO.getReg())
544 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
728 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses");
743 assert((!MO.isUndef() || MO.isDef()) && "Cannot handle undef uses");
lib/CodeGen/RenameIndependentSubregs.cpp 353 if (!MO.isUndef()) {
lib/CodeGen/ScheduleDAGInstrs.cpp 396 bool IsKill = MO.getSubReg() == 0 || MO.isUndef();
402 if (MO.getSubReg() != 0 && MO.isUndef()) {
lib/CodeGen/SplitKit.cpp 177 if (!MO.isUndef())
1331 if (MO.isDef() || MO.isUndef())
1342 if (!ExtendRanges || MO.isUndef())
lib/CodeGen/TargetInstrInfo.cpp 181 bool Reg1IsUndef = MI.getOperand(Idx1).isUndef();
182 bool Reg2IsUndef = MI.getOperand(Idx2).isUndef();
1181 if (MOReg.isUndef())
1206 if (MOReg.isUndef())
1232 if (MOInsertedReg.isUndef())
lib/CodeGen/TwoAddressInstructionPass.cpp 1483 if (SrcMO.isUndef() && !DstMO.getSubReg()) {
1769 mi->getOperand(0).setIsUndef(mi->getOperand(1).isUndef());
1821 if (UseMO.isUndef())
lib/CodeGen/UnreachableBlockElim.cpp 187 !Input.isUndef()) {
lib/CodeGen/VirtRegMap.cpp 352 if (MO.isUndef())
386 if (MI.getOperand(1).isUndef() || MI.getNumOperands() > 2) {
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 181 assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
261 assert(!MI.getOperand(3).isUndef() && "cannot handle undef");
lib/Target/AArch64/AArch64InstrInfo.cpp 3272 if (IsSpill && DstMO.isUndef() && Register::isPhysicalRegister(SrcReg)) {
3319 if (IsFill && SrcMO.getSubReg() == 0 && DstMO.isUndef()) {
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 157 if (Src.isUndef()) {
230 MO.isKill(), MO.isDead(), MO.isUndef(),
280 if (Src0.isUndef() && !MRI->getRegClassOrNull(Src0.getReg()))
282 if (Src1.isUndef() && !MRI->getRegClassOrNull(Src1.getReg()))
483 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef()));
520 const unsigned SrcFlags = getUndefRegState(Src.isUndef());
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 895 bool IsUndef = Src0->isUndef();
lib/Target/AMDGPU/GCNRegBankReassign.cpp 364 if (!Op.isReg() || Op.isUndef())
lib/Target/AMDGPU/R600MachineScheduler.cpp 234 if (MI->getOperand(1).isUndef()) {
lib/Target/AMDGPU/SIFoldOperands.cpp 303 Old.setIsUndef(New->isUndef());
441 return !UseMO.isUndef() && !TII->isSDWA(MI);
720 B.addReg(Src.Reg, Def->isUndef() ? RegState::Undef : 0,
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 141 if (MO.isUndef())
lib/Target/AMDGPU/SIISelLowering.cpp 3203 .addReg(IdxReg.getReg(), getUndefRegState(IdxReg.isUndef()));
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 471 assert(!Op.getSubReg() || !Op.isUndef());
807 !MI.getOperand(1).isUndef();
lib/Target/AMDGPU/SIInstrInfo.cpp 1483 bool IsUndef = MI.getOperand(1).isUndef();
1599 MovDPP.addReg(Src, SrcOp.isUndef() ? RegState::Undef : 0, Sub);
1649 bool IsUndef = RegOp.isUndef();
2041 CondReg.setIsUndef(OrigCond.isUndef());
2072 Cond[1].isUndef();
2094 CondReg.setIsUndef(Cond[1].isUndef());
3051 Use.setIsUndef(Orig.isUndef());
4337 unsigned VRsrcUndef = getUndefRegState(Rsrc.isUndef());
6374 return RegOpnd.isUndef() ? TargetInstrInfo::RegSubRegPair() :
6431 if (Op1.isUndef())
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 262 .addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg());
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 279 To.setIsUndef(From.isUndef());
lib/Target/AMDGPU/SIShrinkInstructions.cpp 261 if (!Op.isUndef())
lib/Target/AMDGPU/SIWholeQuadMode.cpp 361 if (Inactive.isUndef()) {
lib/Target/ARM/ARMAsmPrinter.cpp 1129 if (MO.isUndef()) {
lib/Target/ARM/ARMBaseInstrInfo.cpp 685 if (!MO.isReg() || MO.isUndef() || MO.isUse())
5263 if (!MOReg->isUndef())
5268 if (!MOReg->isUndef())
5289 if (MOReg.isUndef())
5310 if (MOInsertedReg.isUndef())
lib/Target/ARM/ARMExpandPseudoInsts.cpp 626 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
714 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
939 assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
1058 assert(!MI.getOperand(2).isUndef() && "cannot handle undef");
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 1009 unsigned PRegNum = PMO.isUndef() ? std::numeric_limits<unsigned>::max()
1062 unsigned RegNum = MO.isUndef() ? std::numeric_limits<unsigned>::max()
1610 if (MI.getOperand(0).isReg() && MI.getOperand(0).isUndef())
1614 if (MI.getOperand(1).isUndef())
1679 bool EvenUndef = MI->getOperand(0).isUndef();
1682 bool OddUndef = MI->getOperand(1).isUndef();
1684 bool BaseUndef = BaseOp.isUndef();
lib/Target/ARM/Thumb2SizeReduction.cpp 301 if (!MO.isReg() || MO.isUndef() || MO.isUse())
310 if (!MO.isReg() || MO.isUndef() || MO.isDef())
975 if (!MO.isReg() || MO.isUndef() || MO.isUse())
990 if (!MO.isReg() || MO.isUndef() || MO.isDef())
lib/Target/Hexagon/HexagonBlockRanges.cpp 321 if (!Op.isReg() || !Op.isUse() || Op.isUndef())
337 if (!Op.isReg() || !Op.isDef() || Op.isUndef())
lib/Target/Hexagon/HexagonExpandCondsets.cpp 675 bool ReadUndef = MD.isUndef();
885 MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0,
1006 if (Op.isDef() && Op.isUndef()) {
lib/Target/Hexagon/HexagonGenMux.cpp 246 if (PredOp.isUndef())
lib/Target/Hexagon/HexagonInstrInfo.cpp 630 unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
634 unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
645 unsigned Flags = getUndefRegState(RO.isUndef());
669 unsigned Flags = getUndefRegState(RO.isUndef());
1048 if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
4274 if (Cond[1].isUndef())
lib/Target/Hexagon/HexagonOptAddrMode.cpp 422 BaseOp.setIsUndef(AddRegOp.isUndef());
lib/Target/Hexagon/HexagonSplitDouble.cpp 622 Op.isDead(), Op.isUndef(), Op.isEarlyClobber(), SR, Op.isDebug(),
lib/Target/Hexagon/RDFGraph.cpp 1272 if (!Op.isReg() || Op.getReg() == 0 || !Op.isUse() || Op.isUndef())
1372 if (Op.isUndef())
lib/Target/Hexagon/RDFLiveness.cpp 899 if (!Op.isReg() || !Op.isUse() || Op.isUndef())
lib/Target/Mips/MipsSEFrameLowering.cpp 348 if ((Op1.isReg() && Op1.isUndef()) || (Op2.isReg() && Op2.isUndef())) {
348 if ((Op1.isReg() && Op1.isUndef()) || (Op2.isReg() && Op2.isUndef())) {
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 228 bool AddRegUndef = AddendMI->getOperand(1).isUndef();
229 bool KilledProdRegUndef = MI.getOperand(KilledProdOp).isUndef();
230 bool OtherProdRegUndef = MI.getOperand(OtherProdOp).isUndef();
lib/Target/SystemZ/SystemZInstrInfo.cpp 80 unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef());
164 MI.getOperand(1).isUndef());
202 Size, MI.getOperand(1).isKill(), MI.getOperand(1).isUndef());
lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp 125 if (!O.isUndef()) {
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 335 if (!MO.isReg() || MO.isUndef())
lib/Target/X86/X86InstrInfo.cpp 722 assert(!Src.isUndef() && "Undef op doesn't need optimization");
739 assert(!Src.isUndef() && "Undef op doesn't need optimization");
796 assert(!MI.getOperand(1).isUndef() && "Undef op doesn't need optimization");
836 assert(!MI.getOperand(2).isUndef() && "Undef op doesn't need optimization");
909 if (Src.isUndef())
912 if (MI.getOperand(2).isReg() && MI.getOperand(2).isUndef())
2563 if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef())
4071 getUndefRegState(MIB->getOperand(1).isUndef()));
4561 if (MO.isUndef() && Register::isPhysicalRegister(MO.getReg())) {
4813 if (MI.getOperand(1).isUndef())
5544 getUndefRegState(ImpOp.isUndef()));