reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/MachineOperand.h

  551     assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&
  672     assert((isFI() || isCPI() || isTargetIndex() || isJTI()) &&

lib/CodeGen/AsmPrinter/AsmPrinter.cpp

  882       assert(MI->getOperand(0).isFI() && "Unknown operand type");

lib/CodeGen/LiveDebugVariables.cpp

 1316   assert((!Spilled || MO.isFI()) && "a spilled location must be a frame index");

lib/CodeGen/LocalStackSlotAllocation.cpp

  321         if (MI.getOperand(i).isFI()) {
  366       if (!MI.getOperand(idx).isFI())

lib/CodeGen/MIRVRegNamerUtils.cpp

  143         if (MO.isFI()) {
  296       if (!MO.isReg() && !MO.isFI())

lib/CodeGen/MachineLICM.cpp

  406     if (MO.isFI()) {

lib/CodeGen/MachineScheduler.cpp

 1485       if (BaseOp->isFI()) {

lib/CodeGen/PrologEpilogInserter.cpp

  187     if (MI.getOperand(0).isFI()) {
 1199       if (!MI.getOperand(i).isFI())

lib/CodeGen/RegisterScavenging.cpp

  452   while (!MI.getOperand(i).isFI()) {

lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp

  572     bool hasFI = MI->getOperand(0).isFI();

lib/CodeGen/ShrinkWrap.cpp

  302     if (UseOrDefCSR || (MO.isFI() && !MI.isDebugValue())) {
  304                         << MO.isFI() << "): " << MI << '\n');

lib/CodeGen/StackColoring.cpp

  605         if (!MO.isFI())
  681           if (!MO.isFI())
  986         if (!MO.isFI())
 1095         if (!MO.isFI())

lib/CodeGen/StackSlotColoring.cpp

  167         if (!MO.isFI())
  401     if (!MO.isFI())

lib/CodeGen/TargetLoweringBase.cpp

 1040     if (!MO.isFI())

lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp

   66     if (MO.isFI())

lib/Target/AArch64/AArch64FrameLowering.cpp

  196         if (!MO.isFI())

lib/Target/AArch64/AArch64InstrInfo.cpp

 1067     if (MO.isFI())
 1663     if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
 1686     if (MI.getOperand(0).getSubReg() == 0 && MI.getOperand(1).isFI() &&
 1933   assert((MI.getOperand(1).isReg() || MI.getOperand(1).isFI()) &&
 1995     if ((!LdSt.getOperand(1).isReg() && !LdSt.getOperand(1).isFI()) ||
 2001         (!LdSt.getOperand(2).isReg() && !LdSt.getOperand(2).isFI()) ||
 2028   assert((BaseOp->isReg() || BaseOp->isFI()) &&
 2334   assert((BaseOp1.isReg() || BaseOp1.isFI()) &&
 2375   if (BaseOp1.isFI()) {
 5405     if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||

lib/Target/AArch64/AArch64RegisterInfo.cpp

  336   for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i)
  434   while (!MI.getOperand(i).isFI()) {

lib/Target/AMDGPU/SIFoldOperands.cpp

   51     } else if (FoldOp->isFI()) {
  176   return OpToFold.isFI() &&
  403           (OpToFold->isImm() || OpToFold->isFI() || OpToFold->isGlobal())) {
  610       OpToFold.isImm() || OpToFold.isFI() || OpToFold.isGlobal();
 1122   bool FoldingImm = OpToFold.isImm() || OpToFold.isFI() || OpToFold.isGlobal();
 1500           OpToFold.isImm() || OpToFold.isFI() || OpToFold.isGlobal();

lib/Target/AMDGPU/SIFormMemoryClauses.cpp

  213     if (MO.isFI())

lib/Target/AMDGPU/SIInstrInfo.cpp

  325       if (AddrReg && !AddrReg->isFI())
 1654   else if (NonRegOp.isFI())
 2929   assert(MO.isImm() || MO.isTargetIndex() || MO.isFI() || MO.isGlobal());
 3275       if (!MI.getOperand(i).isImm() && !MI.getOperand(i).isFI()) {
 3945   assert(MO.isImm() || MO.isTargetIndex() || MO.isFI() || MO.isGlobal());
 4002   assert(MO->isImm() || MO->isTargetIndex() || MO->isFI() || MO->isGlobal());
 5922   if (!Addr || !Addr->isFI())
 5935   assert(Addr && Addr->isFI());

lib/Target/AMDGPU/SIRegisterInfo.cpp

  385     if (MO.isFI()) {
  399   assert(FIOp && FIOp->isFI() && "frame index must be address operand");

lib/Target/AMDGPU/SIShrinkInstructions.cpp

   94         } else if (MovSrc.isFI()) {

lib/Target/ARC/ARCInstrInfo.cpp

   72     if ((MI.getOperand(1).isFI()) &&  // is a stack slot
   91     if ((MI.getOperand(1).isFI()) &&  // is a stack slot

lib/Target/ARM/ARMBaseInstrInfo.cpp

 1211     if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
 1223     if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
 1230     if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
 1239     if (MI.getOperand(0).isFI() && MI.getOperand(2).getSubReg() == 0) {
 1245     if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
 1448     if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
 1460     if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
 1467     if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&
 1482     if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
 1488     if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
 2194     if (MO.isFI() || MO.isCPI() || MO.isJTI())

lib/Target/ARM/ARMBaseRegisterInfo.cpp

  550   for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
  668   while (!MI.getOperand(i).isFI()) {
  688   for (; !MI->getOperand(i).isFI(); ++i)

lib/Target/ARM/ARMFrameLowering.cpp

 1518         if (!MI.getOperand(i).isFI())

lib/Target/ARM/Thumb1FrameLowering.cpp

  456   if (MI.getOpcode() == ARM::tLDRspi && MI.getOperand(1).isFI() &&

lib/Target/ARM/ThumbRegisterInfo.cpp

  441   while (!MI.getOperand(i).isFI()) {

lib/Target/AVR/AVRFrameLowering.cpp

  470           if (!MO.isFI()) {

lib/Target/AVR/AVRInstrInfo.cpp

   87     if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
  106     if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&

lib/Target/BPF/BPFRegisterInfo.cpp

   75   while (!MI.getOperand(i).isFI()) {

lib/Target/Hexagon/HexagonConstExtenders.cpp

  238         } else if (Op.isFI()) {
 1152     if (Op.isFI() && Op.getIndex() < 0)

lib/Target/Hexagon/HexagonFrameLowering.cpp

  303         if (MO.isFI())
 1593   if (!MI->getOperand(0).isFI())
 1626   if (!MI->getOperand(1).isFI())
 1657   if (!MI->getOperand(0).isFI())
 1694   if (!MI->getOperand(1).isFI())
 1732   if (!MI->getOperand(0).isFI())
 1792   if (!MI->getOperand(1).isFI())
 1832   if (!MI->getOperand(0).isFI())
 1861   if (!MI->getOperand(1).isFI())
 2117         if (!Op.isFI())
 2518           if (MI.getOperand(0).isFI())

lib/Target/Hexagon/HexagonInstrInfo.cpp

  255       if (!OpFI.isFI())
  269       if (!OpFI.isFI())
  303       if (!OpFI.isFI())
  321       if (!OpFI.isFI())

lib/Target/Hexagon/HexagonOptAddrMode.cpp

  205       if (Mo.isFI())

lib/Target/Lanai/LanaiInstrInfo.cpp

  474     if (MO.isFI() || MO.isCPI() || MO.isJTI())
  720     if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
  749     if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&

lib/Target/Mips/MipsSEFrameLowering.cpp

  171   assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
  186   assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
  204   assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());
  229   assert(I->getOperand(0).isReg() && I->getOperand(1).isFI());

lib/Target/Mips/MipsSEInstrInfo.cpp

   51     if ((MI.getOperand(1).isFI()) &&  // is a stack slot
   73     if ((MI.getOperand(1).isFI()) &&  // is a stack slot

lib/Target/NVPTX/NVPTXPrologEpilogPass.cpp

   61         if (!MI.getOperand(i).isFI())

lib/Target/PowerPC/PPCInstrInfo.cpp

  308         MI.getOperand(2).isFI()) {
  360         MI.getOperand(2).isFI()) {

lib/Target/PowerPC/PPCRegisterInfo.cpp

 1244   while (!MI.getOperand(FIOperandNum).isFI()) {
 1269   while (!MI->getOperand(FIOperandNum).isFI()) {

lib/Target/RISCV/RISCVInstrInfo.cpp

   53   if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
   76   if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&

lib/Target/RISCV/RISCVMergeBaseOffset.cpp

  231     if (Tail.getOperand(1).isFI())

lib/Target/Sparc/SparcInstrInfo.cpp

   48     if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
   67     if (MI.getOperand(0).isFI() && MI.getOperand(1).isImm() &&

lib/Target/SystemZ/SystemZInstrInfo.cpp

  312   if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&
  335   if (MI.getOpcode() != SystemZ::MVC || !MI.getOperand(0).isFI() ||
  336       MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() ||

lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp

  318   if (!((Base.isReg() && Base.getReg() != X86::NoRegister) || Base.isFI()))

lib/Target/X86/X86FrameLowering.cpp

 3123         if (!MO.isFI())

lib/Target/X86/X86ISelLowering.cpp

 4247           Def->getOperand(1).isFI()) {

lib/Target/X86/X86InstrInfo.cpp

  195   if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
 7598     } else if (Op1.isFI())
 7630       if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
 8097     if (MOP.isCPI() || MOP.isJTI() || MOP.isCFIIndex() || MOP.isFI() ||

lib/Target/X86/X86InstrInfo.h

  113   if (MI.getOperand(Op).isFI())
  126   if (MI.getOperand(Op).isFI())

lib/Target/X86/X86SpeculativeLoadHardening.cpp

 1720         if (!BaseMO.isFI() && BaseMO.getReg() != X86::RIP &&
 1958   if (BaseMO.isFI()) {

lib/Target/XCore/XCoreInstrInfo.cpp

   67     if ((MI.getOperand(1).isFI()) &&  // is a stack slot
   87     if ((MI.getOperand(1).isFI()) &&  // is a stack slot