|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenInstrInfo.inc18212 MI.getOperand(1).getReg() == AArch64::WZR
18213 || MI.getOperand(1).getReg() == AArch64::XZR
18288 MI.getOperand(0).getReg() == AArch64::WSP
18289 || MI.getOperand(0).getReg() == AArch64::SP
18290 || MI.getOperand(1).getReg() == AArch64::WSP
18291 || MI.getOperand(1).getReg() == AArch64::SP
18301 MI.getOperand(1).getReg() == AArch64::WZR
18302 || MI.getOperand(1).getReg() == AArch64::XZR
18338 MI.getOperand(1).getReg() == AArch64::WZR
18339 || MI.getOperand(1).getReg() == AArch64::XZR
gen/lib/Target/AArch64/AArch64GenSubtargetInfo.inc18036 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18036 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18047 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18047 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18059 MI->getOperand(0).getReg() == AArch64::D0
18060 || MI->getOperand(0).getReg() == AArch64::D1
18061 || MI->getOperand(0).getReg() == AArch64::D2
18062 || MI->getOperand(0).getReg() == AArch64::D3
18063 || MI->getOperand(0).getReg() == AArch64::D4
18064 || MI->getOperand(0).getReg() == AArch64::D5
18065 || MI->getOperand(0).getReg() == AArch64::D6
18066 || MI->getOperand(0).getReg() == AArch64::D7
18067 || MI->getOperand(0).getReg() == AArch64::D8
18068 || MI->getOperand(0).getReg() == AArch64::D9
18069 || MI->getOperand(0).getReg() == AArch64::D10
18070 || MI->getOperand(0).getReg() == AArch64::D11
18071 || MI->getOperand(0).getReg() == AArch64::D12
18072 || MI->getOperand(0).getReg() == AArch64::D13
18073 || MI->getOperand(0).getReg() == AArch64::D14
18074 || MI->getOperand(0).getReg() == AArch64::D15
18075 || MI->getOperand(0).getReg() == AArch64::D16
18076 || MI->getOperand(0).getReg() == AArch64::D17
18077 || MI->getOperand(0).getReg() == AArch64::D18
18078 || MI->getOperand(0).getReg() == AArch64::D19
18079 || MI->getOperand(0).getReg() == AArch64::D20
18080 || MI->getOperand(0).getReg() == AArch64::D21
18081 || MI->getOperand(0).getReg() == AArch64::D22
18082 || MI->getOperand(0).getReg() == AArch64::D23
18083 || MI->getOperand(0).getReg() == AArch64::D24
18084 || MI->getOperand(0).getReg() == AArch64::D25
18085 || MI->getOperand(0).getReg() == AArch64::D26
18086 || MI->getOperand(0).getReg() == AArch64::D27
18087 || MI->getOperand(0).getReg() == AArch64::D28
18088 || MI->getOperand(0).getReg() == AArch64::D29
18089 || MI->getOperand(0).getReg() == AArch64::D30
18090 || MI->getOperand(0).getReg() == AArch64::D31
18096 MI->getOperand(0).getReg() == AArch64::Q0
18097 || MI->getOperand(0).getReg() == AArch64::Q1
18098 || MI->getOperand(0).getReg() == AArch64::Q2
18099 || MI->getOperand(0).getReg() == AArch64::Q3
18100 || MI->getOperand(0).getReg() == AArch64::Q4
18101 || MI->getOperand(0).getReg() == AArch64::Q5
18102 || MI->getOperand(0).getReg() == AArch64::Q6
18103 || MI->getOperand(0).getReg() == AArch64::Q7
18104 || MI->getOperand(0).getReg() == AArch64::Q8
18105 || MI->getOperand(0).getReg() == AArch64::Q9
18106 || MI->getOperand(0).getReg() == AArch64::Q10
18107 || MI->getOperand(0).getReg() == AArch64::Q11
18108 || MI->getOperand(0).getReg() == AArch64::Q12
18109 || MI->getOperand(0).getReg() == AArch64::Q13
18110 || MI->getOperand(0).getReg() == AArch64::Q14
18111 || MI->getOperand(0).getReg() == AArch64::Q15
18112 || MI->getOperand(0).getReg() == AArch64::Q16
18113 || MI->getOperand(0).getReg() == AArch64::Q17
18114 || MI->getOperand(0).getReg() == AArch64::Q18
18115 || MI->getOperand(0).getReg() == AArch64::Q19
18116 || MI->getOperand(0).getReg() == AArch64::Q20
18117 || MI->getOperand(0).getReg() == AArch64::Q21
18118 || MI->getOperand(0).getReg() == AArch64::Q22
18119 || MI->getOperand(0).getReg() == AArch64::Q23
18120 || MI->getOperand(0).getReg() == AArch64::Q24
18121 || MI->getOperand(0).getReg() == AArch64::Q25
18122 || MI->getOperand(0).getReg() == AArch64::Q26
18123 || MI->getOperand(0).getReg() == AArch64::Q27
18124 || MI->getOperand(0).getReg() == AArch64::Q28
18125 || MI->getOperand(0).getReg() == AArch64::Q29
18126 || MI->getOperand(0).getReg() == AArch64::Q30
18127 || MI->getOperand(0).getReg() == AArch64::Q31
18205 MI->getOperand(0).getReg() == AArch64::D0
18206 || MI->getOperand(0).getReg() == AArch64::D1
18207 || MI->getOperand(0).getReg() == AArch64::D2
18208 || MI->getOperand(0).getReg() == AArch64::D3
18209 || MI->getOperand(0).getReg() == AArch64::D4
18210 || MI->getOperand(0).getReg() == AArch64::D5
18211 || MI->getOperand(0).getReg() == AArch64::D6
18212 || MI->getOperand(0).getReg() == AArch64::D7
18213 || MI->getOperand(0).getReg() == AArch64::D8
18214 || MI->getOperand(0).getReg() == AArch64::D9
18215 || MI->getOperand(0).getReg() == AArch64::D10
18216 || MI->getOperand(0).getReg() == AArch64::D11
18217 || MI->getOperand(0).getReg() == AArch64::D12
18218 || MI->getOperand(0).getReg() == AArch64::D13
18219 || MI->getOperand(0).getReg() == AArch64::D14
18220 || MI->getOperand(0).getReg() == AArch64::D15
18221 || MI->getOperand(0).getReg() == AArch64::D16
18222 || MI->getOperand(0).getReg() == AArch64::D17
18223 || MI->getOperand(0).getReg() == AArch64::D18
18224 || MI->getOperand(0).getReg() == AArch64::D19
18225 || MI->getOperand(0).getReg() == AArch64::D20
18226 || MI->getOperand(0).getReg() == AArch64::D21
18227 || MI->getOperand(0).getReg() == AArch64::D22
18228 || MI->getOperand(0).getReg() == AArch64::D23
18229 || MI->getOperand(0).getReg() == AArch64::D24
18230 || MI->getOperand(0).getReg() == AArch64::D25
18231 || MI->getOperand(0).getReg() == AArch64::D26
18232 || MI->getOperand(0).getReg() == AArch64::D27
18233 || MI->getOperand(0).getReg() == AArch64::D28
18234 || MI->getOperand(0).getReg() == AArch64::D29
18235 || MI->getOperand(0).getReg() == AArch64::D30
18236 || MI->getOperand(0).getReg() == AArch64::D31
18242 MI->getOperand(0).getReg() == AArch64::Q0
18243 || MI->getOperand(0).getReg() == AArch64::Q1
18244 || MI->getOperand(0).getReg() == AArch64::Q2
18245 || MI->getOperand(0).getReg() == AArch64::Q3
18246 || MI->getOperand(0).getReg() == AArch64::Q4
18247 || MI->getOperand(0).getReg() == AArch64::Q5
18248 || MI->getOperand(0).getReg() == AArch64::Q6
18249 || MI->getOperand(0).getReg() == AArch64::Q7
18250 || MI->getOperand(0).getReg() == AArch64::Q8
18251 || MI->getOperand(0).getReg() == AArch64::Q9
18252 || MI->getOperand(0).getReg() == AArch64::Q10
18253 || MI->getOperand(0).getReg() == AArch64::Q11
18254 || MI->getOperand(0).getReg() == AArch64::Q12
18255 || MI->getOperand(0).getReg() == AArch64::Q13
18256 || MI->getOperand(0).getReg() == AArch64::Q14
18257 || MI->getOperand(0).getReg() == AArch64::Q15
18258 || MI->getOperand(0).getReg() == AArch64::Q16
18259 || MI->getOperand(0).getReg() == AArch64::Q17
18260 || MI->getOperand(0).getReg() == AArch64::Q18
18261 || MI->getOperand(0).getReg() == AArch64::Q19
18262 || MI->getOperand(0).getReg() == AArch64::Q20
18263 || MI->getOperand(0).getReg() == AArch64::Q21
18264 || MI->getOperand(0).getReg() == AArch64::Q22
18265 || MI->getOperand(0).getReg() == AArch64::Q23
18266 || MI->getOperand(0).getReg() == AArch64::Q24
18267 || MI->getOperand(0).getReg() == AArch64::Q25
18268 || MI->getOperand(0).getReg() == AArch64::Q26
18269 || MI->getOperand(0).getReg() == AArch64::Q27
18270 || MI->getOperand(0).getReg() == AArch64::Q28
18271 || MI->getOperand(0).getReg() == AArch64::Q29
18272 || MI->getOperand(0).getReg() == AArch64::Q30
18273 || MI->getOperand(0).getReg() == AArch64::Q31
18285 MI->getOperand(0).getReg() == AArch64::D0
18286 || MI->getOperand(0).getReg() == AArch64::D1
18287 || MI->getOperand(0).getReg() == AArch64::D2
18288 || MI->getOperand(0).getReg() == AArch64::D3
18289 || MI->getOperand(0).getReg() == AArch64::D4
18290 || MI->getOperand(0).getReg() == AArch64::D5
18291 || MI->getOperand(0).getReg() == AArch64::D6
18292 || MI->getOperand(0).getReg() == AArch64::D7
18293 || MI->getOperand(0).getReg() == AArch64::D8
18294 || MI->getOperand(0).getReg() == AArch64::D9
18295 || MI->getOperand(0).getReg() == AArch64::D10
18296 || MI->getOperand(0).getReg() == AArch64::D11
18297 || MI->getOperand(0).getReg() == AArch64::D12
18298 || MI->getOperand(0).getReg() == AArch64::D13
18299 || MI->getOperand(0).getReg() == AArch64::D14
18300 || MI->getOperand(0).getReg() == AArch64::D15
18301 || MI->getOperand(0).getReg() == AArch64::D16
18302 || MI->getOperand(0).getReg() == AArch64::D17
18303 || MI->getOperand(0).getReg() == AArch64::D18
18304 || MI->getOperand(0).getReg() == AArch64::D19
18305 || MI->getOperand(0).getReg() == AArch64::D20
18306 || MI->getOperand(0).getReg() == AArch64::D21
18307 || MI->getOperand(0).getReg() == AArch64::D22
18308 || MI->getOperand(0).getReg() == AArch64::D23
18309 || MI->getOperand(0).getReg() == AArch64::D24
18310 || MI->getOperand(0).getReg() == AArch64::D25
18311 || MI->getOperand(0).getReg() == AArch64::D26
18312 || MI->getOperand(0).getReg() == AArch64::D27
18313 || MI->getOperand(0).getReg() == AArch64::D28
18314 || MI->getOperand(0).getReg() == AArch64::D29
18315 || MI->getOperand(0).getReg() == AArch64::D30
18316 || MI->getOperand(0).getReg() == AArch64::D31
18322 MI->getOperand(0).getReg() == AArch64::Q0
18323 || MI->getOperand(0).getReg() == AArch64::Q1
18324 || MI->getOperand(0).getReg() == AArch64::Q2
18325 || MI->getOperand(0).getReg() == AArch64::Q3
18326 || MI->getOperand(0).getReg() == AArch64::Q4
18327 || MI->getOperand(0).getReg() == AArch64::Q5
18328 || MI->getOperand(0).getReg() == AArch64::Q6
18329 || MI->getOperand(0).getReg() == AArch64::Q7
18330 || MI->getOperand(0).getReg() == AArch64::Q8
18331 || MI->getOperand(0).getReg() == AArch64::Q9
18332 || MI->getOperand(0).getReg() == AArch64::Q10
18333 || MI->getOperand(0).getReg() == AArch64::Q11
18334 || MI->getOperand(0).getReg() == AArch64::Q12
18335 || MI->getOperand(0).getReg() == AArch64::Q13
18336 || MI->getOperand(0).getReg() == AArch64::Q14
18337 || MI->getOperand(0).getReg() == AArch64::Q15
18338 || MI->getOperand(0).getReg() == AArch64::Q16
18339 || MI->getOperand(0).getReg() == AArch64::Q17
18340 || MI->getOperand(0).getReg() == AArch64::Q18
18341 || MI->getOperand(0).getReg() == AArch64::Q19
18342 || MI->getOperand(0).getReg() == AArch64::Q20
18343 || MI->getOperand(0).getReg() == AArch64::Q21
18344 || MI->getOperand(0).getReg() == AArch64::Q22
18345 || MI->getOperand(0).getReg() == AArch64::Q23
18346 || MI->getOperand(0).getReg() == AArch64::Q24
18347 || MI->getOperand(0).getReg() == AArch64::Q25
18348 || MI->getOperand(0).getReg() == AArch64::Q26
18349 || MI->getOperand(0).getReg() == AArch64::Q27
18350 || MI->getOperand(0).getReg() == AArch64::Q28
18351 || MI->getOperand(0).getReg() == AArch64::Q29
18352 || MI->getOperand(0).getReg() == AArch64::Q30
18353 || MI->getOperand(0).getReg() == AArch64::Q31
18365 MI->getOperand(0).getReg() == AArch64::D0
18366 || MI->getOperand(0).getReg() == AArch64::D1
18367 || MI->getOperand(0).getReg() == AArch64::D2
18368 || MI->getOperand(0).getReg() == AArch64::D3
18369 || MI->getOperand(0).getReg() == AArch64::D4
18370 || MI->getOperand(0).getReg() == AArch64::D5
18371 || MI->getOperand(0).getReg() == AArch64::D6
18372 || MI->getOperand(0).getReg() == AArch64::D7
18373 || MI->getOperand(0).getReg() == AArch64::D8
18374 || MI->getOperand(0).getReg() == AArch64::D9
18375 || MI->getOperand(0).getReg() == AArch64::D10
18376 || MI->getOperand(0).getReg() == AArch64::D11
18377 || MI->getOperand(0).getReg() == AArch64::D12
18378 || MI->getOperand(0).getReg() == AArch64::D13
18379 || MI->getOperand(0).getReg() == AArch64::D14
18380 || MI->getOperand(0).getReg() == AArch64::D15
18381 || MI->getOperand(0).getReg() == AArch64::D16
18382 || MI->getOperand(0).getReg() == AArch64::D17
18383 || MI->getOperand(0).getReg() == AArch64::D18
18384 || MI->getOperand(0).getReg() == AArch64::D19
18385 || MI->getOperand(0).getReg() == AArch64::D20
18386 || MI->getOperand(0).getReg() == AArch64::D21
18387 || MI->getOperand(0).getReg() == AArch64::D22
18388 || MI->getOperand(0).getReg() == AArch64::D23
18389 || MI->getOperand(0).getReg() == AArch64::D24
18390 || MI->getOperand(0).getReg() == AArch64::D25
18391 || MI->getOperand(0).getReg() == AArch64::D26
18392 || MI->getOperand(0).getReg() == AArch64::D27
18393 || MI->getOperand(0).getReg() == AArch64::D28
18394 || MI->getOperand(0).getReg() == AArch64::D29
18395 || MI->getOperand(0).getReg() == AArch64::D30
18396 || MI->getOperand(0).getReg() == AArch64::D31
18402 MI->getOperand(0).getReg() == AArch64::Q0
18403 || MI->getOperand(0).getReg() == AArch64::Q1
18404 || MI->getOperand(0).getReg() == AArch64::Q2
18405 || MI->getOperand(0).getReg() == AArch64::Q3
18406 || MI->getOperand(0).getReg() == AArch64::Q4
18407 || MI->getOperand(0).getReg() == AArch64::Q5
18408 || MI->getOperand(0).getReg() == AArch64::Q6
18409 || MI->getOperand(0).getReg() == AArch64::Q7
18410 || MI->getOperand(0).getReg() == AArch64::Q8
18411 || MI->getOperand(0).getReg() == AArch64::Q9
18412 || MI->getOperand(0).getReg() == AArch64::Q10
18413 || MI->getOperand(0).getReg() == AArch64::Q11
18414 || MI->getOperand(0).getReg() == AArch64::Q12
18415 || MI->getOperand(0).getReg() == AArch64::Q13
18416 || MI->getOperand(0).getReg() == AArch64::Q14
18417 || MI->getOperand(0).getReg() == AArch64::Q15
18418 || MI->getOperand(0).getReg() == AArch64::Q16
18419 || MI->getOperand(0).getReg() == AArch64::Q17
18420 || MI->getOperand(0).getReg() == AArch64::Q18
18421 || MI->getOperand(0).getReg() == AArch64::Q19
18422 || MI->getOperand(0).getReg() == AArch64::Q20
18423 || MI->getOperand(0).getReg() == AArch64::Q21
18424 || MI->getOperand(0).getReg() == AArch64::Q22
18425 || MI->getOperand(0).getReg() == AArch64::Q23
18426 || MI->getOperand(0).getReg() == AArch64::Q24
18427 || MI->getOperand(0).getReg() == AArch64::Q25
18428 || MI->getOperand(0).getReg() == AArch64::Q26
18429 || MI->getOperand(0).getReg() == AArch64::Q27
18430 || MI->getOperand(0).getReg() == AArch64::Q28
18431 || MI->getOperand(0).getReg() == AArch64::Q29
18432 || MI->getOperand(0).getReg() == AArch64::Q30
18433 || MI->getOperand(0).getReg() == AArch64::Q31
18445 && MI->getOperand(0).getReg() == AArch64::LR
18453 && MI->getOperand(0).getReg() == AArch64::LR
18461 && MI->getOperand(0).getReg() == AArch64::LR
18517 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18517 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18528 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18528 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18541 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18541 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18552 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18552 && MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
18575 MI->getOperand(0).getReg() == AArch64::Q0
18576 || MI->getOperand(0).getReg() == AArch64::Q1
18577 || MI->getOperand(0).getReg() == AArch64::Q2
18578 || MI->getOperand(0).getReg() == AArch64::Q3
18579 || MI->getOperand(0).getReg() == AArch64::Q4
18580 || MI->getOperand(0).getReg() == AArch64::Q5
18581 || MI->getOperand(0).getReg() == AArch64::Q6
18582 || MI->getOperand(0).getReg() == AArch64::Q7
18583 || MI->getOperand(0).getReg() == AArch64::Q8
18584 || MI->getOperand(0).getReg() == AArch64::Q9
18585 || MI->getOperand(0).getReg() == AArch64::Q10
18586 || MI->getOperand(0).getReg() == AArch64::Q11
18587 || MI->getOperand(0).getReg() == AArch64::Q12
18588 || MI->getOperand(0).getReg() == AArch64::Q13
18589 || MI->getOperand(0).getReg() == AArch64::Q14
18590 || MI->getOperand(0).getReg() == AArch64::Q15
18591 || MI->getOperand(0).getReg() == AArch64::Q16
18592 || MI->getOperand(0).getReg() == AArch64::Q17
18593 || MI->getOperand(0).getReg() == AArch64::Q18
18594 || MI->getOperand(0).getReg() == AArch64::Q19
18595 || MI->getOperand(0).getReg() == AArch64::Q20
18596 || MI->getOperand(0).getReg() == AArch64::Q21
18597 || MI->getOperand(0).getReg() == AArch64::Q22
18598 || MI->getOperand(0).getReg() == AArch64::Q23
18599 || MI->getOperand(0).getReg() == AArch64::Q24
18600 || MI->getOperand(0).getReg() == AArch64::Q25
18601 || MI->getOperand(0).getReg() == AArch64::Q26
18602 || MI->getOperand(0).getReg() == AArch64::Q27
18603 || MI->getOperand(0).getReg() == AArch64::Q28
18604 || MI->getOperand(0).getReg() == AArch64::Q29
18605 || MI->getOperand(0).getReg() == AArch64::Q30
18606 || MI->getOperand(0).getReg() == AArch64::Q31
20276 MI->getOperand(0).getReg() == AArch64::D0
20277 || MI->getOperand(0).getReg() == AArch64::D1
20278 || MI->getOperand(0).getReg() == AArch64::D2
20279 || MI->getOperand(0).getReg() == AArch64::D3
20280 || MI->getOperand(0).getReg() == AArch64::D4
20281 || MI->getOperand(0).getReg() == AArch64::D5
20282 || MI->getOperand(0).getReg() == AArch64::D6
20283 || MI->getOperand(0).getReg() == AArch64::D7
20284 || MI->getOperand(0).getReg() == AArch64::D8
20285 || MI->getOperand(0).getReg() == AArch64::D9
20286 || MI->getOperand(0).getReg() == AArch64::D10
20287 || MI->getOperand(0).getReg() == AArch64::D11
20288 || MI->getOperand(0).getReg() == AArch64::D12
20289 || MI->getOperand(0).getReg() == AArch64::D13
20290 || MI->getOperand(0).getReg() == AArch64::D14
20291 || MI->getOperand(0).getReg() == AArch64::D15
20292 || MI->getOperand(0).getReg() == AArch64::D16
20293 || MI->getOperand(0).getReg() == AArch64::D17
20294 || MI->getOperand(0).getReg() == AArch64::D18
20295 || MI->getOperand(0).getReg() == AArch64::D19
20296 || MI->getOperand(0).getReg() == AArch64::D20
20297 || MI->getOperand(0).getReg() == AArch64::D21
20298 || MI->getOperand(0).getReg() == AArch64::D22
20299 || MI->getOperand(0).getReg() == AArch64::D23
20300 || MI->getOperand(0).getReg() == AArch64::D24
20301 || MI->getOperand(0).getReg() == AArch64::D25
20302 || MI->getOperand(0).getReg() == AArch64::D26
20303 || MI->getOperand(0).getReg() == AArch64::D27
20304 || MI->getOperand(0).getReg() == AArch64::D28
20305 || MI->getOperand(0).getReg() == AArch64::D29
20306 || MI->getOperand(0).getReg() == AArch64::D30
20307 || MI->getOperand(0).getReg() == AArch64::D31
20313 MI->getOperand(0).getReg() == AArch64::Q0
20314 || MI->getOperand(0).getReg() == AArch64::Q1
20315 || MI->getOperand(0).getReg() == AArch64::Q2
20316 || MI->getOperand(0).getReg() == AArch64::Q3
20317 || MI->getOperand(0).getReg() == AArch64::Q4
20318 || MI->getOperand(0).getReg() == AArch64::Q5
20319 || MI->getOperand(0).getReg() == AArch64::Q6
20320 || MI->getOperand(0).getReg() == AArch64::Q7
20321 || MI->getOperand(0).getReg() == AArch64::Q8
20322 || MI->getOperand(0).getReg() == AArch64::Q9
20323 || MI->getOperand(0).getReg() == AArch64::Q10
20324 || MI->getOperand(0).getReg() == AArch64::Q11
20325 || MI->getOperand(0).getReg() == AArch64::Q12
20326 || MI->getOperand(0).getReg() == AArch64::Q13
20327 || MI->getOperand(0).getReg() == AArch64::Q14
20328 || MI->getOperand(0).getReg() == AArch64::Q15
20329 || MI->getOperand(0).getReg() == AArch64::Q16
20330 || MI->getOperand(0).getReg() == AArch64::Q17
20331 || MI->getOperand(0).getReg() == AArch64::Q18
20332 || MI->getOperand(0).getReg() == AArch64::Q19
20333 || MI->getOperand(0).getReg() == AArch64::Q20
20334 || MI->getOperand(0).getReg() == AArch64::Q21
20335 || MI->getOperand(0).getReg() == AArch64::Q22
20336 || MI->getOperand(0).getReg() == AArch64::Q23
20337 || MI->getOperand(0).getReg() == AArch64::Q24
20338 || MI->getOperand(0).getReg() == AArch64::Q25
20339 || MI->getOperand(0).getReg() == AArch64::Q26
20340 || MI->getOperand(0).getReg() == AArch64::Q27
20341 || MI->getOperand(0).getReg() == AArch64::Q28
20342 || MI->getOperand(0).getReg() == AArch64::Q29
20343 || MI->getOperand(0).getReg() == AArch64::Q30
20344 || MI->getOperand(0).getReg() == AArch64::Q31
20357 MI->getOperand(0).getReg() == AArch64::Q0
20358 || MI->getOperand(0).getReg() == AArch64::Q1
20359 || MI->getOperand(0).getReg() == AArch64::Q2
20360 || MI->getOperand(0).getReg() == AArch64::Q3
20361 || MI->getOperand(0).getReg() == AArch64::Q4
20362 || MI->getOperand(0).getReg() == AArch64::Q5
20363 || MI->getOperand(0).getReg() == AArch64::Q6
20364 || MI->getOperand(0).getReg() == AArch64::Q7
20365 || MI->getOperand(0).getReg() == AArch64::Q8
20366 || MI->getOperand(0).getReg() == AArch64::Q9
20367 || MI->getOperand(0).getReg() == AArch64::Q10
20368 || MI->getOperand(0).getReg() == AArch64::Q11
20369 || MI->getOperand(0).getReg() == AArch64::Q12
20370 || MI->getOperand(0).getReg() == AArch64::Q13
20371 || MI->getOperand(0).getReg() == AArch64::Q14
20372 || MI->getOperand(0).getReg() == AArch64::Q15
20373 || MI->getOperand(0).getReg() == AArch64::Q16
20374 || MI->getOperand(0).getReg() == AArch64::Q17
20375 || MI->getOperand(0).getReg() == AArch64::Q18
20376 || MI->getOperand(0).getReg() == AArch64::Q19
20377 || MI->getOperand(0).getReg() == AArch64::Q20
20378 || MI->getOperand(0).getReg() == AArch64::Q21
20379 || MI->getOperand(0).getReg() == AArch64::Q22
20380 || MI->getOperand(0).getReg() == AArch64::Q23
20381 || MI->getOperand(0).getReg() == AArch64::Q24
20382 || MI->getOperand(0).getReg() == AArch64::Q25
20383 || MI->getOperand(0).getReg() == AArch64::Q26
20384 || MI->getOperand(0).getReg() == AArch64::Q27
20385 || MI->getOperand(0).getReg() == AArch64::Q28
20386 || MI->getOperand(0).getReg() == AArch64::Q29
20387 || MI->getOperand(0).getReg() == AArch64::Q30
20388 || MI->getOperand(0).getReg() == AArch64::Q31
20606 if (MI->getOperand(1).getReg() == AArch64::WZR ||
20608 MI->getOperand(1).getReg() == AArch64::XZR)
20857 MI->getOperand(0).getReg() == AArch64::D0
20858 || MI->getOperand(0).getReg() == AArch64::D1
20859 || MI->getOperand(0).getReg() == AArch64::D2
20860 || MI->getOperand(0).getReg() == AArch64::D3
20861 || MI->getOperand(0).getReg() == AArch64::D4
20862 || MI->getOperand(0).getReg() == AArch64::D5
20863 || MI->getOperand(0).getReg() == AArch64::D6
20864 || MI->getOperand(0).getReg() == AArch64::D7
20865 || MI->getOperand(0).getReg() == AArch64::D8
20866 || MI->getOperand(0).getReg() == AArch64::D9
20867 || MI->getOperand(0).getReg() == AArch64::D10
20868 || MI->getOperand(0).getReg() == AArch64::D11
20869 || MI->getOperand(0).getReg() == AArch64::D12
20870 || MI->getOperand(0).getReg() == AArch64::D13
20871 || MI->getOperand(0).getReg() == AArch64::D14
20872 || MI->getOperand(0).getReg() == AArch64::D15
20873 || MI->getOperand(0).getReg() == AArch64::D16
20874 || MI->getOperand(0).getReg() == AArch64::D17
20875 || MI->getOperand(0).getReg() == AArch64::D18
20876 || MI->getOperand(0).getReg() == AArch64::D19
20877 || MI->getOperand(0).getReg() == AArch64::D20
20878 || MI->getOperand(0).getReg() == AArch64::D21
20879 || MI->getOperand(0).getReg() == AArch64::D22
20880 || MI->getOperand(0).getReg() == AArch64::D23
20881 || MI->getOperand(0).getReg() == AArch64::D24
20882 || MI->getOperand(0).getReg() == AArch64::D25
20883 || MI->getOperand(0).getReg() == AArch64::D26
20884 || MI->getOperand(0).getReg() == AArch64::D27
20885 || MI->getOperand(0).getReg() == AArch64::D28
20886 || MI->getOperand(0).getReg() == AArch64::D29
20887 || MI->getOperand(0).getReg() == AArch64::D30
20888 || MI->getOperand(0).getReg() == AArch64::D31
20894 MI->getOperand(0).getReg() == AArch64::Q0
20895 || MI->getOperand(0).getReg() == AArch64::Q1
20896 || MI->getOperand(0).getReg() == AArch64::Q2
20897 || MI->getOperand(0).getReg() == AArch64::Q3
20898 || MI->getOperand(0).getReg() == AArch64::Q4
20899 || MI->getOperand(0).getReg() == AArch64::Q5
20900 || MI->getOperand(0).getReg() == AArch64::Q6
20901 || MI->getOperand(0).getReg() == AArch64::Q7
20902 || MI->getOperand(0).getReg() == AArch64::Q8
20903 || MI->getOperand(0).getReg() == AArch64::Q9
20904 || MI->getOperand(0).getReg() == AArch64::Q10
20905 || MI->getOperand(0).getReg() == AArch64::Q11
20906 || MI->getOperand(0).getReg() == AArch64::Q12
20907 || MI->getOperand(0).getReg() == AArch64::Q13
20908 || MI->getOperand(0).getReg() == AArch64::Q14
20909 || MI->getOperand(0).getReg() == AArch64::Q15
20910 || MI->getOperand(0).getReg() == AArch64::Q16
20911 || MI->getOperand(0).getReg() == AArch64::Q17
20912 || MI->getOperand(0).getReg() == AArch64::Q18
20913 || MI->getOperand(0).getReg() == AArch64::Q19
20914 || MI->getOperand(0).getReg() == AArch64::Q20
20915 || MI->getOperand(0).getReg() == AArch64::Q21
20916 || MI->getOperand(0).getReg() == AArch64::Q22
20917 || MI->getOperand(0).getReg() == AArch64::Q23
20918 || MI->getOperand(0).getReg() == AArch64::Q24
20919 || MI->getOperand(0).getReg() == AArch64::Q25
20920 || MI->getOperand(0).getReg() == AArch64::Q26
20921 || MI->getOperand(0).getReg() == AArch64::Q27
20922 || MI->getOperand(0).getReg() == AArch64::Q28
20923 || MI->getOperand(0).getReg() == AArch64::Q29
20924 || MI->getOperand(0).getReg() == AArch64::Q30
20925 || MI->getOperand(0).getReg() == AArch64::Q31
20933 if (MI->getOperand(1).getReg() == AArch64::WZR ||
20935 MI->getOperand(1).getReg() == AArch64::XZR)
21387 if (MI->getOperand(1).getReg() == AArch64::WZR ||
21389 MI->getOperand(1).getReg() == AArch64::XZR)
21400 MI->getOperand(0).getReg() == AArch64::D0
21401 || MI->getOperand(0).getReg() == AArch64::D1
21402 || MI->getOperand(0).getReg() == AArch64::D2
21403 || MI->getOperand(0).getReg() == AArch64::D3
21404 || MI->getOperand(0).getReg() == AArch64::D4
21405 || MI->getOperand(0).getReg() == AArch64::D5
21406 || MI->getOperand(0).getReg() == AArch64::D6
21407 || MI->getOperand(0).getReg() == AArch64::D7
21408 || MI->getOperand(0).getReg() == AArch64::D8
21409 || MI->getOperand(0).getReg() == AArch64::D9
21410 || MI->getOperand(0).getReg() == AArch64::D10
21411 || MI->getOperand(0).getReg() == AArch64::D11
21412 || MI->getOperand(0).getReg() == AArch64::D12
21413 || MI->getOperand(0).getReg() == AArch64::D13
21414 || MI->getOperand(0).getReg() == AArch64::D14
21415 || MI->getOperand(0).getReg() == AArch64::D15
21416 || MI->getOperand(0).getReg() == AArch64::D16
21417 || MI->getOperand(0).getReg() == AArch64::D17
21418 || MI->getOperand(0).getReg() == AArch64::D18
21419 || MI->getOperand(0).getReg() == AArch64::D19
21420 || MI->getOperand(0).getReg() == AArch64::D20
21421 || MI->getOperand(0).getReg() == AArch64::D21
21422 || MI->getOperand(0).getReg() == AArch64::D22
21423 || MI->getOperand(0).getReg() == AArch64::D23
21424 || MI->getOperand(0).getReg() == AArch64::D24
21425 || MI->getOperand(0).getReg() == AArch64::D25
21426 || MI->getOperand(0).getReg() == AArch64::D26
21427 || MI->getOperand(0).getReg() == AArch64::D27
21428 || MI->getOperand(0).getReg() == AArch64::D28
21429 || MI->getOperand(0).getReg() == AArch64::D29
21430 || MI->getOperand(0).getReg() == AArch64::D30
21431 || MI->getOperand(0).getReg() == AArch64::D31
21437 MI->getOperand(0).getReg() == AArch64::Q0
21438 || MI->getOperand(0).getReg() == AArch64::Q1
21439 || MI->getOperand(0).getReg() == AArch64::Q2
21440 || MI->getOperand(0).getReg() == AArch64::Q3
21441 || MI->getOperand(0).getReg() == AArch64::Q4
21442 || MI->getOperand(0).getReg() == AArch64::Q5
21443 || MI->getOperand(0).getReg() == AArch64::Q6
21444 || MI->getOperand(0).getReg() == AArch64::Q7
21445 || MI->getOperand(0).getReg() == AArch64::Q8
21446 || MI->getOperand(0).getReg() == AArch64::Q9
21447 || MI->getOperand(0).getReg() == AArch64::Q10
21448 || MI->getOperand(0).getReg() == AArch64::Q11
21449 || MI->getOperand(0).getReg() == AArch64::Q12
21450 || MI->getOperand(0).getReg() == AArch64::Q13
21451 || MI->getOperand(0).getReg() == AArch64::Q14
21452 || MI->getOperand(0).getReg() == AArch64::Q15
21453 || MI->getOperand(0).getReg() == AArch64::Q16
21454 || MI->getOperand(0).getReg() == AArch64::Q17
21455 || MI->getOperand(0).getReg() == AArch64::Q18
21456 || MI->getOperand(0).getReg() == AArch64::Q19
21457 || MI->getOperand(0).getReg() == AArch64::Q20
21458 || MI->getOperand(0).getReg() == AArch64::Q21
21459 || MI->getOperand(0).getReg() == AArch64::Q22
21460 || MI->getOperand(0).getReg() == AArch64::Q23
21461 || MI->getOperand(0).getReg() == AArch64::Q24
21462 || MI->getOperand(0).getReg() == AArch64::Q25
21463 || MI->getOperand(0).getReg() == AArch64::Q26
21464 || MI->getOperand(0).getReg() == AArch64::Q27
21465 || MI->getOperand(0).getReg() == AArch64::Q28
21466 || MI->getOperand(0).getReg() == AArch64::Q29
21467 || MI->getOperand(0).getReg() == AArch64::Q30
21468 || MI->getOperand(0).getReg() == AArch64::Q31
21482 MI->getOperand(0).getReg() == AArch64::D0
21483 || MI->getOperand(0).getReg() == AArch64::D1
21484 || MI->getOperand(0).getReg() == AArch64::D2
21485 || MI->getOperand(0).getReg() == AArch64::D3
21486 || MI->getOperand(0).getReg() == AArch64::D4
21487 || MI->getOperand(0).getReg() == AArch64::D5
21488 || MI->getOperand(0).getReg() == AArch64::D6
21489 || MI->getOperand(0).getReg() == AArch64::D7
21490 || MI->getOperand(0).getReg() == AArch64::D8
21491 || MI->getOperand(0).getReg() == AArch64::D9
21492 || MI->getOperand(0).getReg() == AArch64::D10
21493 || MI->getOperand(0).getReg() == AArch64::D11
21494 || MI->getOperand(0).getReg() == AArch64::D12
21495 || MI->getOperand(0).getReg() == AArch64::D13
21496 || MI->getOperand(0).getReg() == AArch64::D14
21497 || MI->getOperand(0).getReg() == AArch64::D15
21498 || MI->getOperand(0).getReg() == AArch64::D16
21499 || MI->getOperand(0).getReg() == AArch64::D17
21500 || MI->getOperand(0).getReg() == AArch64::D18
21501 || MI->getOperand(0).getReg() == AArch64::D19
21502 || MI->getOperand(0).getReg() == AArch64::D20
21503 || MI->getOperand(0).getReg() == AArch64::D21
21504 || MI->getOperand(0).getReg() == AArch64::D22
21505 || MI->getOperand(0).getReg() == AArch64::D23
21506 || MI->getOperand(0).getReg() == AArch64::D24
21507 || MI->getOperand(0).getReg() == AArch64::D25
21508 || MI->getOperand(0).getReg() == AArch64::D26
21509 || MI->getOperand(0).getReg() == AArch64::D27
21510 || MI->getOperand(0).getReg() == AArch64::D28
21511 || MI->getOperand(0).getReg() == AArch64::D29
21512 || MI->getOperand(0).getReg() == AArch64::D30
21513 || MI->getOperand(0).getReg() == AArch64::D31
21519 MI->getOperand(0).getReg() == AArch64::Q0
21520 || MI->getOperand(0).getReg() == AArch64::Q1
21521 || MI->getOperand(0).getReg() == AArch64::Q2
21522 || MI->getOperand(0).getReg() == AArch64::Q3
21523 || MI->getOperand(0).getReg() == AArch64::Q4
21524 || MI->getOperand(0).getReg() == AArch64::Q5
21525 || MI->getOperand(0).getReg() == AArch64::Q6
21526 || MI->getOperand(0).getReg() == AArch64::Q7
21527 || MI->getOperand(0).getReg() == AArch64::Q8
21528 || MI->getOperand(0).getReg() == AArch64::Q9
21529 || MI->getOperand(0).getReg() == AArch64::Q10
21530 || MI->getOperand(0).getReg() == AArch64::Q11
21531 || MI->getOperand(0).getReg() == AArch64::Q12
21532 || MI->getOperand(0).getReg() == AArch64::Q13
21533 || MI->getOperand(0).getReg() == AArch64::Q14
21534 || MI->getOperand(0).getReg() == AArch64::Q15
21535 || MI->getOperand(0).getReg() == AArch64::Q16
21536 || MI->getOperand(0).getReg() == AArch64::Q17
21537 || MI->getOperand(0).getReg() == AArch64::Q18
21538 || MI->getOperand(0).getReg() == AArch64::Q19
21539 || MI->getOperand(0).getReg() == AArch64::Q20
21540 || MI->getOperand(0).getReg() == AArch64::Q21
21541 || MI->getOperand(0).getReg() == AArch64::Q22
21542 || MI->getOperand(0).getReg() == AArch64::Q23
21543 || MI->getOperand(0).getReg() == AArch64::Q24
21544 || MI->getOperand(0).getReg() == AArch64::Q25
21545 || MI->getOperand(0).getReg() == AArch64::Q26
21546 || MI->getOperand(0).getReg() == AArch64::Q27
21547 || MI->getOperand(0).getReg() == AArch64::Q28
21548 || MI->getOperand(0).getReg() == AArch64::Q29
21549 || MI->getOperand(0).getReg() == AArch64::Q30
21550 || MI->getOperand(0).getReg() == AArch64::Q31
21558 if (MI->getOperand(1).getReg() == AArch64::WZR ||
21560 MI->getOperand(1).getReg() == AArch64::XZR)
22066 MI->getOperand(0).getReg() == AArch64::D0
22067 || MI->getOperand(0).getReg() == AArch64::D1
22068 || MI->getOperand(0).getReg() == AArch64::D2
22069 || MI->getOperand(0).getReg() == AArch64::D3
22070 || MI->getOperand(0).getReg() == AArch64::D4
22071 || MI->getOperand(0).getReg() == AArch64::D5
22072 || MI->getOperand(0).getReg() == AArch64::D6
22073 || MI->getOperand(0).getReg() == AArch64::D7
22074 || MI->getOperand(0).getReg() == AArch64::D8
22075 || MI->getOperand(0).getReg() == AArch64::D9
22076 || MI->getOperand(0).getReg() == AArch64::D10
22077 || MI->getOperand(0).getReg() == AArch64::D11
22078 || MI->getOperand(0).getReg() == AArch64::D12
22079 || MI->getOperand(0).getReg() == AArch64::D13
22080 || MI->getOperand(0).getReg() == AArch64::D14
22081 || MI->getOperand(0).getReg() == AArch64::D15
22082 || MI->getOperand(0).getReg() == AArch64::D16
22083 || MI->getOperand(0).getReg() == AArch64::D17
22084 || MI->getOperand(0).getReg() == AArch64::D18
22085 || MI->getOperand(0).getReg() == AArch64::D19
22086 || MI->getOperand(0).getReg() == AArch64::D20
22087 || MI->getOperand(0).getReg() == AArch64::D21
22088 || MI->getOperand(0).getReg() == AArch64::D22
22089 || MI->getOperand(0).getReg() == AArch64::D23
22090 || MI->getOperand(0).getReg() == AArch64::D24
22091 || MI->getOperand(0).getReg() == AArch64::D25
22092 || MI->getOperand(0).getReg() == AArch64::D26
22093 || MI->getOperand(0).getReg() == AArch64::D27
22094 || MI->getOperand(0).getReg() == AArch64::D28
22095 || MI->getOperand(0).getReg() == AArch64::D29
22096 || MI->getOperand(0).getReg() == AArch64::D30
22097 || MI->getOperand(0).getReg() == AArch64::D31
22103 MI->getOperand(0).getReg() == AArch64::Q0
22104 || MI->getOperand(0).getReg() == AArch64::Q1
22105 || MI->getOperand(0).getReg() == AArch64::Q2
22106 || MI->getOperand(0).getReg() == AArch64::Q3
22107 || MI->getOperand(0).getReg() == AArch64::Q4
22108 || MI->getOperand(0).getReg() == AArch64::Q5
22109 || MI->getOperand(0).getReg() == AArch64::Q6
22110 || MI->getOperand(0).getReg() == AArch64::Q7
22111 || MI->getOperand(0).getReg() == AArch64::Q8
22112 || MI->getOperand(0).getReg() == AArch64::Q9
22113 || MI->getOperand(0).getReg() == AArch64::Q10
22114 || MI->getOperand(0).getReg() == AArch64::Q11
22115 || MI->getOperand(0).getReg() == AArch64::Q12
22116 || MI->getOperand(0).getReg() == AArch64::Q13
22117 || MI->getOperand(0).getReg() == AArch64::Q14
22118 || MI->getOperand(0).getReg() == AArch64::Q15
22119 || MI->getOperand(0).getReg() == AArch64::Q16
22120 || MI->getOperand(0).getReg() == AArch64::Q17
22121 || MI->getOperand(0).getReg() == AArch64::Q18
22122 || MI->getOperand(0).getReg() == AArch64::Q19
22123 || MI->getOperand(0).getReg() == AArch64::Q20
22124 || MI->getOperand(0).getReg() == AArch64::Q21
22125 || MI->getOperand(0).getReg() == AArch64::Q22
22126 || MI->getOperand(0).getReg() == AArch64::Q23
22127 || MI->getOperand(0).getReg() == AArch64::Q24
22128 || MI->getOperand(0).getReg() == AArch64::Q25
22129 || MI->getOperand(0).getReg() == AArch64::Q26
22130 || MI->getOperand(0).getReg() == AArch64::Q27
22131 || MI->getOperand(0).getReg() == AArch64::Q28
22132 || MI->getOperand(0).getReg() == AArch64::Q29
22133 || MI->getOperand(0).getReg() == AArch64::Q30
22134 || MI->getOperand(0).getReg() == AArch64::Q31
22148 MI->getOperand(0).getReg() == AArch64::D0
22149 || MI->getOperand(0).getReg() == AArch64::D1
22150 || MI->getOperand(0).getReg() == AArch64::D2
22151 || MI->getOperand(0).getReg() == AArch64::D3
22152 || MI->getOperand(0).getReg() == AArch64::D4
22153 || MI->getOperand(0).getReg() == AArch64::D5
22154 || MI->getOperand(0).getReg() == AArch64::D6
22155 || MI->getOperand(0).getReg() == AArch64::D7
22156 || MI->getOperand(0).getReg() == AArch64::D8
22157 || MI->getOperand(0).getReg() == AArch64::D9
22158 || MI->getOperand(0).getReg() == AArch64::D10
22159 || MI->getOperand(0).getReg() == AArch64::D11
22160 || MI->getOperand(0).getReg() == AArch64::D12
22161 || MI->getOperand(0).getReg() == AArch64::D13
22162 || MI->getOperand(0).getReg() == AArch64::D14
22163 || MI->getOperand(0).getReg() == AArch64::D15
22164 || MI->getOperand(0).getReg() == AArch64::D16
22165 || MI->getOperand(0).getReg() == AArch64::D17
22166 || MI->getOperand(0).getReg() == AArch64::D18
22167 || MI->getOperand(0).getReg() == AArch64::D19
22168 || MI->getOperand(0).getReg() == AArch64::D20
22169 || MI->getOperand(0).getReg() == AArch64::D21
22170 || MI->getOperand(0).getReg() == AArch64::D22
22171 || MI->getOperand(0).getReg() == AArch64::D23
22172 || MI->getOperand(0).getReg() == AArch64::D24
22173 || MI->getOperand(0).getReg() == AArch64::D25
22174 || MI->getOperand(0).getReg() == AArch64::D26
22175 || MI->getOperand(0).getReg() == AArch64::D27
22176 || MI->getOperand(0).getReg() == AArch64::D28
22177 || MI->getOperand(0).getReg() == AArch64::D29
22178 || MI->getOperand(0).getReg() == AArch64::D30
22179 || MI->getOperand(0).getReg() == AArch64::D31
22185 MI->getOperand(0).getReg() == AArch64::Q0
22186 || MI->getOperand(0).getReg() == AArch64::Q1
22187 || MI->getOperand(0).getReg() == AArch64::Q2
22188 || MI->getOperand(0).getReg() == AArch64::Q3
22189 || MI->getOperand(0).getReg() == AArch64::Q4
22190 || MI->getOperand(0).getReg() == AArch64::Q5
22191 || MI->getOperand(0).getReg() == AArch64::Q6
22192 || MI->getOperand(0).getReg() == AArch64::Q7
22193 || MI->getOperand(0).getReg() == AArch64::Q8
22194 || MI->getOperand(0).getReg() == AArch64::Q9
22195 || MI->getOperand(0).getReg() == AArch64::Q10
22196 || MI->getOperand(0).getReg() == AArch64::Q11
22197 || MI->getOperand(0).getReg() == AArch64::Q12
22198 || MI->getOperand(0).getReg() == AArch64::Q13
22199 || MI->getOperand(0).getReg() == AArch64::Q14
22200 || MI->getOperand(0).getReg() == AArch64::Q15
22201 || MI->getOperand(0).getReg() == AArch64::Q16
22202 || MI->getOperand(0).getReg() == AArch64::Q17
22203 || MI->getOperand(0).getReg() == AArch64::Q18
22204 || MI->getOperand(0).getReg() == AArch64::Q19
22205 || MI->getOperand(0).getReg() == AArch64::Q20
22206 || MI->getOperand(0).getReg() == AArch64::Q21
22207 || MI->getOperand(0).getReg() == AArch64::Q22
22208 || MI->getOperand(0).getReg() == AArch64::Q23
22209 || MI->getOperand(0).getReg() == AArch64::Q24
22210 || MI->getOperand(0).getReg() == AArch64::Q25
22211 || MI->getOperand(0).getReg() == AArch64::Q26
22212 || MI->getOperand(0).getReg() == AArch64::Q27
22213 || MI->getOperand(0).getReg() == AArch64::Q28
22214 || MI->getOperand(0).getReg() == AArch64::Q29
22215 || MI->getOperand(0).getReg() == AArch64::Q30
22216 || MI->getOperand(0).getReg() == AArch64::Q31
22230 MI->getOperand(0).getReg() == AArch64::D0
22231 || MI->getOperand(0).getReg() == AArch64::D1
22232 || MI->getOperand(0).getReg() == AArch64::D2
22233 || MI->getOperand(0).getReg() == AArch64::D3
22234 || MI->getOperand(0).getReg() == AArch64::D4
22235 || MI->getOperand(0).getReg() == AArch64::D5
22236 || MI->getOperand(0).getReg() == AArch64::D6
22237 || MI->getOperand(0).getReg() == AArch64::D7
22238 || MI->getOperand(0).getReg() == AArch64::D8
22239 || MI->getOperand(0).getReg() == AArch64::D9
22240 || MI->getOperand(0).getReg() == AArch64::D10
22241 || MI->getOperand(0).getReg() == AArch64::D11
22242 || MI->getOperand(0).getReg() == AArch64::D12
22243 || MI->getOperand(0).getReg() == AArch64::D13
22244 || MI->getOperand(0).getReg() == AArch64::D14
22245 || MI->getOperand(0).getReg() == AArch64::D15
22246 || MI->getOperand(0).getReg() == AArch64::D16
22247 || MI->getOperand(0).getReg() == AArch64::D17
22248 || MI->getOperand(0).getReg() == AArch64::D18
22249 || MI->getOperand(0).getReg() == AArch64::D19
22250 || MI->getOperand(0).getReg() == AArch64::D20
22251 || MI->getOperand(0).getReg() == AArch64::D21
22252 || MI->getOperand(0).getReg() == AArch64::D22
22253 || MI->getOperand(0).getReg() == AArch64::D23
22254 || MI->getOperand(0).getReg() == AArch64::D24
22255 || MI->getOperand(0).getReg() == AArch64::D25
22256 || MI->getOperand(0).getReg() == AArch64::D26
22257 || MI->getOperand(0).getReg() == AArch64::D27
22258 || MI->getOperand(0).getReg() == AArch64::D28
22259 || MI->getOperand(0).getReg() == AArch64::D29
22260 || MI->getOperand(0).getReg() == AArch64::D30
22261 || MI->getOperand(0).getReg() == AArch64::D31
22267 MI->getOperand(0).getReg() == AArch64::Q0
22268 || MI->getOperand(0).getReg() == AArch64::Q1
22269 || MI->getOperand(0).getReg() == AArch64::Q2
22270 || MI->getOperand(0).getReg() == AArch64::Q3
22271 || MI->getOperand(0).getReg() == AArch64::Q4
22272 || MI->getOperand(0).getReg() == AArch64::Q5
22273 || MI->getOperand(0).getReg() == AArch64::Q6
22274 || MI->getOperand(0).getReg() == AArch64::Q7
22275 || MI->getOperand(0).getReg() == AArch64::Q8
22276 || MI->getOperand(0).getReg() == AArch64::Q9
22277 || MI->getOperand(0).getReg() == AArch64::Q10
22278 || MI->getOperand(0).getReg() == AArch64::Q11
22279 || MI->getOperand(0).getReg() == AArch64::Q12
22280 || MI->getOperand(0).getReg() == AArch64::Q13
22281 || MI->getOperand(0).getReg() == AArch64::Q14
22282 || MI->getOperand(0).getReg() == AArch64::Q15
22283 || MI->getOperand(0).getReg() == AArch64::Q16
22284 || MI->getOperand(0).getReg() == AArch64::Q17
22285 || MI->getOperand(0).getReg() == AArch64::Q18
22286 || MI->getOperand(0).getReg() == AArch64::Q19
22287 || MI->getOperand(0).getReg() == AArch64::Q20
22288 || MI->getOperand(0).getReg() == AArch64::Q21
22289 || MI->getOperand(0).getReg() == AArch64::Q22
22290 || MI->getOperand(0).getReg() == AArch64::Q23
22291 || MI->getOperand(0).getReg() == AArch64::Q24
22292 || MI->getOperand(0).getReg() == AArch64::Q25
22293 || MI->getOperand(0).getReg() == AArch64::Q26
22294 || MI->getOperand(0).getReg() == AArch64::Q27
22295 || MI->getOperand(0).getReg() == AArch64::Q28
22296 || MI->getOperand(0).getReg() == AArch64::Q29
22297 || MI->getOperand(0).getReg() == AArch64::Q30
22298 || MI->getOperand(0).getReg() == AArch64::Q31
gen/lib/Target/ARM/ARMGenSubtargetInfo.inc19932 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19936 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19940 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19944 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19948 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19952 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19956 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19960 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19964 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
19968 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19972 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19976 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19980 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19984 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19988 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19992 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
19996 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20000 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20007 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20010 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20013 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20016 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20019 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20022 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20025 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20028 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20031 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20034 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
20037 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20040 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20043 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20046 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20049 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20052 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20055 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
20058 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21450 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21453 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21456 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21459 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21462 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21465 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21468 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21471 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21474 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21477 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21480 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21483 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21486 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21489 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21492 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21495 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21498 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21501 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21508 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21511 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21514 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21517 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21520 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21523 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21526 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21529 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21532 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21535 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
21538 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21541 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21544 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21547 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21550 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21553 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21556 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21559 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21680 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21684 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21688 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21692 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21696 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21700 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21704 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21708 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21712 && (Register::isVirtualRegister(MI->getOperand(0).getReg()))
21716 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21720 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21724 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21728 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21732 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21736 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21740 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21744 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
21748 && (Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22385 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22388 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22391 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22394 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22397 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22400 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22403 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22406 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22409 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22412 if ((Register::isVirtualRegister(MI->getOperand(0).getReg()))
22415 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22418 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22421 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22424 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22427 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22430 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22433 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
22436 if ((Register::isPhysicalRegister(MI->getOperand(0).getReg()))
gen/lib/Target/X86/X86GenInstrInfo.inc49351 && MI.getOperand(1).getReg() != 0
49353 && MI.getOperand(3).getReg() != 0
gen/lib/Target/X86/X86GenSubtargetInfo.inc21530 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21530 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21535 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21535 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21924 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21924 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21929 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21929 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21934 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21934 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21939 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21939 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21944 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21944 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21949 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21949 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21954 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21954 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21961 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21961 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21966 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21966 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21971 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21971 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21976 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21976 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21981 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21981 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21986 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21986 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21991 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21991 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21998 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
21998 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22003 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22003 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22008 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22008 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22013 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22013 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22018 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22018 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22023 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22023 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22030 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22030 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22035 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22035 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22040 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22040 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22045 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22045 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22050 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22050 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22055 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22055 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22060 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22060 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22067 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22067 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22072 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22072 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22077 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22077 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22082 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22082 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22087 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22087 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22092 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22092 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22097 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22097 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22104 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22104 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22109 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22109 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22114 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22114 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22119 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22119 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22124 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22124 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22129 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22129 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22134 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22134 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22141 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22141 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22146 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22146 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22151 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22151 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22156 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22156 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22161 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22161 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22166 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22166 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22367 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22367 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22372 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22372 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22377 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22377 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22382 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22382 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22389 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22389 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22394 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22394 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22399 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22399 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22404 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22404 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22411 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22411 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22416 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22416 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22421 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22421 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22426 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22426 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22435 && MI->getOperand(1).getReg() != X86::AX
22436 && MI->getOperand(1).getReg() != X86::EAX
22437 && MI->getOperand(1).getReg() != X86::RAX
22453 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
22453 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
22469 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22469 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22474 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22474 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22481 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22481 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22486 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22486 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22493 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22493 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22498 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22498 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22505 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22505 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22510 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22510 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22742 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22742 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22749 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22749 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22756 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22756 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22776 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22776 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22781 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22781 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22788 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22788 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22793 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22793 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22798 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22798 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22803 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22803 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22808 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22808 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22813 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22813 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22818 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22818 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22825 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22825 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22830 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22830 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22835 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22835 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22840 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22840 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22847 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22847 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22854 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22854 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22861 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22861 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22868 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22868 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22875 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22875 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22882 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22882 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22889 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22889 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22896 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22896 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22903 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22903 if (MI->getOperand(1).getReg() == MI->getOperand(2).getReg())
22925 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
22925 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
22933 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
22933 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()
22997 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
22997 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
23017 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
23017 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
23034 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
23034 return MI->getOperand(1).getReg() == MI->getOperand(2).getReg();
23042 return MI->getOperand(0).getReg() == MI->getOperand(1).getReg();
23042 return MI->getOperand(0).getReg() == MI->getOperand(1).getReg();
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h 101 if (Register::isPhysicalRegister(MO.getReg())) {
109 MachineInstr *NewMI = MRI.getVRegDef(MO.getReg());
201 dbgs() << MRI.getType(MO.getReg()) << "\n";
207 const LLT Ty = MRI.getType(MO.getReg());
501 unsigned Size = MRI.getType(MO.getReg()).getSizeInBits();
528 MRI.getType(MO.getReg()) != ISelInfo.TypeObjects[TypeID]) {
545 const LLT Ty = MRI.getType(MO.getReg());
577 RBI.getRegBank(MO.getReg(), MRI, TRI)) {
620 LLT Ty = MRI.getType(MO.getReg());
811 OutMIs[NewInsnID].addReg(State.MIs[OldInsnID]->getOperand(OpIdx).getReg(),
include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h 53 Register DstReg = MI.getOperand(0).getReg();
54 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
98 Register DstReg = MI.getOperand(0).getReg();
99 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
139 Register DstReg = MI.getOperand(0).getReg();
140 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
165 Register DstReg = MI.getOperand(0).getReg();
166 Register SrcReg = lookThroughCopyInstrs(MI.getOperand(1).getReg());
194 MI.getOperand(1).getReg(), MRI)) {
196 Register DstReg = MI.getOperand(0).getReg();
255 getDefIgnoringCopies(MI.getOperand(NumDefs).getReg(), MRI);
259 LLT OpTy = MRI.getType(MI.getOperand(NumDefs).getReg());
260 LLT DestTy = MRI.getType(MI.getOperand(0).getReg());
268 MergeI = getDefIgnoringCopies(SrcDef->getOperand(1).getReg(), MRI);
294 DstRegs.push_back(MI.getOperand(DefIdx).getReg());
301 = MRI.getType(MergeI->getOperand(0).getReg()).getElementType();
305 Builder.buildUnmerge(TmpRegs, MergeI->getOperand(Idx + 1).getReg());
310 Builder.buildUnmerge(DstRegs, MergeI->getOperand(Idx + 1).getReg());
331 Regs.push_back(MergeI->getOperand(Idx).getReg());
333 Builder.buildMerge(MI.getOperand(DefIdx).getReg(), Regs);
337 LLT MergeSrcTy = MRI.getType(MergeI->getOperand(1).getReg());
342 Register MergeSrc = MergeI->getOperand(Idx + 1).getReg();
343 Builder.buildInstr(ConvertOp, {MI.getOperand(Idx).getReg()},
356 MRI.replaceRegWith(MI.getOperand(Idx).getReg(),
357 MergeI->getOperand(Idx + 1).getReg());
391 unsigned Src = lookThroughCopyInstrs(MI.getOperand(1).getReg());
396 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
416 MI.getOperand(0).getReg(),
417 MergeI->getOperand(MergeSrcIdx + 1).getReg(),
453 for (auto &Use : MRI.use_instructions(MI.getOperand(0).getReg()))
470 return MI.getOperand(MI.getNumOperands() - 1).getReg();
472 return MI.getOperand(1).getReg();
513 if (PrevMI == &DefMI && MRI.hasOneUse(DefMI.getOperand(0).getReg()))
include/llvm/CodeGen/GlobalISel/MIPatternMatch.h 183 return (L.match(MRI, TmpMI->getOperand(1).getReg()) &&
184 R.match(MRI, TmpMI->getOperand(2).getReg())) ||
185 (Commutable && (R.match(MRI, TmpMI->getOperand(1).getReg()) &&
186 L.match(MRI, TmpMI->getOperand(2).getReg())));
251 return L.match(MRI, TmpMI->getOperand(1).getReg());
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 70 DstOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(DstType::Ty_Reg) {}
131 SrcOp(const MachineOperand &Op) : Reg(Op.getReg()), Ty(SrcType::Ty_Reg) {}
151 MIB.addUse(SrcMIB->getOperand(0).getReg());
167 return MRI.getType(SrcMIB->getOperand(0).getReg());
180 return SrcMIB->getOperand(0).getReg();
include/llvm/CodeGen/LiveRegUnits.h 56 Register Reg = O->getReg();
include/llvm/CodeGen/LiveVariables.h 217 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) {
253 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) {
include/llvm/CodeGen/MachineInstr.h 1076 return isDebugValue() && getOperand(0).isReg() && !getOperand(0).getReg().isValid();
1135 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
1135 return isCopy() && getOperand(0).getReg() == getOperand(1).getReg() &&
include/llvm/CodeGen/MachineInstrBuilder.h 85 Register getReg(unsigned Idx) const { return MI->getOperand(Idx).getReg(); }
503 getRenamableRegState(Register::isPhysicalRegister(RegOp.getReg()) &&
lib/CodeGen/AggressiveAntiDepBreaker.cpp 235 Register Reg = MO.getReg();
255 const Register Reg = MO.getReg();
368 Register Reg = MO.getReg();
378 Register Reg = MO.getReg();
421 Register Reg = MO.getReg();
474 Register Reg = MO.getReg();
509 Register Reg = MO.getReg();
lib/CodeGen/AntiDepBreaker.h 61 if (MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == OldReg)
lib/CodeGen/AsmPrinter/AsmPrinter.cpp 793 Register RegNo = MI->getOperand(0).getReg();
812 << printReg(Op.getReg(), AP.MF->getSubtarget().getRegisterInfo());
880 Reg = MI->getOperand(0).getReg();
lib/CodeGen/AsmPrinter/AsmPrinterInlineAsm.cpp 534 !TRI->isAsmClobberable(*MF, MI->getOperand(I + 1).getReg())) {
535 RestrRegs.push_back(TRI->getName(MI->getOperand(I + 1).getReg()));
lib/CodeGen/AsmPrinter/DbgEntityHistoryCalculator.cpp 50 return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : Register();
271 if (MO.isReg() && MO.isDef() && MO.getReg()) {
274 if (MI.isCall() && MO.getReg() == SP)
278 if (Register::isVirtualRegister(MO.getReg()))
279 clobberRegisterUses(RegVars, MO.getReg(), DbgValues, LiveEntries,
285 else if (MO.getReg() != FrameReg ||
288 for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid();
lib/CodeGen/AsmPrinter/DebugHandlerBase.cpp 37 Location.Register = Instruction.getOperand(0).getReg();
218 return MI->getOperand(0).isReg() && MI->getOperand(0).getReg();
lib/CodeGen/AsmPrinter/DwarfDebug.cpp 241 MachineLocation MLoc(RegOp.getReg(), Op1.isImm());
591 Register::isPhysicalRegister(MO.getReg())) {
593 if (TRI->regsOverlap(FwdReg, MO.getReg())) {
653 Register RegLoc = ParamValue->first.getReg();
730 CallReg = CalleeOp.getReg();
lib/CodeGen/BranchFolding.cpp 267 OperandHash = Op.getReg();
1882 Register Reg = MO.getReg();
1920 Register Reg = MO.getReg();
1948 Register Reg = MO.getReg();
2021 Register Reg = MO.getReg();
2071 Register Reg = MO.getReg();
2089 Register Reg = MO.getReg();
lib/CodeGen/BreakFalseDeps.cpp 112 Register OriginalReg = MO.getReg();
132 !OpRC->contains(CurrMO.getReg()))
136 MO.setReg(CurrMO.getReg());
165 Register reg = MI->getOperand(OpIdx).getReg();
203 if (!MO.isReg() || !MO.getReg())
237 if (!LiveRegSet.contains(UndefMI->getOperand(OpIdx).getReg()))
lib/CodeGen/CalcSpillWeights.cpp 56 if (mi->getOperand(0).getReg() == reg) {
58 hreg = mi->getOperand(1).getReg();
62 hreg = mi->getOperand(0).getReg();
108 if (MI->getOperand(0).getReg() != Reg)
112 Reg = MI->getOperand(1).getReg();
lib/CodeGen/CriticalAntiDepBreaker.cpp 190 Register Reg = MO.getReg();
275 Register Reg = MO.getReg();
306 Register Reg = MO.getReg();
368 CheckOper.getReg() != NewReg)
616 Register Reg = MO.getReg();
lib/CodeGen/DeadMachineInstructionElim.cpp 78 Register Reg = MO.getReg();
143 Register Reg = MO.getReg();
162 Register Reg = MO.getReg();
lib/CodeGen/DetectDeadLanes.cpp 157 Register SrcReg = MO.getReg();
197 Register MOReg = MO.getReg();
222 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
234 DefinedByCopy[Register::virtReg2Index(MI.getOperand(0).getReg())]);
253 Register DefReg = Def.getReg();
288 Register DefReg = Def.getReg();
348 DefinedLanes &= MRI->getMaxLaneMaskForVReg(Def.getReg());
380 Register MOReg = MO.getReg();
431 Register DefReg = Def.getReg();
473 Register DefReg = Def.getReg();
485 Register MOReg = MO.getReg();
539 Register Reg = MO.getReg();
lib/CodeGen/EarlyIfConversion.cpp 262 Register Reg = MO.getReg();
382 Register Reg = MO.getReg();
514 PI.TReg = PI.PHI->getOperand(i).getReg();
516 PI.FReg = PI.PHI->getOperand(i).getReg();
569 Register DstReg = PI.PHI->getOperand(0).getReg();
596 Register PHIDst = PI.PHI->getOperand(0).getReg();
lib/CodeGen/ExecutionDomainFix.cpp 246 for (int rx : regIndices(MO.getReg())) {
265 for (int rx : regIndices(mo.getReg())) {
275 for (int rx : regIndices(mo.getReg())) {
296 for (int rx : regIndices(mo.getReg())) {
386 for (int rx : regIndices(mo.getReg())) {
lib/CodeGen/ExpandPostRAPseudos.cpp 82 Register DstReg = MI->getOperand(0).getReg();
83 Register InsReg = MI->getOperand(2).getReg();
146 bool IdentityCopy = (SrcMO.getReg() == DstMO.getReg());
146 bool IdentityCopy = (SrcMO.getReg() == DstMO.getReg());
166 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
166 DstMO.getReg(), SrcMO.getReg(), SrcMO.isKill());
lib/CodeGen/GlobalISel/CSEInfo.cpp 336 Register Reg = MO.getReg();
lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp 132 return buildCopy(Op.getReg(), MIB->getOperand(0).getReg());
lib/CodeGen/GlobalISel/CallLowering.cpp 468 return MIB->getOperand(0).getReg();
lib/CodeGen/GlobalISel/CombinerHelper.cpp 75 Register DstReg = MI.getOperand(0).getReg();
76 Register SrcReg = MI.getOperand(1).getReg();
86 Register DstReg = MI.getOperand(0).getReg();
87 Register SrcReg = MI.getOperand(1).getReg();
116 Register Reg = MO.getReg();
128 Ops.push_back(BuildVecMO.getReg());
138 assert(MRI.getType(Undef->getOperand(0).getReg()) ==
145 Ops.push_back(Undef->getOperand(0).getReg());
158 Register DstReg = MI.getOperand(0).getReg();
189 LLT DstType = MRI.getType(MI.getOperand(0).getReg());
190 Register Src1 = MI.getOperand(1).getReg();
235 Register Src2 = MI.getOperand(2).getReg();
253 Register DstReg = MI.getOperand(0).getReg();
374 LLT LoadValueTy = MRI.getType(LoadValue.getReg());
402 for (auto &UseMI : MRI.use_instructions(LoadValue.getReg())) {
407 MRI.getType(UseMI.getOperand(0).getReg()),
426 Register ChosenDstReg = Preferred.MI->getOperand(0).getReg();
437 UseMO.setReg(PreviouslyEmitted->getOperand(0).getReg());
443 Register NewDstReg = MRI.cloneVirtualRegister(MI.getOperand(0).getReg());
460 for (auto &UseMO : MRI.use_operands(LoadValue.getReg()))
470 Register UseDstReg = UseMI->getOperand(0).getReg();
566 Base = MI.getOperand(1).getReg();
577 Offset = Use.getOperand(2).getReg();
600 for (auto &GEPUse : MRI.use_instructions(Use.getOperand(0).getReg())) {
615 Addr = Use.getOperand(0).getReg();
633 Addr = MI.getOperand(1).getReg();
638 Base = AddrDef->getOperand(1).getReg();
639 Offset = AddrDef->getOperand(2).getReg();
657 if (Base == MI.getOperand(0).getReg()) {
664 if (MI.getOperand(0).getReg() == Addr) {
719 MIB.addUse(MI.getOperand(0).getReg());
721 MIB.addDef(MI.getOperand(0).getReg());
768 MachineInstr *CmpMI = MRI.getVRegDef(BrCond->getOperand(0).getReg());
770 !MRI.hasOneUse(CmpMI->getOperand(0).getReg()))
786 MachineInstr *CmpMI = MRI.getVRegDef(BrCond->getOperand(0).getReg());
1265 Register Dst = MI.getOperand(1).getReg();
1266 Register Src = MI.getOperand(2).getReg();
1267 Register Len = MI.getOperand(3).getReg();
lib/CodeGen/GlobalISel/GISelKnownBits.cpp 66 return getKnownBits(MI.getOperand(0).getReg());
134 if (Dst.getSubReg() == 0 /*NoSubRegister*/ && Src.getReg().isVirtual() &&
136 MRI.getType(Src.getReg()).isValid()) {
138 computeKnownBitsImpl(Src.getReg(), Known, DemandedElts, Depth);
158 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
163 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,
170 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
172 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
184 LLT Ty = MRI.getType(MI.getOperand(1).getReg());
197 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
201 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,
212 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
214 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
225 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
227 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
237 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts,
239 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known2, DemandedElts,
258 computeKnownBitsImpl(MI.getOperand(3).getReg(), Known, DemandedElts,
263 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts,
280 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
288 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
312 computeKnownBitsImpl(MI.getOperand(2).getReg(), RHSKnown, DemandedElts,
316 MachineInstr *RHSMI = MRI.getVRegDef(MI.getOperand(2).getReg());
323 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts,
350 Register SrcReg = MI.getOperand(1).getReg();
lib/CodeGen/GlobalISel/IRTranslator.cpp 1911 Idx = MIRBuilder.buildSExtOrTrunc(VecIdxTy, Idx)->getOperand(0).getReg();
lib/CodeGen/GlobalISel/InstructionSelect.cpp 170 Register SrcReg = MI.getOperand(1).getReg();
171 Register DstReg = MI.getOperand(0).getReg();
lib/CodeGen/GlobalISel/InstructionSelector.cpp 51 if (MO.isReg() && MO.getReg())
52 if (auto VRegVal = getConstantVRegValWithLookThrough(MO.getReg(), MRI))
62 MachineInstr *RootI = MRI.getVRegDef(Root.getReg());
67 MachineInstr *RHSI = MRI.getVRegDef(RHS.getReg());
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 386 Args.push_back({MI.getOperand(i).getReg(), OpType});
387 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), OpType},
400 Register Reg = MI.getOperand(i).getReg();
485 return createLibcall(MIRBuilder, Libcall, {MI.getOperand(0).getReg(), ToType},
486 {{MI.getOperand(1).getReg(), FromType}});
491 LLT LLTy = MRI.getType(MI.getOperand(0).getReg());
539 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
540 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
551 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
552 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
564 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
565 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
579 unsigned FromSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
580 unsigned ToSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
602 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
618 MIRBuilder.buildUndef(NarrowTy)->getOperand(0).getReg());
620 Register DstReg = MI.getOperand(0).getReg();
629 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
654 insertParts(MI.getOperand(0).getReg(),
664 Register SrcReg = MI.getOperand(1).getReg();
679 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {SrcReg, Shift.getReg(0)});
687 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
696 SmallVector<Register, 4> Srcs = {MI.getOperand(1).getReg()};
699 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), Srcs);
707 uint64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
713 auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1).getReg());
714 MIRBuilder.buildCopy(MI.getOperand(0).getReg(), Unmerge.getReg(0));
728 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
729 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
746 Register DstReg = MI.getOperand(0).getReg();
763 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src1Regs);
764 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src2Regs);
782 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
795 Register DstReg = MI.getOperand(0).getReg();
803 MIRBuilder.buildLoad(TmpReg, MI.getOperand(1).getReg(), MMO);
814 Register DstReg = MI.getOperand(0).getReg();
815 Register PtrReg = MI.getOperand(1).getReg();
841 Register SrcReg = MI.getOperand(0).getReg();
856 MIRBuilder.buildStore(TmpReg, MI.getOperand(1).getReg(), MMO);
921 extractParts(MI.getOperand(i).getReg(), NarrowTy, NumParts,
934 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), DstRegs);
951 uint64_t SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
958 MIRBuilder.buildUnmerge({LHSL, LHSH}, MI.getOperand(2).getReg());
962 MIRBuilder.buildUnmerge({RHSL, RHSH}, MI.getOperand(3).getReg());
966 LLT ResTy = MRI.getType(MI.getOperand(0).getReg());
973 MIRBuilder.buildICmp(Pred, MI.getOperand(0).getReg(), Or, Zero);
980 MIRBuilder.buildSelect(MI.getOperand(0).getReg(), CmpHEQ, CmpLU, CmpH);
1001 auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1.getReg());
1002 MO1.setReg(TruncMIB->getOperand(0).getReg());
1007 MIRBuilder.buildInstr(TargetOpcode::G_SEXT, {MO2.getReg()}, {DstExt});
1034 MIRBuilder.buildUnmerge(SrcRegs, MI.getOperand(1).getReg());
1039 .getReg();
1058 .getReg());
1067 .getReg());
1073 Register DstReg = MI.getOperand(0).getReg();
1084 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
1085 MO.setReg(ExtB->getOperand(0).getReg());
1092 {MO.getReg()});
1093 MO.setReg(ExtB->getOperand(0).getReg());
1101 MIRBuilder.buildInstr(TruncOpcode, {MO.getReg()}, {DstExt});
1110 MIRBuilder.buildInstr(ExtOpcode, {MO.getReg()}, {DstTrunc});
1119 MIRBuilder.buildExtract(MO.getReg(), DstExt, 0);
1127 LLT OldTy = MRI.getType(MO.getReg());
1136 Parts.push_back(MO.getReg());
1149 MIRBuilder.buildInsert(MoreReg, ImpDef, MO.getReg(), 0);
1159 Register DstReg = MI.getOperand(0).getReg();
1164 Register Src1 = MI.getOperand(1).getReg();
1182 Register SrcReg = MI.getOperand(I).getReg();
1236 Register SrcReg = MI.getOperand(I).getReg();
1282 Register SrcReg = MI.getOperand(NumDst).getReg();
1287 Register Dst0Reg = MI.getOperand(0).getReg();
1306 MI.getOperand(NumDst).setReg(WideSrc->getOperand(0).getReg());
1318 Register DstReg = MI.getOperand(0).getReg();
1319 Register SrcReg = MI.getOperand(1).getReg();
1426 {MI.getOperand(2).getReg()});
1428 {MI.getOperand(3).getReg()});
1434 LLT OrigTy = MRI.getType(MI.getOperand(0).getReg());
1440 MIRBuilder.buildICmp(CmpInst::ICMP_NE, MI.getOperand(1).getReg(), NewOp,
1443 MIRBuilder.buildTrunc(MI.getOperand(0).getReg(), NewOp);
1459 Register SrcReg = MI.getOperand(1).getReg();
1492 Register DstReg = MI.getOperand(0).getReg();
1518 Register DstReg = MI.getOperand(0).getReg();
1616 bool IsVec = MRI.getType(MI.getOperand(1).getReg()).isVector();
1662 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1776 Register VecReg = MI.getOperand(1).getReg();
1801 Register VecReg = MI.getOperand(1).getReg();
1921 .addUse(MI.getOperand(1).getReg())
1922 .addUse(MI.getOperand(2).getReg());
1925 MIRBuilder.buildMul(ProdReg, QuotReg, MI.getOperand(2).getReg());
1926 MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1926 MIRBuilder.buildSub(MI.getOperand(0).getReg(), MI.getOperand(1).getReg(),
1938 Register Res = MI.getOperand(0).getReg();
1939 Register Overflow = MI.getOperand(1).getReg();
1940 Register LHS = MI.getOperand(2).getReg();
1941 Register RHS = MI.getOperand(3).getReg();
1980 Register Res = MI.getOperand(0).getReg();
2002 Register SubByReg = MI.getOperand(1).getReg();
2003 Register ZeroReg = Zero->getOperand(0).getReg();
2015 Register Res = MI.getOperand(0).getReg();
2016 Register LHS = MI.getOperand(1).getReg();
2017 Register RHS = MI.getOperand(2).getReg();
2027 Register OldValRes = MI.getOperand(0).getReg();
2028 Register SuccessRes = MI.getOperand(1).getReg();
2029 Register Addr = MI.getOperand(2).getReg();
2030 Register CmpVal = MI.getOperand(3).getReg();
2031 Register NewVal = MI.getOperand(4).getReg();
2042 Register DstReg = MI.getOperand(0).getReg();
2043 Register PtrReg = MI.getOperand(1).getReg();
2133 Register SrcReg = MI.getOperand(0).getReg();
2134 Register PtrReg = MI.getOperand(1).getReg();
2178 Register Res = MI.getOperand(0).getReg();
2179 Register CarryOut = MI.getOperand(1).getReg();
2180 Register LHS = MI.getOperand(2).getReg();
2181 Register RHS = MI.getOperand(3).getReg();
2190 Register Res = MI.getOperand(0).getReg();
2191 Register CarryOut = MI.getOperand(1).getReg();
2192 Register LHS = MI.getOperand(2).getReg();
2193 Register RHS = MI.getOperand(3).getReg();
2194 Register CarryIn = MI.getOperand(4).getReg();
2208 Register Res = MI.getOperand(0).getReg();
2209 Register BorrowOut = MI.getOperand(1).getReg();
2210 Register LHS = MI.getOperand(2).getReg();
2211 Register RHS = MI.getOperand(3).getReg();
2220 Register Res = MI.getOperand(0).getReg();
2221 Register BorrowOut = MI.getOperand(1).getReg();
2222 Register LHS = MI.getOperand(2).getReg();
2223 Register RHS = MI.getOperand(3).getReg();
2224 Register BorrowIn = MI.getOperand(4).getReg();
2263 Register DstReg = MI.getOperand(0).getReg();
2264 Register SrcReg = MI.getOperand(1).getReg();
2269 MIRBuilder.buildInstr(TargetOpcode::G_SHL, {TmpRes}, {SrcReg, MIBSz->getOperand(0).getReg()});
2270 MIRBuilder.buildInstr(TargetOpcode::G_ASHR, {DstReg}, {TmpRes, MIBSz->getOperand(0).getReg()});
2290 Register DstReg = MI.getOperand(0).getReg();
2319 const Register DstReg = MI.getOperand(0).getReg();
2343 MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(), Offset);
2359 MIRBuilder.buildExtract(PartOpReg, MI.getOperand(I).getReg(),
2374 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, Src0Regs);
2377 extractParts(MI.getOperand(2).getReg(), NarrowTy, NumParts, Src1Regs);
2380 extractParts(MI.getOperand(3).getReg(), NarrowTy, NumParts, Src2Regs);
2428 const Register DstReg = MI.getOperand(0).getReg();
2446 Register SrcReg = MI.getOperand(I).getReg();
2508 Register DstReg = MI.getOperand(0).getReg();
2509 Register SrcReg = MI.getOperand(1).getReg();
2554 Register DstReg = MI.getOperand(0).getReg();
2555 Register Src0Reg = MI.getOperand(2).getReg();
2593 extractParts(MI.getOperand(2).getReg(), NarrowTy1, NumParts, Src1Regs);
2594 extractParts(MI.getOperand(3).getReg(), NarrowTy1, NumParts, Src2Regs);
2621 Register DstReg = MI.getOperand(0).getReg();
2622 Register CondReg = MI.getOperand(1).getReg();
2669 extractParts(MI.getOperand(1).getReg(), NarrowTy1, NumParts, Src0Regs);
2671 extractParts(MI.getOperand(2).getReg(), NarrowTy0, NumParts, Src1Regs);
2672 extractParts(MI.getOperand(3).getReg(), NarrowTy0, NumParts, Src2Regs);
2693 const Register DstReg = MI.getOperand(0).getReg();
2734 Register SrcReg = MI.getOperand(I).getReg();
2765 const Register SrcReg = MI.getOperand(NumDst).getReg();
2768 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
2789 MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg());
2802 Register DstReg = MI.getOperand(0).getReg();
2834 Register SrcReg = MI.getOperand(SrcIdx + 1).getReg();
2872 Register ValReg = MI.getOperand(0).getReg();
2873 Register AddrReg = MI.getOperand(1).getReg();
3047 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
3050 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {InL, InH});
3123 MIRBuilder.buildMerge(MI.getOperand(0).getReg(), {Lo.getReg(), Hi.getReg()});
3140 Register DstReg = MI.getOperand(0).getReg();
3145 Register Amt = MI.getOperand(2).getReg();
3171 MIRBuilder.buildUnmerge({InL, InH}, MI.getOperand(1).getReg());
3313 if (MRI.getType(MI.getOperand(1).getReg()).isVector())
3326 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
3332 MIB.addDef(MI.getOperand(I).getReg());
3338 MIB.addUse(MI.getOperand(NumDst).getReg());
3414 Register DstReg = MI.getOperand(0).getReg();
3415 Register Src1 = MI.getOperand(1).getReg();
3416 Register Src2 = MI.getOperand(2).getReg();
3455 int64_t SizeOp1 = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
3464 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3466 Register OpReg = MI.getOperand(0).getReg();
3503 Register DstReg = MI.getOperand(0).getReg();
3519 uint64_t SizeOp0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
3531 extractParts(MI.getOperand(1).getReg(), NarrowTy, NumParts, SrcRegs);
3533 Register OpReg = MI.getOperand(2).getReg();
3578 Register DstReg = MI.getOperand(0).getReg();
3590 Register DstReg = MI.getOperand(0).getReg();
3599 if (!extractParts(MI.getOperand(1).getReg(), DstTy, NarrowTy, LeftoverTy,
3604 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, Unused,
3611 DstRegs.push_back(Inst->getOperand(0).getReg());
3618 DstLeftoverRegs.push_back(Inst->getOperand(0).getReg());
3634 Register CondReg = MI.getOperand(1).getReg();
3639 Register DstReg = MI.getOperand(0).getReg();
3646 if (!extractParts(MI.getOperand(2).getReg(), DstTy, NarrowTy, LeftoverTy,
3651 if (!extractParts(MI.getOperand(3).getReg(), DstTy, NarrowTy, Unused,
3658 DstRegs.push_back(Select->getOperand(0).getReg());
3664 DstLeftoverRegs.push_back(Select->getOperand(0).getReg());
3693 Register SrcReg = MI.getOperand(1).getReg();
3703 MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3727 Op = MIBOp->getOperand(0).getReg();
3730 MIRBuilder.buildInstr(TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3743 Register SrcReg = MI.getOperand(1).getReg();
3754 MIRBuilder.buildSelect(MI.getOperand(0).getReg(), MIBICmp, MIBLen,
3774 TargetOpcode::G_SUB, {MI.getOperand(0).getReg()},
3781 MI.getOperand(1).setReg(MIBTmp->getOperand(0).getReg());
3791 Register Dst = MI.getOperand(0).getReg();
3792 Register Src = MI.getOperand(1).getReg();
3847 Register Dst = MI.getOperand(0).getReg();
3848 Register Src = MI.getOperand(1).getReg();
3868 Register Dst = MI.getOperand(0).getReg();
3869 Register Src = MI.getOperand(1).getReg();
3906 Register Dst = MI.getOperand(0).getReg();
3907 Register Src = MI.getOperand(1).getReg();
3963 Register Dst = MI.getOperand(0).getReg();
3964 Register Src0 = MI.getOperand(1).getReg();
3965 Register Src1 = MI.getOperand(2).getReg();
3979 Register Dst = MI.getOperand(0).getReg();
3980 Register Src0 = MI.getOperand(1).getReg();
3981 Register Src1 = MI.getOperand(2).getReg();
4030 Register Dst = MI.getOperand(0).getReg();
4031 Register Src0 = MI.getOperand(1).getReg();
4032 Register Src1 = MI.getOperand(2).getReg();
4058 Register DstReg = MI.getOperand(0).getReg();
4072 const Register SrcReg = MI.getOperand(NumDst).getReg();
4075 Register Dst0Reg = MI.getOperand(0).getReg();
4104 Register DstReg = MI.getOperand(0).getReg();
4105 Register Src0Reg = MI.getOperand(1).getReg();
4106 Register Src1Reg = MI.getOperand(2).getReg();
4163 Register Dst = MI.getOperand(0).getReg();
4164 Register AllocSize = MI.getOperand(1).getReg();
4198 Register Dst = MI.getOperand(0).getReg();
4199 Register Src = MI.getOperand(1).getReg();
4230 Register Dst = MI.getOperand(0).getReg();
4231 Register Src = MI.getOperand(1).getReg();
4232 Register InsertSrc = MI.getOperand(2).getReg();
4270 Register Dst0 = MI.getOperand(0).getReg();
4271 Register Dst1 = MI.getOperand(1).getReg();
4272 Register LHS = MI.getOperand(2).getReg();
4273 Register RHS = MI.getOperand(3).getReg();
lib/CodeGen/GlobalISel/LegalizerInfo.cpp 398 return MRI.getType(MI.getOperand(MI.getNumOperands() - 1).getReg());
399 return MRI.getType(MI.getOperand(OpIdx).getReg());
lib/CodeGen/GlobalISel/Localizer.cpp 82 Register Reg = MI.getOperand(0).getReg();
124 Register Reg = MI.getOperand(0).getReg();
180 Register Reg = MI->getOperand(0).getReg();
lib/CodeGen/GlobalISel/RegBankSelect.cpp 148 Register Src = MO.getReg();
173 LLT RegTy = MRI->getType(MO.getReg());
194 .addDef(MO.getReg());
206 UnMergeBuilder.addUse(MO.getReg());
243 const RegisterBank *CurRegBank = RBI->getRegBank(MO.getReg(), *MRI, *TRI);
279 RBI->getSizeInBits(MO.getReg(), *MRI, *TRI));
400 Register Reg = MO.getReg();
471 Register Reg = MO.getReg();
597 Register Reg = MO.getReg();
761 Register Reg = MO.getReg();
789 assert(!It->modifiesRegister(MO.getReg(), &TRI) &&
807 assert(It->modifiesRegister(MO.getReg(), &TRI) &&
lib/CodeGen/GlobalISel/RegisterBankInfo.cpp 182 Register Reg = MO.getReg();
216 unsigned ResultSize = getSizeInBits(MI.getOperand(0).getReg(),
231 Register Reg = MO.getReg();
446 if (!MO.getReg()) {
462 Register OrigReg = MO.getReg();
610 Register Reg = MO.getReg();
790 OS << '(' << printReg(getMI().getOperand(Idx).getReg(), TRI) << ", [";
lib/CodeGen/GlobalISel/Utils.cpp 46 Register Reg = RegMO.getReg();
75 Register Reg = RegMO.getReg();
131 Register Reg = MO.getReg();
171 Register Reg = MO.getReg();
235 MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
252 MRI.getType(MI->getOperand(0).getReg()).getSizeInBits()));
253 VReg = MI->getOperand(1).getReg();
256 VReg = MI->getOperand(1).getReg();
261 VReg = MI->getOperand(1).getReg();
306 auto DstTy = MRI.getType(DefMI->getOperand(0).getReg());
310 Register SrcReg = DefMI->getOperand(1).getReg();
lib/CodeGen/IfConversion.cpp 1948 Register Reg = MO.getReg();
2116 Register Reg = MO.getReg();
lib/CodeGen/ImplicitNullChecks.cpp 278 if (!(MOA.isReg() && MOA.getReg()))
281 Register RegA = MOA.getReg();
283 if (!(MOB.isReg() && MOB.getReg()))
286 Register RegB = MOB.getReg();
369 !BaseOp->isReg() || BaseOp->getReg() != PointerReg)
416 if (!(DependenceMO.isReg() && DependenceMO.getReg()))
436 if (AnyAliasLiveIn(TRI, NullSucc, DependenceMO.getReg()))
443 TRI->regsOverlap(DependenceMO.getReg(), PointerReg)) &&
520 const Register PointerReg = MBP.LHS.getReg();
601 return MO.isReg() && MO.getReg() && MO.isDef() &&
602 TRI->regsOverlap(MO.getReg(), PointerReg);
626 DefReg = MI->getOperand(0).getReg();
692 Register Reg = MO.getReg();
700 if (!MO.isReg() || !MO.getReg() || !MO.isDef())
702 if (!NC.getNotNullSucc()->isLiveIn(MO.getReg()))
703 NC.getNotNullSucc()->addLiveIn(MO.getReg());
lib/CodeGen/InlineSpiller.cpp 264 if (MI.getOperand(0).getReg() == Reg)
265 return MI.getOperand(1).getReg();
266 if (MI.getOperand(1).getReg() == Reg)
267 return MI.getOperand(0).getReg();
379 Register SrcReg = CopyMI.getOperand(1).getReg();
512 LiveInterval &SnipLI = LIS.getInterval(MI->getOperand(1).getReg());
559 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg)
624 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) {
816 ImpReg = MO.getReg();
847 Register Reg = MO->getReg();
886 if (MO.getReg() == ImpReg)
lib/CodeGen/LiveDebugValues.cpp 89 return MI.getOperand(0).isReg() ? MI.getOperand(0).getReg() : Register();
697 assert(MI.getOperand(0).isReg() && MI.getOperand(0).getReg() == 0 &&
815 if (MO.isReg() && MO.isDef() && MO.getReg() &&
816 Register::isPhysicalRegister(MO.getReg()) &&
817 !(MI.isCall() && MO.getReg() == SP)) {
819 for (MCRegAliasIterator RAI(MO.getReg(), TRI, true); RAI.isValid(); ++RAI)
868 Reg = MO.getReg();
907 Reg = MI.getOperand(0).getReg();
1013 Register SrcReg = SrcRegOp->getReg();
1014 Register DestReg = DestRegOp->getReg();
1301 return Op.isReg() && Op.getReg() != SP && Op.getReg() != FP;
1301 return Op.isReg() && Op.getReg() != SP && Op.getReg() != FP;
lib/CodeGen/LiveDebugVariables.cpp 229 if (LocMO.getReg() == 0)
234 locations[i].getReg() == LocMO.getReg() &&
234 locations[i].getReg() == LocMO.getReg() &&
569 Register::isVirtualRegister(locations[i].getReg()))
570 LDV->mapVirtReg(locations[i].getReg(), this);
617 Register::isVirtualRegister(MI.getOperand(0).getReg())) {
618 const Register Reg = MI.getOperand(0).getReg();
778 Register DstReg = MI->getOperand(0).getReg();
855 if (Register::isVirtualRegister(LocMO.getReg())) {
858 if (LIS.hasInterval(LocMO.getReg())) {
859 LI = &LIS.getInterval(LocMO.getReg());
1123 if (!Loc->isReg() || Loc->getReg() != OldReg)
1171 if (Loc.isReg() && Loc.getReg() &&
1172 Register::isVirtualRegister(Loc.getReg())) {
1173 Register VirtReg = Loc.getReg();
1269 Register Reg = LocMO.getReg();
lib/CodeGen/LiveInterval.cpp 906 if (MOI->getReg() != Reg)
lib/CodeGen/LiveIntervals.cpp 779 if (!MO.isReg() || MO.getReg() != Reg)
989 Register Reg = MO.getReg();
1447 Register::isPhysicalRegister(MO->getReg()) &&
1448 TRI.hasRegUnit(MO->getReg(), Reg))
1514 if (!MO.isReg() || MO.getReg() != Reg)
1603 if (MOI->isReg() && Register::isVirtualRegister(MOI->getReg()) &&
1604 !hasInterval(MOI->getReg())) {
1605 createAndComputeVirtRegInterval(MOI->getReg());
lib/CodeGen/LivePhysRegs.cpp 49 Register Reg = O->getReg();
63 Register Reg = O->getReg();
89 Register Reg = O->getReg();
295 Register Reg = MO->getReg();
312 Register Reg = MO->getReg();
lib/CodeGen/LiveRangeEdit.cpp 113 if (!MO.isReg() || !MO.getReg() || !MO.readsReg())
117 if (Register::isPhysicalRegister(MO.getReg())) {
118 if (MRI.isConstantPhysReg(MO.getReg()))
123 LiveInterval &li = LIS.getInterval(MO.getReg());
294 Dest = MI->getOperand(0).getReg();
311 Register Reg = MOI->getReg();
352 if (MO.isReg() && Register::isPhysicalRegister(MO.getReg()))
lib/CodeGen/LiveRangeShrink.cpp 144 UseMap[MO.getReg()] = std::make_pair(CurrentOrder, &MI);
145 else if (MO.isDead() && UseMap.count(MO.getReg()))
148 if (Barrier < UseMap[MO.getReg()].first) {
149 Barrier = UseMap[MO.getReg()].first;
150 BarrierMI = UseMap[MO.getReg()].second;
175 Register Reg = MO.getReg();
192 MRI.getRegClass(DefMO->getReg()) ==
193 MRI.getRegClass(MO.getReg())) {
237 EndIter->getOperand(0).getReg() == MI.getOperand(0).getReg();
237 EndIter->getOperand(0).getReg() == MI.getOperand(0).getReg();
lib/CodeGen/LiveRegUnits.cpp 50 Register Reg = O->getReg();
62 Register Reg = O->getReg();
73 Register Reg = O->getReg();
lib/CodeGen/LiveVariables.cpp 216 if (!MO.isReg() || !MO.isDef() || MO.getReg() == 0)
218 Register DefReg = MO.getReg();
405 bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg;
521 if (!MO.isReg() || MO.getReg() == 0)
523 Register MOReg = MO.getReg();
694 Register Reg = MO.getReg();
716 .push_back(BBI.getOperand(i).getReg());
773 Defs.insert(BBI->getOperand(0).getReg());
778 getVarInfo(BBI->getOperand(i).getReg()).AliveBlocks.set(NumNew);
785 if (I->isReg() && Register::isVirtualRegister(I->getReg())) {
787 Defs.insert(I->getReg());
789 Kills.insert(I->getReg());
lib/CodeGen/MIRCanonicalizerPass.cpp 173 if (Register::isVirtualRegister(MO.getReg()))
179 PhysRegDefs.push_back(MO.getReg());
190 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
203 if (!Register::isVirtualRegister(II->getOperand(i).getReg()))
204 if (llvm::find(PhysRegDefs, II->getOperand(i).getReg()) ==
225 for (auto &UO : MRI->use_nodbg_operands(MO.getReg())) {
323 const Register Dst = MI->getOperand(0).getReg();
324 const Register Src = MI->getOperand(1).getReg();
429 Register vRegToRename = MI.getOperand(0).getReg();
lib/CodeGen/MIRParser/MIParser.cpp 1122 getRegisterName(TRI, I.getReg()) + "'");
lib/CodeGen/MIRVRegNamerUtils.cpp 61 const Register Dst = MI->getOperand(0).getReg();
150 RegQueue.push(TypedVReg(MO.getReg()));
279 if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
283 RegQueue.push(TypedVReg(MO.getReg()));
301 RegQueue.push(MO.isReg() ? TypedVReg(MO.getReg())
lib/CodeGen/MachineBasicBlock.cpp 508 if (I->getOperand(1).getReg() == PhysReg) {
509 Register VirtReg = I->getOperand(0).getReg();
908 if (!OI->isReg() || OI->getReg() == 0 ||
911 Register Reg = OI->getReg();
929 if (!OI->isReg() || OI->getReg() == 0)
932 Register Reg = OI->getReg();
1032 Register Reg = MO.getReg();
lib/CodeGen/MachineCSE.cpp 170 Register Reg = MO.getReg();
177 Register SrcReg = DefMI->getOperand(1).getReg();
237 if (!MO.isReg() || !MO.getReg())
239 if (!TRI->regsOverlap(MO.getReg(), Reg))
285 Register Reg = MO.getReg();
304 Register Reg = MO.getReg();
381 Register MOReg = MO.getReg();
466 if (MO.isReg() && MO.isUse() && Register::isVirtualRegister(MO.getReg())) {
598 Register OldReg = MO.getReg();
599 Register NewReg = CSMI->getOperand(i).getReg();
781 if (!Register::isVirtualRegister(def.getReg()))
785 if (use.isReg() && !Register::isVirtualRegister(use.getReg()))
827 Register VReg = MI->getOperand(0).getReg();
lib/CodeGen/MachineCombiner.cpp 140 if (MO.isReg() && Register::isVirtualRegister(MO.getReg()))
141 DefInstr = MRI->getUniqueVRegDef(MO.getReg());
171 if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
178 InstrIdxForVirtReg.find(MO.getReg());
186 int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg());
187 int UseIdx = InstrPtr->findRegisterUseOperandIdx(MO.getReg());
195 DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()),
196 InstrPtr, InstrPtr->findRegisterUseOperandIdx(MO.getReg()));
226 if (!(MO.isReg() && Register::isVirtualRegister(MO.getReg())))
231 MachineRegisterInfo::reg_iterator RI = MRI->reg_begin(MO.getReg());
239 NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), UseMO,
240 UseMO->findRegisterUseOperandIdx(MO.getReg()));
lib/CodeGen/MachineCopyPropagation.cpp 111 markRegsUnavailable({MI->getOperand(0).getReg()}, TRI);
122 Register Def = MI->getOperand(0).getReg();
123 Register Src = MI->getOperand(1).getReg();
161 !TRI.isSubRegisterEq(AvailCopy->getOperand(0).getReg(), Reg))
166 Register AvailSrc = AvailCopy->getOperand(1).getReg();
167 Register AvailDef = AvailCopy->getOperand(0).getReg();
265 Register PreviousSrc = PreviousCopy.getOperand(1).getReg();
266 Register PreviousDef = PreviousCopy.getOperand(0).getReg();
303 Register CopyDef = Copy.getOperand(0).getReg();
322 Register CopySrcReg = Copy.getOperand(1).getReg();
350 TRI->getMinimalPhysRegClass(UseI.getOperand(0).getReg());
373 MIUse.isUse() && TRI->regsOverlap(Use.getReg(), MIUse.getReg()))
373 MIUse.isUse() && TRI->regsOverlap(Use.getReg(), MIUse.getReg()))
400 if (!MOUse.getReg())
409 MachineInstr *Copy = Tracker.findAvailCopy(MI, MOUse.getReg(), *TRI);
413 Register CopyDstReg = Copy->getOperand(0).getReg();
415 Register CopySrcReg = CopySrc.getReg();
418 if (MOUse.getReg() != CopyDstReg) {
441 LLVM_DEBUG(dbgs() << "MCP: Replacing " << printReg(MOUse.getReg(), TRI)
469 if (MI->isCopy() && !TRI->regsOverlap(MI->getOperand(0).getReg(),
470 MI->getOperand(1).getReg())) {
471 Register Def = MI->getOperand(0).getReg();
472 Register Src = MI->getOperand(1).getReg();
499 Src = MI->getOperand(1).getReg();
507 Register Reg = MO.getReg();
530 Register Reg = MO.getReg();
544 Register Reg = MO.getReg();
563 Register Reg = MO.getReg();
586 Register Reg = MaybeDead->getOperand(0).getReg();
622 assert(!MRI->isReserved(MaybeDead->getOperand(0).getReg()));
626 unsigned SrcReg = MaybeDead->getOperand(1).getReg();
lib/CodeGen/MachineInstr.cpp 630 if (!Register::isVirtualRegister(MO.getReg()) ||
631 !Register::isVirtualRegister(OMO.getReg()))
686 Register Reg = MO.getReg();
893 if (!MO.isReg() || MO.getReg() != Reg)
934 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == Reg)
949 Register MOReg = MO.getReg();
971 if (!MO.isReg() || MO.getReg() != Reg)
1003 Register MOReg = MO.getReg();
1146 if (!MO.isReg() || MO.getReg() != FromReg)
1152 if (!MO.isReg() || MO.getReg() != FromReg)
1361 Register Reg = getOperand(1).getReg();
1363 if (getOperand(i).getReg() != Reg)
1430 return MRI.getType(Op.getReg());
1434 return MRI.getType(Op.getReg());
1439 LLT TypeToPrint = MRI.getType(Op.getReg());
1803 Register Reg = MO.getReg();
1857 Register OpReg = MO.getReg();
1875 Register MOReg = MO.getReg();
1918 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
1926 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg || MO.getSubReg() == 0)
1940 if (MO.isReg() && MO.getReg() == Reg && MO.isDef() &&
1959 Register Reg = MO.getReg();
1983 if (MO.isReg() && MO.isDef() && Register::isVirtualRegister(MO.getReg()))
2038 return BuildMI(MF, DL, MCID, IsIndirect, MO.getReg(), Variable, Expr);
2116 DI->getOperand(0).getReg() == MI.getOperand(0).getReg())
2116 DI->getOperand(0).getReg() == MI.getOperand(0).getReg())
2128 unsigned DefReg = getOperand(0).getReg();
2135 DI->getOperand(0).getReg() == DefReg){
lib/CodeGen/MachineInstrBundle.cpp 157 Register Reg = MO.getReg();
180 Register Reg = MO.getReg();
290 if (!MO.isReg() || MO.getReg() != Reg)
332 Register MOReg = MO.getReg();
lib/CodeGen/MachineLICM.cpp 426 Register Reg = MO.getReg();
528 Register Reg = MO.getReg();
554 if (!MO.isReg() || MO.isDef() || !MO.getReg())
556 Register Reg = MO.getReg();
579 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue;
580 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
580 if (MO.getReg() == Reg || TRI->isSuperRegister(Reg, MO.getReg()))
769 if (!MO.isDef() || !MO.isReg() || !MO.getReg())
771 if (!MRI->hasOneDef(MO.getReg()))
775 for (MachineInstr &MI : MRI->use_instructions(MO.getReg())) {
801 return MO.isKill() || MRI->hasOneNonDBGUse(MO.getReg());
854 Register Reg = MO.getReg();
924 Register Reg = MO.getReg();
928 Reg = TRI->lookThruCopyLike(MO.getReg(), MRI);
957 Register CopySrcReg = MI.getOperand(1).getReg();
964 Register CopyDstReg = MI.getOperand(0).getReg();
1012 Register Reg = MO.getReg();
1063 Register Reg = MO.getReg();
1106 Register MOReg = MO.getReg();
1134 Register Reg = DefMO.getReg();
1227 Register Reg = MO.getReg();
1379 assert((!MO.isReg() || MO.getReg() == 0 ||
1380 !Register::isPhysicalRegister(MO.getReg()) ||
1381 MO.getReg() == Dup->getOperand(i).getReg()) &&
1381 MO.getReg() == Dup->getOperand(i).getReg()) &&
1385 !Register::isPhysicalRegister(MO.getReg()))
1392 Register Reg = MI->getOperand(Idx).getReg();
1393 Register DupReg = Dup->getOperand(Idx).getReg();
1399 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]);
1405 Register Reg = MI->getOperand(Idx).getReg();
1406 Register DupReg = Dup->getOperand(Idx).getReg();
1487 MRI->clearKillFlags(MO.getReg());
lib/CodeGen/MachineLoopUtils.cpp 51 Register OrigR = MO.getReg();
67 MRI.constrainRegClass(R, MRI.getRegClass(Use->getReg()));
76 if (MO.isReg() && Remaps.count(MO.getReg()))
77 MO.setReg(Remaps[MO.getReg()]);
89 Register R = MI.getOperand(LoopRegIdx).getReg();
98 Register LoopReg = OrigPhi.getOperand(LoopRegIdx).getReg();
lib/CodeGen/MachineOperand.cpp 53 if (getReg() == Reg)
117 assert(Register::isPhysicalRegister(getReg()) &&
135 assert(Register::isPhysicalRegister(getReg()) &&
281 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
281 return getReg() == Other.getReg() && isDef() == Other.isDef() &&
347 return hash_combine(MO.getType(), (unsigned)MO.getReg(), MO.getSubReg(), MO.isDef());
751 Register Reg = getReg();
767 if (Register::isPhysicalRegister(getReg()) && isRenamable())
lib/CodeGen/MachineOutliner.cpp 1255 MOP.getReg(), true, /* isDef = true */
lib/CodeGen/MachinePipeliner.cpp 355 auto *RC = MRI.getRegClass(DefOp.getReg());
369 .addReg(RegOp.getReg(), getRegState(RegOp),
589 InitVal = Phi.getOperand(i).getReg();
591 LoopVal = Phi.getOperand(i).getReg();
600 return Phi.getOperand(i).getReg();
772 Register Reg = MOI->getReg();
824 if (PMI->getOperand(0).getReg() == HasPhiUse)
851 Register OrigBase = I.getInstr()->getOperand(BasePos).getReg();
1556 Register Reg = MO.getReg();
1567 Register Reg = MO.getReg();
2066 Register BaseReg = BaseOp->getReg();
2104 Register BaseReg = MI->getOperand(BasePosLd).getReg();
2159 Register BaseReg = MI->getOperand(BasePos).getReg();
2194 Def = MRI.getVRegDef(Def->getOperand(i).getReg());
2248 MachineInstr *Def = MRI.getVRegDef(BaseOpS->getReg());
2474 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
2477 Register Reg = MO.getReg();
2480 if (MI->getOperand(BasePos).getReg() == Reg)
2622 MachineInstr *Phi = MRI.getVRegDef(MO.getReg());
2632 if (DMO.getReg() == LoopReg)
2769 if (MO.isReg() && MO.isUse() && MO.getReg() == OverlapReg) {
2797 OverlapReg = MI->getOperand(TiedUseIdx).getReg();
2799 NewBaseReg = MI->getOperand(i).getReg();
lib/CodeGen/MachineRegisterInfo.cpp 244 if (MO->getReg() != Reg) {
267 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
281 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
281 assert(MO->getReg() == Head->getReg() && "Different regs on the same list!");
286 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
286 assert(MO->getReg() == Last->getReg() && "Different regs on the same list!");
306 MachineOperand *&HeadRef = getRegUseDefListHead(MO->getReg());
352 MachineOperand *&Head = getRegUseDefListHead(Src->getReg());
lib/CodeGen/MachineSSAUpdater.cpp 98 Register SrcReg = I->getOperand(i).getReg();
106 return I->getOperand(0).getReg();
155 return NewDef->getOperand(0).getReg();
207 return InsertedPHI->getOperand(0).getReg();
267 unsigned getIncomingValue() { return PHI->getOperand(idx).getReg(); }
298 return NewDef->getOperand(0).getReg();
309 return PHI->getOperand(0).getReg();
344 return PHI->getOperand(0).getReg();
lib/CodeGen/MachineScheduler.cpp 938 Register Reg = MO.getReg();
946 if (MO2.isReg() && MO2.isDef() && MO2.getReg() == Reg && !MO2.isDead()) {
1482 return std::make_tuple(BaseOp->getReg(), Offset, SU->NodeNum) <
1483 std::make_tuple(RHS.BaseOp->getReg(), RHS.Offset,
1692 Register SrcReg = SrcOp.getReg();
1697 Register DstReg = DstOp.getReg();
2919 if (Register::isPhysicalRegister(MI->getOperand(ScheduledOper).getReg()))
2924 if (Register::isPhysicalRegister(MI->getOperand(UnscheduledOper).getReg()))
2934 if (Op.isReg() && !Register::isPhysicalRegister(Op.getReg())) {
lib/CodeGen/MachineSink.cpp 206 Register SrcReg = MI.getOperand(1).getReg();
207 Register DstReg = MI.getOperand(0).getReg();
411 if (!MO.isReg() || !MO.getReg().isVirtual())
414 SeenDbgUsers[MO.getReg()].push_back(&MI);
442 Register Reg = MO.getReg();
641 Register Reg = MO.getReg();
758 MBP.LHS.getReg() == BaseOp->getReg();
758 MBP.LHS.getReg() == BaseOp->getReg();
810 if (DbgMO.getReg().isVirtual() != SrcMO->getReg().isVirtual())
810 if (DbgMO.getReg().isVirtual() != SrcMO->getReg().isVirtual())
815 bool arePhysRegs = !DbgMO.getReg().isVirtual();
828 if (PostRA && DbgMO.getReg() != DstMO->getReg())
828 if (PostRA && DbgMO.getReg() != DstMO->getReg())
831 DbgMI->getOperand(0).setReg(SrcMO->getReg());
881 Register Reg = MO.getReg();
953 if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual())
955 if (!SeenDbgUsers.count(MO.getReg()))
958 auto &Users = SeenDbgUsers[MO.getReg()];
977 RegsToClearKillFlags.set(MO.getReg()); // Remember to clear kill flags.
994 if (!MO.isReg() || !MO.isDef() || !MO.getReg().isVirtual())
996 for (auto &User : MRI.use_instructions(MO.getReg())) {
1013 User->getOperand(0).setReg(MI.getOperand(1).getReg());
1149 Register SrcReg = MO.getReg();
1172 Register Reg = MI->getOperand(U).getReg();
1188 Register Reg = MO.getReg();
1257 if (MO.isReg() && Register::isPhysicalRegister(MO.getReg())) {
1265 SmallSet<unsigned, 4> Units = getRegUnits(MO.getReg(), TRI);
1315 SmallSet<unsigned, 4> Units = getRegUnits(MO.getReg(), TRI);
lib/CodeGen/MachineTraceMetrics.cpp 663 Register Reg = MO.getReg();
690 Register Reg = UseMI.getOperand(i).getReg();
711 Register Reg = MO.getReg();
742 for (MCRegUnitIterator Units(UseMI->getOperand(DefOp).getReg(), TRI);
905 Register Reg = MO.getReg();
933 Register Reg = MI.getOperand(ReadOps[i]).getReg();
981 unsigned Reg = DefMI->getOperand(DefOp).getReg();
lib/CodeGen/MachineVerifier.cpp 941 LLT OpTy = MRI->getType(MO->getReg());
960 if (MO->isReg() && Register::isPhysicalRegister(MO->getReg()))
979 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1011 LLT ValTy = MRI->getType(MI->getOperand(0).getReg());
1012 LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1039 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1045 LLT Ty = MRI->getType(MO.getReg());
1056 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1057 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1071 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1072 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1104 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1105 LLT PtrTy = MRI->getType(MI->getOperand(1).getReg());
1106 LLT OffsetTy = MRI->getType(MI->getOperand(2).getReg());
1131 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1132 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1160 LLT SelTy = MRI->getType(MI->getOperand(0).getReg());
1161 LLT CondTy = MRI->getType(MI->getOperand(1).getReg());
1175 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1176 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1185 if (MRI->getType(MI->getOperand(I).getReg()) != SrcTy)
1192 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1193 LLT SrcTy = MRI->getType(MI->getOperand(MI->getNumOperands()-1).getReg());
1196 if (MRI->getType(MI->getOperand(i).getReg()) != DstTy)
1209 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1210 LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1223 if (MRI->getType(MI->getOperand(1).getReg()) !=
1224 MRI->getType(MI->getOperand(i).getReg()))
1233 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1234 LLT SrcEltTy = MRI->getType(MI->getOperand(1).getReg());
1239 if (MRI->getType(MI->getOperand(1).getReg()) !=
1240 MRI->getType(MI->getOperand(i).getReg()))
1253 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1254 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1259 if (MRI->getType(MI->getOperand(1).getReg()) !=
1260 MRI->getType(MI->getOperand(i).getReg()))
1270 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1271 LLT SrcTy = MRI->getType(MI->getOperand(2).getReg());
1292 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1293 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1314 unsigned DstSize = MRI->getType(MI->getOperand(0).getReg()).getSizeInBits();
1315 unsigned SrcSize = MRI->getType(SrcOp.getReg()).getSizeInBits();
1328 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1334 if (!MRI->getType(MI->getOperand(0).getReg()).isPointer())
1341 if (!IdxOp.isReg() || MRI->getType(IdxOp.getReg()).isPointer())
1393 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1394 LLT SrcTy = MRI->getType(MI->getOperand(1).getReg());
1423 LLT DstTy = MRI->getType(MI->getOperand(0).getReg());
1424 LLT Src0Ty = MRI->getType(MI->getOperand(1).getReg());
1425 LLT Src1Ty = MRI->getType(MI->getOperand(2).getReg());
1459 if (!DstOp.isReg() || !MRI->getType(DstOp.getReg()).isPointer()) {
1464 if (!AllocOp.isReg() || !MRI->getType(AllocOp.getReg()).isScalar()) {
1544 LLT DstTy = MRI->getType(DstOp.getReg());
1545 LLT SrcTy = MRI->getType(SrcOp.getReg());
1556 unsigned SrcSize = TRI->getRegSizeInBits(SrcOp.getReg(), *MRI);
1557 unsigned DstSize = TRI->getRegSizeInBits(DstOp.getReg(), *MRI);
1629 else if (Register::isPhysicalRegister(MO->getReg())) {
1633 else if (Register::isPhysicalRegister(MOTied.getReg()) &&
1634 MO->getReg() != MOTied.getReg())
1634 MO->getReg() != MOTied.getReg())
1641 if (MO->isReg() && !MO->isImplicit() && !MI->isVariadic() && MO->getReg())
1647 const Register Reg = MO->getReg();
1679 Reg != MI->getOperand(DefIdx).getReg())
1941 const unsigned Reg = MO->getReg();
2025 if (!Register::isPhysicalRegister(MOP.getReg()))
2028 for (MCSubRegIterator SubRegs(MOP.getReg(), TRI); SubRegs.isValid();
2222 Register DefReg = MODef.getReg();
2252 !PrInfo.isLiveOut(MO0.getReg()))
2419 if (MOI->getReg() != Reg)
2422 if (!Register::isPhysicalRegister(MOI->getReg()) ||
2423 !TRI->hasRegUnit(MOI->getReg(), Reg))
2556 if (!MOI->isReg() || MOI->getReg() != Reg)
lib/CodeGen/ModuloSchedule.cpp 43 InitVal = Phi.getOperand(i).getReg();
45 LoopVal = Phi.getOperand(i).getReg();
54 return Phi.getOperand(i).getReg();
62 return Phi.getOperand(i).getReg();
81 Register Reg = Op.getReg();
385 Register Def = BBI->getOperand(0).getReg();
626 !Register::isVirtualRegister(MO.getReg()))
631 Register Def = MO.getReg();
729 Register reg = MOI->getReg();
767 Register reg = MI->getOperand(0).getReg();
789 Register Def = PHI.getOperand(0).getReg();
921 Register BaseReg = BaseOp->getReg();
1027 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
1029 Register reg = MO.getReg();
1066 Def = MRI.getVRegDef(Def->getOperand(i).getReg());
1114 Register PhiDef = PHI.getOperand(0).getReg();
1152 if (!Phi->isPHI() && UseMI->getOperand(0).getReg() == NewReg)
1224 if (MRI.use_empty(MI.getOperand(0).getReg())) {
1230 MRI.constrainRegClass(MI.getOperand(1).getReg(),
1231 MRI.getRegClass(MI.getOperand(0).getReg()));
1232 MRI.replaceRegWith(MI.getOperand(0).getReg(),
1233 MI.getOperand(1).getReg());
1320 if (!MO.isReg() || MO.getReg().isPhysical() || MO.isImplicit())
1322 Register Reg = remapUse(MO.getReg(), MI);
1334 Register R = MI->getOperand(0).getReg();
1340 for (MachineInstr &MI : MRI.use_instructions(Def.getReg())) {
1342 phi(Def.getReg());
1530 MachineInstr *MI = MRI.getVRegDef(MO->getReg());
1562 return MO->isReg() && MO->getReg().isVirtual() &&
1563 MRI.getVRegDef(MO->getReg())->getParent() == BB;
1639 Register Reg = MI.getOperand(1).getReg();
1679 auto RC = MRI.getRegClass(MI.getOperand(0).getReg());
1680 Register OldR = MI.getOperand(3).getReg();
1716 return BlockMIs[{BB, CanonicalMIs[MI]}]->getOperand(OpIdx).getReg();
1723 Register PhiR = MI->getOperand(0).getReg();
1724 Register R = MI->getOperand(3).getReg();
1727 R = MI->getOperand(1).getReg();
1744 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) {
1748 Register Reg = getEquivalentRegisterIn(UseMI.getOperand(0).getReg(),
1753 Sub.first->substituteRegister(DefMO.getReg(), Sub.second, /*SubIdx=*/0,
lib/CodeGen/OptimizePHIs.cpp 100 Register DstReg = MI->getOperand(0).getReg();
112 Register SrcReg = MI->getOperand(i).getReg();
120 Register::isVirtualRegister(SrcMI->getOperand(1).getReg())) {
121 SrcReg = SrcMI->getOperand(1).getReg();
144 Register DstReg = MI->getOperand(0).getReg();
179 Register OldReg = MI->getOperand(0).getReg();
lib/CodeGen/PHIElimination.cpp 173 Register DefReg = DefMI->getOperand(0).getReg();
234 if (!isImplicitlyDefined(MO.getReg(), MRI) && !MO.isUndef())
250 Register DestReg = MPhi->getOperand(0).getReg();
370 MPhi->getOperand(i).getReg())];
376 Register SrcReg = MPhi->getOperand(i * 2 + 1).getReg();
558 BBI.getOperand(i).getReg())];
575 Register Reg = BBI->getOperand(i).getReg();
lib/CodeGen/PeepholeOptimizer.cpp 845 Src = RegSubRegPair(MOSrc.getReg(), MOSrc.getSubReg());
848 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
891 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
928 Src = RegSubRegPair(MOInsertedReg.getReg(), MOInsertedReg.getSubReg());
936 Dst = RegSubRegPair(MODef.getReg(),
979 Src = RegSubRegPair(MOExtractedReg.getReg(),
984 Dst = RegSubRegPair(MODef.getReg(), MODef.getSubReg());
1051 Src.Reg = MOInsertedReg.getReg();
1061 Dst.Reg = MODef.getReg();
1150 return RegSubRegPair(MODef.getReg(), MODef.getSubReg());
1173 if (Register::isPhysicalRegister(MODef.getReg()))
1318 Register Reg = MI.getOperand(0).getReg();
1338 Register Reg = MI.getOperand(0).getReg();
1361 Register Reg = MO.getReg();
1395 Register SrcReg = MI.getOperand(1).getReg();
1399 Register DstReg = MI.getOperand(0).getReg();
1418 Register PrevDstReg = PrevCopy->getOperand(0).getReg();
1445 Register DstReg = MI.getOperand(0).getReg();
1446 Register SrcReg = MI.getOperand(1).getReg();
1468 Register PrevDstReg = PrevCopy->second->getOperand(0).getReg();
1490 return Register::isVirtualRegister(MO.getReg());
1533 return findTargetRecurrence(DefOp.getReg(), TargetRegs, RC);
1539 return findTargetRecurrence(DefOp.getReg(), TargetRegs, RC);
1569 TargetRegs.insert(MO.getReg());
1574 if (findTargetRecurrence(PHI.getOperand(0).getReg(), TargetRegs, RC)) {
1663 Register Reg = MO.getReg();
1761 unsigned FoldAsLoadDefReg = MOp.getReg();
1825 return ValueTrackerResult(Src.getReg(), Src.getSubReg());
1848 if (!MO.isReg() || !MO.getReg())
1867 for (const MachineInstr &UseMI : MRI.use_nodbg_instructions(DefOp.getReg())) {
1875 return ValueTrackerResult(Src.getReg(), Src.getSubReg());
1959 if (MRI.getRegClass(MODef.getReg()) != MRI.getRegClass(BaseReg.Reg) ||
2020 return ValueTrackerResult(Def->getOperand(2).getReg(),
2042 Res.addSource(MO.getReg(), MO.getSubReg());
lib/CodeGen/ProcessImplicitDefs.cpp 76 Register Reg = MI->getOperand(0).getReg();
103 Register UserReg = MO.getReg();
lib/CodeGen/ReachingDefAnalysis.cpp 106 if (!MO.isReg() || !MO.getReg())
110 for (MCRegUnitIterator Unit(MO.getReg(), TRI); Unit.isValid(); ++Unit) {
112 LLVM_DEBUG(dbgs() << printReg(MO.getReg(), TRI) << ":\t" << CurInstr
lib/CodeGen/RegAllocFast.cpp 357 if (StackSlotForVirtReg[MO.getReg()] != -1)
361 MachineRegisterInfo::reg_nodbg_iterator I = MRI->reg_nodbg_begin(MO.getReg());
372 if (MO.getReg() == LR.PhysReg)
458 Register PhysReg = MO.getReg();
635 Reg = VRegDef->getOperand(1).getReg();
648 Register Reg = MI.getOperand(1).getReg();
753 Register VirtReg = MO.getReg();
790 Hint = UseMI.getOperand(0).getReg();
892 Register Reg = MO.getReg();
907 Register Reg = MO.getReg();
922 Register Reg = MO.getReg();
948 Register Reg = MO.getReg();
963 Register Reg = MO.getReg();
1021 CopyDstReg = MI.getOperand(0).getReg();
1022 CopySrcReg = MI.getOperand(1).getReg();
1046 Register Reg = MO.getReg();
1097 Register Reg = MO.getReg();
1126 Register Reg = MO.getReg();
1141 Register Reg = MO.getReg();
1167 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
1169 Register Reg = MO.getReg();
1180 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber())
1182 Register Reg = MO.getReg();
1217 Register Reg = MO.getReg();
lib/CodeGen/RegAllocGreedy.cpp 2877 Register OtherReg = Instr.getOperand(0).getReg();
2879 OtherReg = Instr.getOperand(1).getReg();
lib/CodeGen/RegisterCoalescer.cpp 366 Dst = MI->getOperand(0).getReg();
368 Src = MI->getOperand(1).getReg();
371 Dst = MI->getOperand(0).getReg();
374 Src = MI->getOperand(2).getReg();
805 Register NewReg = NewDstMO.getReg();
888 if (UseMI->getOperand(0).getReg() != IntB.reg ||
1066 if (DefMI->getOperand(0).getReg() != IntA.reg ||
1067 DefMI->getOperand(1).getReg() != IntB.reg ||
1194 if (!Op.isReg() || !Op.isDef() || Op.getReg() != Reg)
1243 Register CopyDstReg = DstOperand.getReg();
1320 if (Register::isPhysicalRegister(MO.getReg()))
1339 Register::isPhysicalRegister(MO.getReg()));
1340 NewMIImplDefs.push_back(MO.getReg());
1428 } else if (NewMI.getOperand(0).getReg() != CopyDstReg) {
1453 for (MCRegUnitIterator Units(NewMI.getOperand(0).getReg(), TRI);
1618 if (MO.isReg() && MO.isDef() && MO.getReg() == DstReg)
2394 if (!MO.isReg() || MO.getReg() != Reg || !MO.isDef())
2414 Register SrcReg = MI->getOperand(1).getReg();
2828 if (!MO.isReg() || MO.isDef() || MO.getReg() != Reg)
2944 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg) {
3192 Register Reg = MI->getOperand(1).getReg();
3466 Register SrcReg = Copy->getOperand(1).getReg();
3467 Register DstReg = Copy->getOperand(0).getReg();
lib/CodeGen/RegisterPressure.cpp 500 if (!MO.isReg() || !MO.getReg())
502 Register Reg = MO.getReg();
531 if (!MO.isReg() || !MO.getReg())
533 Register Reg = MO.getReg();
lib/CodeGen/RegisterScavenging.cpp 136 Register Reg = MO.getReg();
207 Register Reg = MO.getReg();
330 if (!MO.isReg() || MO.isUndef() || !MO.getReg())
332 if (Register::isVirtualRegister(MO.getReg())) {
339 for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
433 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
544 if (MO.isReg() && MO.getReg() != 0 && !(MO.isUse() && MO.isUndef()) &&
545 !Register::isVirtualRegister(MO.getReg()))
546 for (MCRegAliasIterator AI(MO.getReg(), TRI, true); AI.isValid(); ++AI)
697 Register Reg = MO.getReg();
719 Register Reg = MO.getReg();
740 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
lib/CodeGen/ScheduleDAGInstrs.cpp 207 Register Reg = MO.getReg();
240 !DefMIDesc->hasImplicitDefOfPhysReg(MO.getReg()));
241 for (MCRegAliasIterator Alias(MO.getReg(), TRI, true);
287 Register Reg = MO.getReg();
363 Register Reg = MO.getReg();
376 auto RegUse = CurrentVRegUses.find(MO.getReg());
391 Register Reg = MO.getReg();
409 if (OtherMO.isReg() && OtherMO.isDef() && OtherMO.getReg() == Reg)
511 Register Reg = MO.getReg();
841 Register Reg = MO.getReg();
858 Register Reg = MO.getReg();
1091 Register Reg = MO.getReg();
1122 Register Reg = MO.getReg();
lib/CodeGen/SelectionDAG/FastISel.cpp 176 RegDef = MO.getReg();
177 } else if (Register::isVirtualRegister(MO.getReg())) {
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 574 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg();
628 CopyUseMI->getOperand(0).getReg(), Variable, Expr);
1654 if (!OPI2->isReg() || (!Register::isPhysicalRegister(OPI->getReg()) &&
1655 Register::isPhysicalRegister(OPI2->getReg())))
lib/CodeGen/ShrinkWrap.cpp 281 Register PhysReg = MO.getReg();
lib/CodeGen/SplitKit.cpp 440 Register R = DefOp.getReg();
1376 Register Reg = EP.MO.getReg(), Sub = EP.MO.getSubReg();
lib/CodeGen/StackMaps.cpp 116 Register Reg = (++MOI)->getReg();
125 Register Reg = (++MOI)->getReg();
151 assert(Register::isPhysicalRegister(MOI->getReg()) &&
153 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(MOI->getReg());
157 unsigned DwarfRegNum = getDwarfRegNum(MOI->getReg(), TRI);
159 unsigned SubRegIdx = TRI->getSubRegIndex(LLVMRegNum, MOI->getReg());
lib/CodeGen/TailDuplicator.cpp 238 Register Dst = Copy->getOperand(0).getReg();
239 Register Src = Copy->getOperand(1).getReg();
315 Register SrcReg = MI.getOperand(i).getReg();
343 Register DefReg = MI->getOperand(0).getReg();
346 Register SrcReg = MI->getOperand(SrcOpIdx).getReg();
387 Register Reg = MO.getReg();
480 Register Reg = MO0.getReg();
lib/CodeGen/TargetInstrInfo.cpp 173 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
174 Register Reg1 = MI.getOperand(Idx1).getReg();
175 Register Reg2 = MI.getOperand(Idx2).getReg();
335 MO.setReg(Pred[j].getReg());
414 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
446 Register FoldReg = FoldOp.getReg();
447 Register LiveReg = LiveOp.getReg();
454 if (Register::isPhysicalRegister(LiveOp.getReg()))
455 return RC->contains(LiveOp.getReg()) ? RC : nullptr;
515 MF.getRegInfo().getRegClass(MO.getReg());
613 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
615 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
677 if (Op1.isReg() && Register::isVirtualRegister(Op1.getReg()))
678 MI1 = MRI.getUniqueVRegDef(Op1.getReg());
679 if (Op2.isReg() && Register::isVirtualRegister(Op2.getReg()))
680 MI2 = MRI.getUniqueVRegDef(Op2.getReg());
690 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg());
691 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg());
706 MRI.hasOneNonDBGUse(MI1->getOperand(0).getReg());
808 Register RegA = OpA.getReg();
809 Register RegB = OpB.getReg();
810 Register RegX = OpX.getReg();
811 Register RegY = OpY.getReg();
812 Register RegC = OpC.getReg();
867 Prev = MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
871 Prev = MRI.getUniqueVRegDef(Root.getOperand(2).getReg());
890 Register DefReg = MI.getOperand(0).getReg();
927 Register Reg = MO.getReg();
1187 InputRegs.push_back(RegSubRegPairAndIdx(MOReg.getReg(), MOReg.getSubReg(),
1212 InputReg.Reg = MOReg.getReg();
1237 BaseReg.Reg = MOBaseReg.getReg();
1240 InsertedReg.Reg = MOInsertedReg.getReg();
lib/CodeGen/TargetRegisterInfo.cpp 504 CopySrcReg = MI->getOperand(1).getReg();
507 CopySrcReg = MI->getOperand(2).getReg();
lib/CodeGen/TargetSchedule.cpp 303 Register Reg = DefMI->getOperand(DefOperIdx).getReg();
lib/CodeGen/TwoAddressInstructionPass.cpp 233 Register MOReg = MO.getReg();
237 UseRegs.insert(MO.getReg());
246 DefReg = MO.getReg();
302 Register MOReg = MO.getReg();
372 TmpReg = Def->getOperand(1).getReg();
413 DstReg = MI.getOperand(0).getReg();
414 SrcReg = MI.getOperand(1).getReg();
416 DstReg = MI.getOperand(0).getReg();
417 SrcReg = MI.getOperand(2).getReg();
505 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
509 DstReg = MI.getOperand(ti).getReg();
685 Register RegC = MI->getOperand(RegCIdx).getReg();
702 Register RegA = MI->getOperand(DstIdx).getReg();
913 Register MOReg = MO.getReg();
932 if (End->isCopy() && regOverlapsSet(Defs, End->getOperand(1).getReg(), TRI))
933 Defs.push_back(End->getOperand(0).getReg());
957 Register MOReg = MO.getReg();
1095 Register MOReg = MO.getReg();
1132 Register MOReg = MO.getReg();
1209 Register DstOpReg = MI->getOperand(DstOpIdx).getReg();
1210 Register BaseOpReg = MI->getOperand(BaseOpIdx).getReg();
1222 Register OtherOpReg = MI->getOperand(OtherOpIdx).getReg();
1277 Register regA = MI.getOperand(DstIdx).getReg();
1278 Register regB = MI.getOperand(SrcIdx).getReg();
1313 regB = MI.getOperand(SrcIdx).getReg();
1400 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
1403 if (NewMIs[0]->killsRegister(MO.getReg()))
1404 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[0]);
1406 assert(NewMIs[1]->killsRegister(MO.getReg()) &&
1408 LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[1]);
1411 } else if (LV->removeVirtualRegisterDead(MO.getReg(), MI)) {
1412 if (NewMIs[1]->registerDefIsDead(MO.getReg()))
1413 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[1]);
1415 assert(NewMIs[0]->registerDefIsDead(MO.getReg()) &&
1417 LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[0]);
1429 OrigRegs.push_back(MO.getReg());
1474 Register SrcReg = SrcMO.getReg();
1475 Register DstReg = DstMO.getReg();
1522 Register RegA = DstMO.getReg();
1526 RegB = MI->getOperand(SrcIdx).getReg();
1548 MI->getOperand(i).getReg() != RegA);
1592 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() &&
1617 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1657 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) {
1742 Register SrcReg = mi->getOperand(SrcIdx).getReg();
1743 Register DstReg = mi->getOperand(DstIdx).getReg();
1801 Register DstReg = MI.getOperand(0).getReg();
1810 OrigRegs.push_back(MI.getOperand(0).getReg());
1812 OrigRegs.push_back(MI.getOperand(i).getReg());
1818 Register SrcReg = UseMO.getReg();
1829 if (MI.getOperand(j).getReg() == SrcReg) {
lib/CodeGen/UnreachableBlockElim.cpp 177 Register InputReg = Input.getReg();
178 Register OutputReg = Output.getReg();
lib/CodeGen/VirtRegMap.cpp 355 Register Reg = MO.getReg();
425 if (TRI->regsOverlap(Dst->getOperand(0).getReg(),
426 Src->getOperand(1).getReg()))
515 if (!MO.isReg() || !MO.getReg().isVirtual())
517 Register VirtReg = MO.getReg();
lib/Target/AArch64/AArch64A53Fix835769.cpp 69 return MI->getOperand(3).getReg() != AArch64::XZR;
lib/Target/AArch64/AArch64A57FPLoadBalancing.cpp 554 if (U.isReg() && U.isUse() && Substs.find(U.getReg()) != Substs.end()) {
555 Register OrigReg = U.getReg();
576 bool Change = TransformAll || getColor(MO.getReg()) != C;
581 Substs[MO.getReg()] = Reg;
614 Register DestReg = MI->getOperand(0).getReg();
627 Register DestReg = MI->getOperand(0).getReg();
628 Register AccumReg = MI->getOperand(3).getReg();
690 if (MO.isKill() && ActiveChains.find(MO.getReg()) != ActiveChains.end()) {
691 LLVM_DEBUG(dbgs() << "Kill seen for chain " << printReg(MO.getReg(), TRI)
693 ActiveChains[MO.getReg()]->setKill(MI, Idx, /*Immutable=*/MO.isTied());
695 ActiveChains.erase(MO.getReg());
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 144 if (isFPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
146 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
148 if (isGPR64(MI->getOperand(0).getReg(), MI->getOperand(0).getSubReg(),
150 isFPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(),
204 Register OrigSrc0 = MI.getOperand(1).getReg();
205 Register OrigSrc1 = MI.getOperand(2).getReg();
239 Register Dst = MI.getOperand(0).getReg();
296 Register OrigSrc0 = MI.getOperand(1).getReg();
297 Register OrigSrc1 = MI.getOperand(2).getReg();
309 Src0 = MOSrc0->getReg();
328 Src1 = MOSrc1->getReg();
369 insertCopy(TII, MI, MI.getOperand(0).getReg(), Dst, true);
lib/Target/AArch64/AArch64AsmPrinter.cpp 240 Register Reg = MI.getOperand(0).getReg();
505 Register Reg = MO.getReg();
529 Register Reg = MO.getReg();
553 Register Reg = MO.getReg();
627 Register Reg = MO.getReg();
662 O << "[" << AArch64InstPrinter::getRegisterName(MO.getReg()) << "]";
757 Register DestReg = MI.getOperand(0).getReg();
758 Register ScratchReg = MI.getOperand(1).getReg();
761 Register TableReg = MI.getOperand(2).getReg();
762 Register EntryReg = MI.getOperand(3).getReg();
832 Register ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
862 Register DestReg = MI.getOperand(0).getReg();
926 Register DestReg = MI->getOperand(0).getReg();
960 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
998 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1069 unsigned DestReg = MI->getOperand(0).getReg(),
1070 ScratchReg = MI->getOperand(1).getReg(),
1071 TableReg = MI->getOperand(2).getReg(),
1072 EntryReg = MI->getOperand(3).getReg();
lib/Target/AArch64/AArch64CallLowering.cpp 182 .getReg();
649 Register CopyRHS = RegDef->getOperand(1).getReg();
883 return TRI->regsOverlap(Use.getReg(), ForwardedReg);
lib/Target/AArch64/AArch64CollectLOH.cpp 216 MI.getOperand(0).getReg() != MI.getOperand(1).getReg();
216 MI.getOperand(0).getReg() != MI.getOperand(1).getReg();
476 int Idx = mapRegToGPRIndex(MO.getReg());
487 int Idx = mapRegToGPRIndex(MO.getReg());
536 int DefIdx = mapRegToGPRIndex(Def.getReg());
537 int OpIdx = mapRegToGPRIndex(Op.getReg());
545 int Idx = mapRegToGPRIndex(Op0.getReg());
lib/Target/AArch64/AArch64CondBrTuning.cpp 81 if (!Register::isVirtualRegister(MO.getReg()))
83 return MRI->getUniqueVRegDef(MO.getReg());
94 if (MO.isReg() && MO.isDead() && MO.getReg() == AArch64::NZCV)
101 Register NewDestReg = MI.getOperand(0).getReg();
102 if (MRI->hasOneNonDBGUse(MI.getOperand(0).getReg()))
lib/Target/AArch64/AArch64ConditionOptimizer.cpp 181 } else if (!MRI->use_empty(I->getOperand(0).getReg())) {
lib/Target/AArch64/AArch64ConditionalCompares.cpp 223 Register Reg = I.getOperand(oi).getReg();
340 if (isDeadDef(I->getOperand(0).getReg()))
643 MRI->constrainRegClass(HeadCond[2].getReg(),
690 MRI->constrainRegClass(CmpMI->getOperand(FirstOp).getReg(),
693 MRI->constrainRegClass(CmpMI->getOperand(FirstOp + 1).getReg(),
lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp 148 Register Reg = MO.getReg();
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 98 assert(MO.isReg() && MO.getReg());
112 Register DstReg = MI.getOperand(0).getReg();
153 Register DstReg = MI.getOperand(0).getReg();
177 Register StatusReg = MI.getOperand(1).getReg();
182 Register AddrReg = MI.getOperand(2).getReg();
183 Register DesiredReg = MI.getOperand(3).getReg();
184 Register NewReg = MI.getOperand(4).getReg();
203 BuildMI(LoadCmpBB, DL, TII->get(LdarOp), Dest.getReg())
206 .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
257 Register StatusReg = MI.getOperand(2).getReg();
262 Register AddrReg = MI.getOperand(3).getReg();
263 Register DesiredLoReg = MI.getOperand(4).getReg();
264 Register DesiredHiReg = MI.getOperand(5).getReg();
265 Register NewLoReg = MI.getOperand(6).getReg();
266 Register NewHiReg = MI.getOperand(7).getReg();
283 .addReg(DestLo.getReg(), RegState::Define)
284 .addReg(DestHi.getReg(), RegState::Define)
287 .addReg(DestLo.getReg(), getKillRegState(DestLo.isDead()))
295 .addReg(DestHi.getReg(), getKillRegState(DestHi.isDead()))
348 Register SizeReg = MI.getOperand(2).getReg();
349 Register AddressReg = MI.getOperand(3).getReg();
467 MI.getOperand(0).getReg())
478 Register DstReg = MI.getOperand(0).getReg();
513 unsigned DstReg = MI.getOperand(0).getReg();
551 Register DstReg = MI.getOperand(0).getReg();
595 Register DstReg = MI.getOperand(0).getReg();
683 SrcReg = MI.getOperand(0).getReg();
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 645 Register BaseReg = MI.getOperand(BaseRegIdx).getReg();
650 LI.DestReg = DestRegIdx == -1 ? Register() : MI.getOperand(DestRegIdx).getReg();
669 Off = (1 << 5) | TRI->getEncodingValue(LI.OffsetOpnd->getReg());
747 LR.addReg(MO.getReg());
lib/Target/AArch64/AArch64FastISel.cpp 2053 ResultReg = std::prev(I)->getOperand(0).getReg();
2071 Reg = Opnd.getReg();
4545 Register LoadReg = MI->getOperand(1).getReg();
4570 Reg = MI->getOperand(1).getReg();
lib/Target/AArch64/AArch64FrameLowering.cpp 503 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
504 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(2).getReg());
516 Register Reg0 = MBBI->getOperand(1).getReg();
517 Register Reg1 = MBBI->getOperand(2).getReg();
534 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
545 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
554 unsigned Reg0 = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
555 unsigned Reg1 = RegInfo->getSEHRegNum(MBBI->getOperand(1).getReg());
565 Register Reg0 = MBBI->getOperand(0).getReg();
566 Register Reg1 = MBBI->getOperand(1).getReg();
581 int Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
590 unsigned Reg = RegInfo->getSEHRegNum(MBBI->getOperand(0).getReg());
635 assert(MBBI->getOperand(0).getReg() != AArch64::SP);
705 assert(MBBI->getOperand(OpndIdx - 1).getReg() == AArch64::SP &&
739 assert(MI.getOperand(0).getReg() != AArch64::SP);
766 assert(MI.getOperand(OffsetIdx - 1).getReg() == AArch64::SP &&
1547 Prev->getOperand(0).getReg() == AArch64::SP)
lib/Target/AArch64/AArch64ISelLowering.cpp 1342 Register DestReg = MI.getOperand(0).getReg();
1343 Register IfTrueReg = MI.getOperand(1).getReg();
1344 Register IfFalseReg = MI.getOperand(2).getReg();
lib/Target/AArch64/AArch64InstrInfo.cpp 422 VReg = DefMI->getOperand(1).getReg();
461 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
479 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg());
492 *NewVReg = DefMI->getOperand(SrcOpNum).getReg();
576 Register SrcReg = Cond[2].getReg();
610 .addReg(Cond[2].getReg())
615 .addReg(Cond[2].getReg())
701 (MI.getOperand(1).getReg() == AArch64::WZR ||
702 MI.getOperand(1).getReg() == AArch64::XZR))
924 SrcReg = MI.getOperand(1).getReg();
925 DstReg = MI.getOperand(0).getReg();
1011 SrcReg = MI.getOperand(1).getReg();
1012 SrcReg2 = MI.getOperand(2).getReg();
1020 SrcReg = MI.getOperand(1).getReg();
1030 SrcReg = MI.getOperand(1).getReg();
1073 Register Reg = MO.getReg();
1216 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
1501 Register Reg = MI.getOperand(0).getReg();
1589 return MI.getOperand(1).getReg() == AArch64::WZR;
1591 return MI.getOperand(1).getReg() == AArch64::XZR;
1593 return MI.getOperand(1).getReg() == AArch64::WZR;
1606 Register DstReg = MI.getOperand(0).getReg();
1611 if (MI.getOperand(1).getReg() == AArch64::XZR) {
1636 Register DstReg = MI.getOperand(0).getReg();
1641 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
1641 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
1666 return MI.getOperand(0).getReg();
1689 return MI.getOperand(0).getReg();
1942 Register BaseReg = MI.getOperand(1).getReg();
2338 if (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg())
2338 if (BaseOp1.isReg() && BaseOp1.getReg() != BaseOp2.getReg())
3195 Register DstReg = MI.getOperand(0).getReg();
3196 Register SrcReg = MI.getOperand(1).getReg();
3241 Register DstReg = DstMO.getReg();
3242 Register SrcReg = SrcMO.getReg();
3467 MI.getOperand(0).getReg(), FrameReg, Offset, TII,
3600 if (MO.isReg() && Register::isVirtualRegister(MO.getReg()))
3601 MI = MRI.getUniqueVRegDef(MO.getReg());
3606 if (!MRI.hasOneNonDBGUse(MI->getOperand(0).getReg()))
3614 if (MI->getOperand(3).getReg() != ZeroReg)
3992 MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
3993 Register ResultReg = Root.getOperand(0).getReg();
3994 Register SrcReg0 = MUL->getOperand(1).getReg();
3996 Register SrcReg1 = MUL->getOperand(2).getReg();
4006 SrcReg2 = Root.getOperand(IdxOtherOpd).getReg();
4069 MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg());
4070 Register ResultReg = Root.getOperand(0).getReg();
4071 Register SrcReg0 = MUL->getOperand(1).getReg();
4073 Register SrcReg1 = MUL->getOperand(2).getReg();
4786 Register VReg = MI.getOperand(0).getReg();
4794 Register CopyVReg = DefMI->getOperand(1).getReg();
4822 Register NewReg = MO.getReg();
4855 if (!(DefMI->getOperand(1).getReg() == AArch64::WZR &&
4856 DefMI->getOperand(2).getReg() == AArch64::WZR) &&
4857 !(DefMI->getOperand(1).getReg() == AArch64::XZR &&
4858 DefMI->getOperand(2).getReg() == AArch64::XZR))
5140 Base->getReg() != AArch64::SP)
5411 (MOP.getReg() == AArch64::LR || MOP.getReg() == AArch64::W30))
5411 (MOP.getReg() == AArch64::LR || MOP.getReg() == AArch64::W30))
5511 (Base->isReg() && Base->getReg() != AArch64::SP))
5712 MI.getOperand(1).getReg() == AArch64::WZR &&
5720 MI.getOperand(1).getReg() == AArch64::XZR &&
lib/Target/AArch64/AArch64InstructionSelector.cpp 406 LLT Ty = MRI.getType(I.getOperand(0).getReg());
424 if (!Register::isVirtualRegister(MO.getReg())) {
429 const RegisterBank *OpBank = RBI.getRegBank(MO.getReg(), MRI, TRI);
559 const Register DstReg = I.getOperand(0).getReg();
560 const Register SrcReg = I.getOperand(1).getReg();
606 if (!Register::isPhysicalRegister(I.getOperand(0).getReg()))
607 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI);
620 Register DstReg = I.getOperand(0).getReg();
621 Register SrcReg = I.getOperand(1).getReg();
646 Register DstReg = I.getOperand(0).getReg();
647 Register SrcReg = I.getOperand(1).getReg();
675 (!Register::isPhysicalRegister(I.getOperand(0).getReg()) &&
676 !Register::isPhysicalRegister(I.getOperand(1).getReg()))) &&
834 bool IsFP = (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() !=
836 LLT Ty = MRI.getType(I.getOperand(0).getReg());
848 const ConstantFP *FPImm = getConstantFPVRegVal(I.getOperand(3).getReg(), MRI);
850 unsigned OpSize = MRI.getType(I.getOperand(2).getReg()).getSizeInBits();
955 const Register CondReg = I.getOperand(0).getReg();
959 CCMI = MRI.getVRegDef(CCMI->getOperand(1).getReg());
963 Register LHS = CCMI->getOperand(2).getReg();
964 Register RHS = CCMI->getOperand(3).getReg();
1012 Register DstReg = I.getOperand(0).getReg();
1014 Register Src1Reg = I.getOperand(1).getReg();
1015 Register Src2Reg = I.getOperand(2).getReg();
1042 Register DstReg = I.getOperand(0).getReg();
1044 Register Src1Reg = I.getOperand(1).getReg();
1045 Register Src2Reg = I.getOperand(2).getReg();
1091 Register ListReg = I.getOperand(0).getReg();
1150 BuildMovK(DstReg, AArch64II::MO_G3, 48, I.getOperand(0).getReg());
1169 Register SrcReg = I.getOperand(1).getReg();
1170 Register ShiftReg = I.getOperand(2).getReg();
1205 auto VRegAndVal = getConstantVRegVal(MO.getReg(), MRI);
1209 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
1222 {I.getOperand(0).getReg()}, {I.getOperand(1).getReg()});
1222 {I.getOperand(0).getReg()}, {I.getOperand(1).getReg()});
1250 MachineInstr *Def = getDefIgnoringCopies(I.getOperand(0).getReg(), MRI);
1253 Register DefDstReg = Def->getOperand(0).getReg();
1255 Register StoreSrcReg = I.getOperand(0).getReg();
1296 Register DefReg = I.getOperand(0).getReg();
1333 const Register DefReg = I.getOperand(0).getReg();
1389 I.getOperand(0).isReg() ? MRI.getType(I.getOperand(0).getReg()) : LLT{};
1404 const Register CondReg = I.getOperand(0).getReg();
1449 Register DstReg = I.getOperand(0).getReg();
1494 const Register DefReg = I.getOperand(0).getReg();
1580 Register DstReg = I.getOperand(0).getReg();
1581 Register SrcReg = I.getOperand(1).getReg();
1630 MIB.buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {})
1632 RBI.constrainGenericRegister(I.getOperand(0).getReg(),
1640 LLT SrcTy = MRI.getType(I.getOperand(2).getReg());
1641 LLT DstTy = MRI.getType(I.getOperand(0).getReg());
1650 unsigned Width = MRI.getType(I.getOperand(2).getReg()).getSizeInBits();
1665 .addUse(I.getOperand(2).getReg())
1667 RBI.constrainGenericRegister(I.getOperand(2).getReg(),
1722 LLT PtrTy = MRI.getType(I.getOperand(1).getReg());
1744 const Register PtrReg = I.getOperand(1).getReg();
1754 const Register ValReg = I.getOperand(0).getReg();
1769 if (auto COff = getConstantVRegVal(PtrMI->getOperand(2).getReg(), MRI)) {
1774 Register Ptr2Reg = PtrMI->getOperand(1).getReg();
1806 Register DstReg = I.getOperand(0).getReg();
1827 const Register DefReg = I.getOperand(0).getReg();
1855 if (MRI.getType(I.getOperand(0).getReg()).isVector())
1860 MRI.getType(I.getOperand(0).getReg()).isVector())
1871 const Register DefReg = I.getOperand(0).getReg();
1888 emitADD(I.getOperand(0).getReg(), I.getOperand(1), I.getOperand(2),
1913 AddsOpc, {I.getOperand(0).getReg()},
1914 {I.getOperand(2).getReg(), I.getOperand(3).getReg()});
1914 {I.getOperand(2).getReg(), I.getOperand(3).getReg()});
1922 .buildInstr(AArch64::CSINCWr, {I.getOperand(1).getReg()},
1943 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
1944 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
1946 const Register DstReg = I.getOperand(0).getReg();
1947 const Register SrcReg = I.getOperand(1).getReg();
2014 const Register DstReg = I.getOperand(0).getReg();
2015 const Register SrcReg = I.getOperand(1).getReg();
2061 const Register DefReg = I.getOperand(0).getReg();
2062 const Register SrcReg = I.getOperand(1).getReg();
2131 const LLT DstTy = MRI.getType(I.getOperand(0).getReg()),
2132 SrcTy = MRI.getType(I.getOperand(1).getReg());
2158 if (MRI.getType(I.getOperand(1).getReg()) != LLT::scalar(1)) {
2164 const Register CondReg = I.getOperand(1).getReg();
2165 const Register TReg = I.getOperand(2).getReg();
2166 const Register FReg = I.getOperand(3).getReg();
2179 .addDef(I.getOperand(0).getReg())
2204 emitCSetForICMP(I.getOperand(0).getReg(), I.getOperand(1).getPredicate(),
2230 .addUse(I.getOperand(2).getReg());
2236 CmpMI = CmpMI.addUse(I.getOperand(3).getReg());
2238 const Register DefReg = I.getOperand(0).getReg();
2281 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
2282 const Register DstReg = I.getOperand(0).getReg();
2297 I.getOperand(0).getReg())
2335 Register JTAddr = I.getOperand(0).getReg();
2337 Register Index = I.getOperand(2).getReg();
2357 Register DstReg = I.getOperand(0).getReg();
2393 MIB.buildCopy(I.getOperand(0).getReg(), Register(AArch64::X0));
2394 RBI.constrainGenericRegister(I.getOperand(0).getReg(), AArch64::GPR64RegClass,
2402 const LLT SrcTy = MRI.getType(I.getOperand(0).getReg());
2457 const LLT SrcTy = MRI.getType(I.getOperand(0).getReg());
2512 Register DstReg = I.getOperand(0).getReg();
2514 Register SrcReg = I.getOperand(2).getReg();
2515 Register Src2Reg = I.getOperand(3).getReg();
2712 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
2713 const LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
2715 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);
2725 Register DstReg = I.getOperand(0).getReg();
2726 Register Src1Reg = I.getOperand(1).getReg();
2727 Register Src2Reg = I.getOperand(2).getReg();
2733 MachineInstr *Ins2MI = emitLaneInsert(DstReg, InsMI->getOperand(0).getReg(),
2755 .addUse(I.getOperand(1).getReg())
2763 .addUse(I.getOperand(2).getReg())
2767 .addDef(I.getOperand(0).getReg())
2852 InsertReg = ScalarToVector->getOperand(0).getReg();
2868 Register DstReg = I.getOperand(0).getReg();
2870 const Register SrcReg = I.getOperand(1).getReg();
2887 auto VRegAndVal = getConstantVRegValWithLookThrough(LaneIdxOp.getReg(), MRI);
2907 Register SrcReg = I.getOperand(NumElts).getReg();
2908 const LLT NarrowTy = MRI.getType(I.getOperand(0).getReg());
2922 *RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI);
2924 Register Dst = I.getOperand(OpIdx).getReg();
2940 if (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() !=
2942 RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI)->getID() !=
2952 Register SrcReg = I.getOperand(NumElts).getReg();
2953 const LLT NarrowTy = MRI.getType(I.getOperand(0).getReg());
3017 Register CopyTo = I.getOperand(0).getReg();
3025 Register CopyTo = I.getOperand(LaneIdx).getReg();
3038 MRI.getRegClassOrNull(I.getOperand(1).getReg());
3053 Register Dst = I.getOperand(0).getReg();
3054 Register Op1 = I.getOperand(1).getReg();
3055 Register Op2 = I.getOperand(2).getReg();
3152 bool Is32Bit = MRI.getType(LHS.getReg()).getSizeInBits() == 32;
3155 auto AddMI = MIRBuilder.buildInstr(Opc, {DefReg}, {LHS.getReg()});
3162 AddMI.addUse(RHS.getReg());
3176 bool Is32Bit = (MRI.getType(LHS.getReg()).getSizeInBits() == 32);
3181 auto CmpMI = MIRBuilder.buildInstr(Opc, {ZReg}, {LHS.getReg()});
3188 CmpMI.addUse(RHS.getReg());
3239 LLT CmpTy = MRI.getType(LHS.getReg());
3257 auto CmpMI = MIRBuilder.buildInstr(CmpOpc).addDef(ZReg).addUse(LHS.getReg());
3263 CmpMI.addUse(RHS.getReg());
3323 .buildInstr(InsertOpc, {*Dst}, {WidenedOp1->getOperand(0).getReg()})
3325 .addUse(WidenedOp2->getOperand(0).getReg())
3336 unsigned DefSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
3401 MachineInstr *CondDef = MRI.getVRegDef(I.getOperand(1).getReg());
3404 if (!MRI.hasOneUse(CondDef->getOperand(0).getReg()))
3415 Register::isPhysicalRegister(CondDef->getOperand(1).getReg()))
3418 CondDef = MRI.getVRegDef(CondDef->getOperand(1).getReg());
3458 auto Cmp = MIB.buildInstr(CmpOpc, {}, {CondDef->getOperand(2).getReg()});
3460 Cmp.addUse(CondDef->getOperand(3).getReg());
3467 MIB.buildInstr(CSelOpc, {I.getOperand(0).getReg()},
3468 {I.getOperand(2).getReg(), I.getOperand(3).getReg()})
3468 {I.getOperand(2).getReg(), I.getOperand(3).getReg()})
3507 getConstantVRegValWithLookThrough(DefMI->getOperand(1).getReg(), MRI);
3516 MachineInstr *LHSDef = getDefIgnoringCopies(LHS.getReg(), MRI);
3517 MachineInstr *RHSDef = getDefIgnoringCopies(RHS.getReg(), MRI);
3556 auto ValAndVReg = getConstantVRegValWithLookThrough(RHS.getReg(), MRI);
3560 return emitTST(LHSDef->getOperand(1).getReg(),
3561 LHSDef->getOperand(2).getReg(), MIRBuilder);
3589 getOpcodeDef(G_INSERT_VECTOR_ELT, I.getOperand(1).getReg(), MRI);
3594 getOpcodeDef(G_IMPLICIT_DEF, InsMI->getOperand(1).getReg(), MRI);
3598 Register ScalarReg = InsMI->getOperand(2).getReg();
3602 if (!mi_match(InsMI->getOperand(3).getReg(), MRI, m_ICst(Index)) || Index)
3611 LLT VecTy = MRI.getType(I.getOperand(0).getReg());
3629 ScalarReg = Widen->getOperand(0).getReg();
3631 auto Dup = MIB.buildInstr(Opc, {I.getOperand(0).getReg()}, {ScalarReg});
3651 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
3652 Register Src1Reg = I.getOperand(1).getReg();
3654 Register Src2Reg = I.getOperand(2).getReg();
3708 IndexLoad->getOperand(0).getReg(), MIRBuilder);
3712 {Concat->getOperand(0).getReg(), IndexLoad->getOperand(0).getReg()});
3712 {Concat->getOperand(0).getReg(), IndexLoad->getOperand(0).getReg()});
3717 .buildInstr(TargetOpcode::COPY, {I.getOperand(0).getReg()}, {})
3734 MIRBuilder.buildInstr(AArch64::TBLv16i8Two, {I.getOperand(0).getReg()},
3735 {RegSeq, IndexLoad->getOperand(0).getReg()});
3761 .addUse(InsSub->getOperand(0).getReg())
3778 Register DstReg = I.getOperand(0).getReg();
3783 Register EltReg = I.getOperand(2).getReg();
3791 Register IdxReg = I.getOperand(3).getReg();
3798 Register SrcReg = I.getOperand(1).getReg();
3809 SrcReg = ScalarToVec->getOperand(0).getReg();
3821 Register DemoteVec = InsMI->getOperand(0).getReg();
3854 const LLT DstTy = MRI.getType(I.getOperand(0).getReg());
3855 const LLT EltTy = MRI.getType(I.getOperand(1).getReg());
3859 const RegisterBank &RB = *RBI.getRegBank(I.getOperand(1).getReg(), MRI, TRI);
3865 I.getOperand(1).getReg(), MIRBuilder);
3869 Register DstVec = ScalarToVec->getOperand(0).getReg();
3878 PrevMI = &*emitLaneInsert(None, DstVec, I.getOperand(i).getReg(), i - 1, RB,
3880 DstVec = PrevMI->getOperand(0).getReg();
3906 Register DstReg = I.getOperand(0).getReg();
3917 PrevMI->getOperand(0).setReg(I.getOperand(0).getReg());
3973 Register DstReg = I.getOperand(0).getReg();
3974 Register SrcReg = I.getOperand(2).getReg();
3988 RBI.constrainGenericRegister(I.getOperand(2).getReg(),
4000 if (DstReg != I.getOperand(0).getReg()) {
4004 RBI.constrainGenericRegister(I.getOperand(0).getReg(),
4026 getConstantVRegValWithLookThrough(Root.getReg(), MRI, true);
4133 if (MRI.getType(Root.getReg()).getSizeInBits() == 32)
4151 Register DefReg = MI.getOperand(0).getReg();
4200 MachineInstr *Gep = getOpcodeDef(TargetOpcode::G_GEP, Root.getReg(), MRI);
4206 MachineInstr *OffsetInst = getDefIgnoringCopies(Gep->getOperand(2).getReg(), MRI);
4220 Register OffsetReg = OffsetInst->getOperand(1).getReg();
4221 Register ConstantReg = OffsetInst->getOperand(2).getReg();
4261 MIB.addUse(Gep->getOperand(1).getReg());
4286 MachineInstr *Gep = MRI.getVRegDef(Root.getReg());
4293 if (!MRI.hasOneUse(Gep->getOperand(0).getReg()))
4298 MIB.addUse(Gep->getOperand(1).getReg());
4301 MIB.addUse(Gep->getOperand(2).getReg());
4350 MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
4357 MachineInstr *RHS = MRI.getVRegDef(OffImm.getReg());
4391 MachineInstr *RootDef = MRI.getVRegDef(Root.getReg());
4405 MachineInstr *LHSDef = MRI.getVRegDef(LHS.getReg());
4406 MachineInstr *RHSDef = MRI.getVRegDef(RHS.getReg());
4467 MachineInstr *ShiftInst = MRI.getVRegDef(Root.getReg());
4485 Register ShiftReg = ShiftLHS.getReg();
4502 unsigned Size = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
4517 unsigned Size = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
4580 MachineInstr *RootDef = getDefIgnoringCopies(Root.getReg(), MRI);
4599 MachineInstr *ExtDef = getDefIgnoringCopies(LHS.getReg(), MRI);
4605 ExtReg = ExtDef->getOperand(1).getReg();
4611 ExtReg = RootDef->getOperand(1).getReg();
4639 Optional<int64_t> CstVal = getConstantVRegVal(MI.getOperand(0).getReg(), MRI);
4671 if (MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() != 32)
lib/Target/AArch64/AArch64LegalizerInfo.cpp 667 Register AmtReg = MI.getOperand(2).getReg();
697 Register ValReg = MI.getOperand(0).getReg();
712 MIRBuilder.buildStore(Bitcast.getReg(0), MI.getOperand(1).getReg(), MMO);
715 auto NewLoad = MIRBuilder.buildLoad(NewReg, MI.getOperand(1).getReg(), MMO);
728 Register Dst = MI.getOperand(0).getReg();
729 Register ListPtr = MI.getOperand(1).getReg();
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 639 getLdStRegOp(MI).getReg() == AArch64::WZR;
875 Register Reg = getLdStRegOp(*I).getReg();
904 Register DstRegX = DstMO.getReg();
949 Register LdRt = getLdStRegOp(*LoadI).getReg();
951 Register StRt = getLdStRegOp(*StoreI).getReg();
1109 Register BaseReg = getLdStBaseOp(LoadMI).getReg();
1136 BaseReg == getLdStBaseOp(MI).getReg() &&
1138 ModifiedRegUnits.available(getLdStRegOp(MI).getReg())) {
1223 Register Reg = getLdStRegOp(FirstMI).getReg();
1224 Register BaseReg = getLdStBaseOp(FirstMI).getReg();
1255 Register MIBaseReg = getLdStBaseOp(MI).getReg();
1287 (IsPromotableZeroStore && Reg != getLdStRegOp(MI).getReg())) {
1317 if (MayLoad && Reg == getLdStRegOp(MI).getReg()) {
1328 if (ModifiedRegUnits.available(getLdStRegOp(MI).getReg()) &&
1330 !UsedRegUnits.available(getLdStRegOp(MI).getReg())) &&
1340 if (ModifiedRegUnits.available(getLdStRegOp(FirstMI).getReg()) &&
1342 !UsedRegUnits.available(getLdStRegOp(FirstMI).getReg())) &&
1459 if (MI.getOperand(0).getReg() != BaseReg ||
1460 MI.getOperand(1).getReg() != BaseReg)
1494 Register BaseReg = getLdStBaseOp(MemMI).getReg();
1512 Register DestReg = getLdStRegOp(MemMI, i).getReg();
1554 Register BaseReg = getLdStBaseOp(MemMI).getReg();
1566 Register DestReg = getLdStRegOp(MemMI, i).getReg();
lib/Target/AArch64/AArch64MCInstLower.cpp 261 MCOp = MCOperand::createReg(MO.getReg());
lib/Target/AArch64/AArch64PBQPRegAlloc.cpp 362 Register Rd = MI.getOperand(0).getReg();
363 Register Ra = MI.getOperand(3).getReg();
372 Register Rd = MI.getOperand(0).getReg();
lib/Target/AArch64/AArch64RedundantCopyElimination.cpp 136 KnownRegs.push_back(RegImm(CondBr.getOperand(0).getReg(), 0));
186 MCPhysReg DstReg = PredI.getOperand(0).getReg();
187 MCPhysReg SrcReg = PredI.getOperand(1).getReg();
252 MCPhysReg DstReg = PredI.getOperand(0).getReg();
324 MCPhysReg CopyDstReg = PredI->getOperand(0).getReg();
325 MCPhysReg CopySrcReg = PredI->getOperand(1).getReg();
382 Register DefReg = MI->getOperand(0).getReg();
383 Register SrcReg = IsCopy ? MI->getOperand(1).getReg() : Register();
408 O.getReg() != CmpReg;
lib/Target/AArch64/AArch64RegisterBankInfo.cpp 279 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
300 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
336 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
428 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
444 LLT OpTy = MRI.getType(MI.getOperand(Idx).getReg());
475 return getRegBank(MI.getOperand(0).getReg(), MRI, TRI) ==
547 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
548 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
558 LLT ShiftAmtTy = MRI.getType(MI.getOperand(2).getReg());
559 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
566 Register DstReg = MI.getOperand(0).getReg();
567 Register SrcReg = MI.getOperand(1).getReg();
593 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
594 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
619 if (!MO.isReg() || !MO.getReg())
622 LLT Ty = MRI.getType(MO.getReg());
639 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
646 if (MRI.getType(MI.getOperand(0).getReg()).isVector())
652 if (MRI.getType(MI.getOperand(0).getReg()).isVector())
682 MRI.use_instructions(MI.getOperand(0).getReg())) {
696 Register VReg = MI.getOperand(0).getReg();
712 LLT SrcTy = MRI.getType(MI.getOperand(2).getReg());
730 MRI.use_instructions(MI.getOperand(0).getReg()),
748 Register VReg = MI.getOperand(Idx).getReg();
768 LLT SrcTy = MRI.getType(MI.getOperand(MI.getNumOperands()-1).getReg());
772 any_of(MRI.use_instructions(MI.getOperand(0).getReg()),
794 if (getRegBank(MI.getOperand(2).getReg(), MRI, TRI) == &AArch64::FPRRegBank)
804 LLT SrcTy = MRI.getType(MI.getOperand(1).getReg());
816 Register VReg = MI.getOperand(1).getReg();
840 if (MI.getOperand(Idx).isReg() && MI.getOperand(Idx).getReg()) {
lib/Target/AArch64/AArch64RegisterInfo.cpp 488 FrameReg = MI.getOperand(3).getReg();
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 326 CurrentMI->getOperand(1).getReg() == SrcReg &&
328 *DestReg = CurrentMI->getOperand(0).getReg();
429 Register MulDest = MI.getOperand(0).getReg();
430 Register SrcReg0 = MI.getOperand(1).getReg();
432 Register SrcReg1 = MI.getOperand(2).getReg();
438 Register SrcReg2 = MI.getOperand(3).getReg();
517 SeqReg = MI.getOperand(0).getReg();
518 AddrReg = MI.getOperand(1).getReg();
638 StReg[i] = DefiningMI->getOperand(2*i+1).getReg();
lib/Target/AArch64/AArch64SpeculationHardening.cpp 485 return Op.isReg() && (AArch64::GPR32allRegClass.contains(Op.getReg()) ||
486 AArch64::GPR64allRegClass.contains(Op.getReg()));
499 for (MCRegAliasIterator AI(Op.getReg(), TRI, true); AI.isValid(); ++AI)
518 Modified |= makeGPRSpeculationSafe(MBB, NextMBBI, MI, Def.getReg());
525 Register Reg = Use.getReg();
565 Register DstReg = MI.getOperand(0).getReg();
566 Register SrcReg = MI.getOperand(1).getReg();
571 for (MCRegAliasIterator AI(Op.getReg(), TRI, true); AI.isValid(); ++AI)
632 if (Op.isReg() && RegsNeedingCSDBBeforeUse[Op.getReg()]) {
lib/Target/AArch64/AArch64StackTaggingPreRA.cpp 155 UseI->getOperand(OpIdx).getReg() == TaggedReg) {
160 Register::isVirtualRegister(UseI->getOperand(0).getReg())) {
161 uncheckUsesOf(UseI->getOperand(0).getReg(), FI);
168 unsigned TaggedReg = I->getOperand(0).getReg();
lib/Target/AArch64/AArch64StorePairSuppress.cpp 154 Register BaseReg = BaseOp->getReg();
lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp 707 Register Reg = MO.getReg();
1297 AMDGPUInstPrinter::printRegOperand(MO.getReg(), O,
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 119 Register DstReg = Dst.getReg();
120 Register SrcReg = Src.getReg();
168 if (Register::isPhysicalRegister(MO.getReg()))
175 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI);
181 const Register DefReg = I.getOperand(0).getReg();
225 Register Reg = MO.getReg();
266 Register DstReg = Dst.getReg();
280 if (Src0.isUndef() && !MRI->getRegClassOrNull(Src0.getReg()))
281 MRI->setRegClass(Src0.getReg(), RC);
282 if (Src1.isUndef() && !MRI->getRegClassOrNull(Src1.getReg()))
283 MRI->setRegClass(Src1.getReg(), RC);
302 Register DstReg = I.getOperand(0).getReg();
401 Register Dst0Reg = I.getOperand(0).getReg();
402 Register Dst1Reg = I.getOperand(1).getReg();
416 Register Src0Reg = I.getOperand(2).getReg();
417 Register Src1Reg = I.getOperand(3).getReg();
446 I.getOperand(0).getReg())
447 .addReg(I.getOperand(1).getReg(), 0, SubReg);
454 RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI);
462 Register DstReg = MI.getOperand(0).getReg();
464 LLT SrcTy = MRI->getType(MI.getOperand(1).getReg());
483 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef()));
488 if (SrcRC && !RBI.constrainGenericRegister(Src.getReg(), *SrcRC, *MRI))
505 Register SrcReg = Src.getReg();
506 Register DstReg0 = MI.getOperand(0).getReg();
528 BuildMI(*BB, &MI, DL, TII.get(TargetOpcode::COPY), Dst.getReg())
533 if (DstRC && !RBI.constrainGenericRegister(Dst.getReg(), *DstRC, *MRI))
551 if ((!RC && !MRI->getRegBankOrNull(MO.getReg())) ||
552 (RC && RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI))) {
563 Register DstReg = I.getOperand(0).getReg();
564 Register Src0Reg = I.getOperand(1).getReg();
565 Register Src1Reg = I.getOperand(2).getReg();
626 Register DstReg = I.getOperand(0).getReg();
627 Register Src0Reg = I.getOperand(2).getReg();
628 Register Src1Reg = I.getOperand(3).getReg();
720 Register SrcReg = I.getOperand(2).getReg();
725 Register CCReg = I.getOperand(0).getReg();
747 I.getOperand(0).getReg())
750 RBI.constrainGenericRegister(ICmp->getOperand(0).getReg(),
821 if (mi_match(Def->getOperand(1).getReg(), MRI, m_ICst(Offset)))
822 return std::make_tuple(Def->getOperand(0).getReg(), Offset, Def);
825 if (mi_match(Def->getOperand(1).getReg(), MRI, m_Copy(m_ICst(Offset))))
826 return std::make_tuple(Def->getOperand(0).getReg(), Offset, Def);
982 Register VData = MI.getOperand(1).getReg();
993 Register RSrc = MI.getOperand(2).getReg();
994 Register VOffset = MI.getOperand(3).getReg();
995 Register SOffset = MI.getOperand(4).getReg();
1043 MachineInstr *Exp = buildEXP(TII, &I, Tgt, I.getOperand(3).getReg(),
1044 I.getOperand(4).getReg(),
1045 I.getOperand(5).getReg(),
1046 I.getOperand(6).getReg(),
1056 Register Reg0 = I.getOperand(3).getReg();
1057 Register Reg1 = I.getOperand(4).getReg();
1076 Register Reg = I.getOperand(1).getReg();
1096 Register DstReg = I.getOperand(0).getReg();
1100 Register CCReg = CCOp.getReg();
1166 Register DstReg = I.getOperand(0).getReg();
1167 Register SrcReg = I.getOperand(1).getReg();
1221 const Register DstReg = I.getOperand(0).getReg();
1222 const Register SrcReg = I.getOperand(1).getReg();
1372 Register Src = I.getOperand(1).getReg();
1377 Register DstReg = I.getOperand(0).getReg();
1410 Register DstReg = I.getOperand(0).getReg();
1413 const RegisterBank *RB = MRI->getRegBankOrNull(I.getOperand(0).getReg());
1477 const MachineInstr *PtrMI = MRI.getUniqueVRegDef(Load.getOperand(1).getReg());
1488 const MachineInstr *OpDef = MRI.getUniqueVRegDef(GEPOp.getReg());
1497 const RegisterBank *OpBank = RBI.getRegBank(GEPOp.getReg(), MRI, TRI);
1499 GEPInfo.SgprParts.push_back(GEPOp.getReg());
1501 GEPInfo.VgprParts.push_back(GEPOp.getReg());
1541 const LLT PtrTy = MRI->getType(I.getOperand(1).getReg());
1559 Register CondReg = CondOp.getReg();
1601 Register DstReg = I.getOperand(0).getReg();
1618 Register DstReg = I.getOperand(0).getReg();
1619 Register SrcReg = I.getOperand(1).getReg();
1786 Src = MI->getOperand(1).getReg();
1792 Src = MI->getOperand(1).getReg();
1813 std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg());
1827 std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg());
1850 std::tie(Src, Mods) = selectVOP3ModsImpl(Root.getReg());
1862 [=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); },
1872 [=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); },
1955 [=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); },
1963 const MachineInstr *OpDef = MRI->getVRegDef(Root.getReg());
1968 getConstantVRegVal(OpDef->getOperand(2).getReg(), *MRI);
1976 Register BasePtr = OpDef->getOperand(1).getReg();
2008 if (mi_match(Root.getReg(), *MRI, m_ICst(Offset))) {
2042 Register VAddr = Root.getReg();
2043 if (const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg())) {
2047 const MachineInstr *LHSDef = MRI->getVRegDef(LHS.getReg());
2048 const MachineInstr *RHSDef = MRI->getVRegDef(RHS.getReg());
2054 KnownBits->signBitIsZero(LHS.getReg()))) {
2058 VAddr = LHS.getReg();
2104 return KnownBits->signBitIsZero(Base.getReg());
2114 if (!mi_match(Root.getReg(), *MRI, m_ICst(Offset)) ||
2137 const MachineInstr *RootDef = MRI->getVRegDef(Root.getReg());
2149 const MachineInstr *LHSDef = MRI->getVRegDef(LHS.getReg());
2150 const MachineInstr *RHSDef = MRI->getVRegDef(RHS.getReg());
2166 } else if (mi_match(Root.getReg(), *MRI, m_ICst(ConstAddr))) {
2181 Optional<int64_t> CstVal = getConstantVRegVal(MI.getOperand(0).getReg(), MRI);
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1218 Register Dst = MI.getOperand(0).getReg();
1219 Register Src = MI.getOperand(1).getReg();
1321 Register Src = MI.getOperand(1).getReg();
1339 B.buildSelect(MI.getOperand(0).getReg(), Cond, Src, Tmp2);
1351 Register Src = MI.getOperand(1).getReg();
1368 B.buildFAdd(MI.getOperand(0).getReg(), Trunc, Add);
1397 Register Src = MI.getOperand(1).getReg();
1430 B.buildSelect(MI.getOperand(0).getReg(), ExpGt51, Src, Tmp1);
1439 Register Dst = MI.getOperand(0).getReg();
1440 Register Src = MI.getOperand(1).getReg();
1497 Optional<int64_t> IdxVal = getConstantVRegVal(MI.getOperand(2).getReg(), MRI);
1501 Register Dst = MI.getOperand(0).getReg();
1502 Register Vec = MI.getOperand(1).getReg();
1526 Optional<int64_t> IdxVal = getConstantVRegVal(MI.getOperand(3).getReg(), MRI);
1530 Register Dst = MI.getOperand(0).getReg();
1531 Register Vec = MI.getOperand(1).getReg();
1532 Register Ins = MI.getOperand(2).getReg();
1554 Register DstReg = MI.getOperand(0).getReg();
1555 Register SrcReg = MI.getOperand(1).getReg();
1637 Register DstReg = MI.getOperand(0).getReg();
1709 auto Cast = B.buildAddrSpaceCast(ConstPtr, MI.getOperand(1).getReg());
1719 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
1739 Register DstReg = MI.getOperand(0).getReg();
1740 Register PtrReg = MI.getOperand(1).getReg();
1741 Register CmpVal = MI.getOperand(2).getReg();
1742 Register NewVal = MI.getOperand(3).getReg();
1767 Register CondDef = MI.getOperand(0).getReg();
1851 if (loadInputValue(MI.getOperand(0).getReg(), B, Arg)) {
1863 Register Dst = MI.getOperand(0).getReg();
1879 Register Res = MI.getOperand(0).getReg();
1880 Register LHS = MI.getOperand(1).getReg();
1881 Register RHS = MI.getOperand(2).getReg();
1940 Register Res = MI.getOperand(0).getReg();
1941 Register LHS = MI.getOperand(1).getReg();
1942 Register RHS = MI.getOperand(2).getReg();
1973 Register Res = MI.getOperand(0).getReg();
1974 Register LHS = MI.getOperand(2).getReg();
1975 Register RHS = MI.getOperand(3).getReg();
2019 Register DstReg = MI.getOperand(0).getReg();
2045 auto Hi32 = B.buildExtract(LLT::scalar(32), MI.getOperand(2).getReg(), 32);
2079 Register VData = MI.getOperand(1).getReg();
2118 Register Def = MI.getOperand(1).getReg();
2119 Register Use = MI.getOperand(3).getReg();
2140 Register Reg = MI.getOperand(2).getReg();
lib/Target/AMDGPU/AMDGPUMCInstLower.cpp 135 MCOp = MCOperand::createReg(AMDGPU::getMCReg(MO.getReg(), ST));
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 319 return PHI.getOperand(Index * 2 + 1).getReg();
324 return PHI.getOperand(0).getReg();
758 storeLiveOutReg(MBB, RI.getReg(), RI.getParent(), MRI, TRI, PHIInfo);
762 storeLiveOutReg(MBB, IRI.getReg(), IRI.getParent(), MRI, TRI, PHIInfo);
800 storeLiveOutRegRegion(TopRegion, RI.getReg(), RI.getParent(), MRI, TRI,
805 storeLiveOutRegRegion(TopRegion, IRI.getReg(), IRI.getParent(), MRI,
1026 Register Reg = RI.getReg();
1895 Register CondReg = Cond[0].getReg();
lib/Target/AMDGPU/AMDGPUMacroFusion.cpp 49 return FirstMI->definesRegister(Src2->getReg(), TRI);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 62 Register Reg = Op.getReg();
188 Register Reg = MI.getOperand(RegSrcOpIdx[I]).getReg();
193 unsigned SizeI = getSizeInBits(MI.getOperand(I).getReg(), MRI, *TRI);
348 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
375 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
446 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
447 LLT PtrTy = MRI.getType(MI.getOperand(1).getReg());
450 LLT LoadTy = MRI.getType(MI.getOperand(0).getReg());
479 unsigned Size = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI);
515 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
555 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
577 assert(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 1);
687 LLT ResTy = MRI.getType(Def.getReg());
688 const RegisterBank *DefBank = getRegBank(Def.getReg(), MRI, *TRI);
689 ResultRegs.push_back(Def.getReg());
769 if (SGPROperandRegs.count(Op.getReg())) {
770 LLT OpTy = MRI.getType(Op.getReg());
780 constrainGenericRegister(Op.getReg(), AMDGPU::VGPR_32RegClass, MRI);
784 .addReg(Op.getReg());
795 .addReg(Op.getReg());
827 auto Unmerge = B.buildUnmerge(UnmergeTy, Op.getReg());
913 MRI.setRegBank(Op.getReg(), getRegBank(AMDGPU::SGPRRegBankID));
966 Register Reg = MI.getOperand(Op).getReg();
1001 Register Reg = MI.getOperand(OpIdx).getReg();
1040 Register DstReg = MI.getOperand(0).getReg();
1053 Register PtrReg = MI.getOperand(1).getReg();
1070 LLT PtrTy = MRI.getType(MI.getOperand(1).getReg());
1256 Register VData = MI.getOperand(1).getReg();
1270 Register RSrc = MI.getOperand(2).getReg();
1271 Register VOffset = MI.getOperand(3).getReg();
1272 Register SOffset = MI.getOperand(4).getReg();
1333 Register DstReg = MI.getOperand(0).getReg();
1353 Src0Regs.push_back(MI.getOperand(1).getReg());
1359 split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg());
1365 split64BitValueForMapping(B, Src2Regs, HalfTy, MI.getOperand(3).getReg());
1383 Register DstReg = MI.getOperand(0).getReg();
1409 split64BitValueForMapping(B, Src0Regs, HalfTy, MI.getOperand(1).getReg());
1414 split64BitValueForMapping(B, Src1Regs, HalfTy, MI.getOperand(2).getReg());
1437 Register DstReg = MI.getOperand(0).getReg();
1462 Register DstReg = MI.getOperand(0).getReg();
1495 Register SrcReg = MI.getOperand(1).getReg();
1502 Register DstReg = MI.getOperand(0).getReg();
1593 Register DstReg = MI.getOperand(0).getReg();
1608 Register Lo = MI.getOperand(1).getReg();
1609 Register Hi = MI.getOperand(2).getReg();
1662 Register DstReg = MI.getOperand(0).getReg();
1663 Register SrcReg = MI.getOperand(1).getReg();
1664 Register IdxReg = MI.getOperand(2).getReg();
1728 Register DstReg = MI.getOperand(0).getReg();
1729 Register SrcReg = MI.getOperand(1).getReg();
1730 Register InsReg = MI.getOperand(2).getReg();
1731 Register IdxReg = MI.getOperand(3).getReg();
1909 Register Reg = MI.getOperand(i).getReg();
1928 unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
1943 unsigned Size0 = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
1949 Register Reg1 = MI.getOperand(OpdIdx).getReg();
1963 unsigned Size = getSizeInBits(MO.getReg(), MRI, *TRI);
1983 unsigned Size = getSizeInBits(Op.getReg(), MRI, *TRI);
2008 Register OpReg = MI.getOperand(I).getReg();
2036 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
2037 LLT LoadTy = MRI.getType(MI.getOperand(0).getReg());
2038 Register PtrReg = MI.getOperand(1).getReg();
2122 auto OpBank = getRegBankID(MI.getOperand(I).getReg(), MRI, *TRI);
2130 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
2147 Register Reg = MI.getOperand(I).getReg();
2175 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2197 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2200 = getRegBank(MI.getOperand(0).getReg(), MRI, *TRI);
2216 BankLHS = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
2218 BankRHS = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI,
2222 BankLHS = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
2224 BankRHS = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI,
2259 unsigned Bank1 = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI/*, DefaultBankID*/);
2262 unsigned Bank2 = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI/*, DefaultBankID*/);
2325 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2333 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2340 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2347 unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
2348 unsigned SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
2349 unsigned EltSize = getSizeInBits(MI.getOperand(2).getReg(), MRI, *TRI);
2357 unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
2358 unsigned DstSize = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
2359 unsigned SrcSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
2367 LLT DstTy = MRI.getType(MI.getOperand(0).getReg());
2370 unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
2371 unsigned Src0BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
2372 unsigned Src1BankID = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
2387 unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2388 unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
2408 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2409 unsigned BankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
2414 Register Dst = MI.getOperand(0).getReg();
2415 Register Src = MI.getOperand(1).getReg();
2426 Register Dst = MI.getOperand(0).getReg();
2427 Register Src = MI.getOperand(1).getReg();
2458 unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
2459 unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
2468 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2486 unsigned Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
2487 unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
2488 unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
2506 unsigned SrcBankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
2507 unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2508 unsigned SrcSize = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
2509 unsigned IdxSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
2510 unsigned IdxBank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
2524 unsigned VecSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2525 unsigned InsertSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
2526 unsigned IdxSize = MRI.getType(MI.getOperand(3).getReg()).getSizeInBits();
2527 unsigned SrcBankID = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI);
2528 unsigned InsertEltBankID = getRegBankID(MI.getOperand(2).getReg(),
2530 unsigned IdxBankID = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
2548 unsigned Size = getSizeInBits(MI.getOperand(i).getReg(), MRI, *TRI);
2618 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2623 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2630 Register RSrc = MI.getOperand(2).getReg(); // SGPR
2631 Register Offset = MI.getOperand(3).getReg(); // SGPR/imm
2633 unsigned Size0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2651 unsigned Dst0Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2652 unsigned Dst1Size = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
2656 unsigned SrcSize = MRI.getType(MI.getOperand(3).getReg()).getSizeInBits();
2658 getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI), SrcSize);
2660 getRegBankID(MI.getOperand(4).getReg(), MRI, *TRI), SrcSize);
2665 Register Src0Reg = MI.getOperand(2).getReg();
2666 Register Src1Reg = MI.getOperand(3).getReg();
2669 unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2679 unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2682 unsigned OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
2683 unsigned Op1Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI);
2684 unsigned Op2Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI);
2691 Register IdxReg = MI.getOperand(3).getReg();
2698 unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2699 unsigned SrcSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
2705 unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2706 Register SrcReg = MI.getOperand(2).getReg();
2709 Register IdxReg = MI.getOperand(3).getReg();
2722 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, *TRI);
2738 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2752 unsigned DstSize = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2754 unsigned M0Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI,
2780 Register RSrc = MI.getOperand(2).getReg(); // SGPR
2781 Register VIndex = MI.getOperand(3).getReg(); // VGPR
2782 Register Offset = MI.getOperand(4).getReg(); // SGPR/VGPR/imm
2784 unsigned Size0 = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2807 unsigned Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI,
2814 unsigned Size = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
2819 unsigned WaveSize = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
2833 OpdsMapping[0] = getVGPROpMapping(MI.getOperand(0).getReg(), MRI, *TRI);
2834 OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI);
2835 OpdsMapping[3] = getVGPROpMapping(MI.getOperand(3).getReg(), MRI, *TRI);
2836 OpdsMapping[4] = getSGPROpMapping(MI.getOperand(4).getReg(), MRI, *TRI);
2842 OpdsMapping[1] = getVGPROpMapping(MI.getOperand(1).getReg(), MRI, *TRI);
2843 OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI);
2844 OpdsMapping[3] = getVGPROpMapping(MI.getOperand(3).getReg(), MRI, *TRI);
2845 OpdsMapping[4] = getSGPROpMapping(MI.getOperand(4).getReg(), MRI, *TRI);
2850 OpdsMapping[0] = getVGPROpMapping(MI.getOperand(0).getReg(), MRI, *TRI);
2851 OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI);
2852 OpdsMapping[3] = getVGPROpMapping(MI.getOperand(3).getReg(), MRI, *TRI);
2853 OpdsMapping[4] = getVGPROpMapping(MI.getOperand(4).getReg(), MRI, *TRI);
2854 OpdsMapping[5] = getSGPROpMapping(MI.getOperand(5).getReg(), MRI, *TRI);
2859 OpdsMapping[1] = getVGPROpMapping(MI.getOperand(1).getReg(), MRI, *TRI);
2860 OpdsMapping[2] = getSGPROpMapping(MI.getOperand(2).getReg(), MRI, *TRI);
2861 OpdsMapping[3] = getVGPROpMapping(MI.getOperand(3).getReg(), MRI, *TRI);
2862 OpdsMapping[4] = getVGPROpMapping(MI.getOperand(4).getReg(), MRI, *TRI);
2863 OpdsMapping[5] = getSGPROpMapping(MI.getOperand(5).getReg(), MRI, *TRI);
2867 unsigned Size = getSizeInBits(MI.getOperand(1).getReg(), MRI, *TRI);
2878 unsigned Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI,
2887 unsigned Bank = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
2907 unsigned Size = MRI.getType(MI.getOperand(0).getReg()).getSizeInBits();
2908 unsigned Op2Bank = getRegBankID(MI.getOperand(2).getReg(), MRI, *TRI,
2910 unsigned Op3Bank = getRegBankID(MI.getOperand(3).getReg(), MRI, *TRI,
2917 unsigned CondBank = getRegBankID(MI.getOperand(1).getReg(), MRI, *TRI,
2965 unsigned Bank = getRegBankID(MI.getOperand(0).getReg(), MRI, *TRI,
2967 assert(MRI.getType(MI.getOperand(0).getReg()).getSizeInBits() == 1);
lib/Target/AMDGPU/AMDILCFGStructurizer.cpp 497 MIB.addReg(OldMI->getOperand(1).getReg(), false);
lib/Target/AMDGPU/GCNDPPCombine.cpp 356 auto DPPMovReg = DstOpnd->getReg();
382 if (OldOpnd->getReg().isPhysical() || SrcOpnd->getReg().isPhysical()) {
382 if (OldOpnd->getReg().isPhysical() || SrcOpnd->getReg().isPhysical()) {
459 Register FwdReg = OrigMI.getOperand(0).getReg();
470 if (OrigMI.getOperand(OpNo).getReg() == DPPMovReg) {
542 if (MRI->use_nodbg_empty(S.first->getOperand(0).getReg())) {
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 479 addRegUnits(TRI, Set, Op.getReg());
558 SmrdSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn,
571 SmrdSgprWaitStates - getWaitStatesSinceDef(Use.getReg(),
592 if (!Use.isReg() || TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
596 VmemSgprWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardDefFn,
614 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
617 DppVgprWaitStates - getWaitStatesSinceDef(Use.getReg(),
727 if (!TRI->isVGPR(MRI, Def.getReg()))
729 Register Reg = Def.getReg();
733 TRI->regsOverlap(MI->getOperand(DataIdx).getReg(), Reg);
792 if (!LaneSelectOp->isReg() || !TRI->isSGPRReg(MRI, LaneSelectOp->getReg()))
795 Register LaneSelectReg = LaneSelectOp->getReg();
835 if (!Use.isReg() || TRI->isVGPR(MF.getRegInfo(), Use.getReg()))
841 MovFedWaitStates - getWaitStatesSinceDef(Use.getReg(), IsHazardFn,
894 Register Reg = Src0->getReg();
922 MachineOperand *Op = I->findRegisterUseOperand(Def.getReg(), false, TRI);
970 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg()))) {
980 const Register SDSTReg = SDST->getReg();
999 (MI->getOperand(0).getReg() == AMDGPU::SGPR_NULL);
1055 if (MO.isDef() && TRI->isSGPRClass(TRI->getPhysRegClass(MO.getReg())))
1093 I->getOperand(0).getReg() == AMDGPU::SGPR_NULL &&
1115 I->getOperand(0).getReg() == AMDGPU::SGPR_NULL &&
1220 if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg()))
1224 getWaitStatesSinceDef(Use.getReg(), IsVALUFn, MaxWaitStates);
1240 if (!Op.isReg() || !TRI.isAGPR(MF.getRegInfo(), Op.getReg()))
1255 Register Reg = Op.getReg();
1262 Register DstReg = MI->getOperand(0).getReg();
1308 Register DstReg = MI->getOperand(0).getReg();
1334 Register DstReg = MI->getOperand(0).getReg();
1341 Register Reg = TII.getNamedOperand(*MI, AMDGPU::OpName::src2)->getReg();
1377 if (!Op.isReg() || !TRI.isVGPR(MF.getRegInfo(), Op.getReg()))
1380 Register Reg = Op.getReg();
lib/Target/AMDGPU/GCNNSAReassign.cpp 176 Register Reg = Op.getReg();
199 if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg)
206 if (UseInst->isCopy() && UseInst->getOperand(0).getReg() == PhysReg)
279 Register Reg = Op.getReg();
lib/Target/AMDGPU/GCNRegBankReassign.cpp 367 Register R = Op.getReg();
394 OperandMasks.push_back(OperandMask(Op.getReg(), Op.getSubReg(), Mask));
430 if (Def && Def->isCopy() && Def->getOperand(1).getReg() == PhysReg)
437 if (UseInst->isCopy() && UseInst->getOperand(0).getReg() == PhysReg)
lib/Target/AMDGPU/GCNRegPressure.cpp 200 assert(MO.isDef() && MO.isReg() && Register::isVirtualRegister(MO.getReg()));
206 MRI.getMaxLaneMaskForVReg(MO.getReg()) :
213 assert(MO.isUse() && MO.isReg() && Register::isVirtualRegister(MO.getReg()));
218 auto MaxMask = MRI.getMaxLaneMaskForVReg(MO.getReg());
226 return getLiveLaneMask(MO.getReg(), SI, LIS, MRI);
234 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()))
241 auto Reg = MO.getReg();
331 if (!MO.isReg() || !Register::isVirtualRegister(MO.getReg()) || MO.isDead())
334 auto Reg = MO.getReg();
409 Register Reg = MO.getReg();
lib/Target/AMDGPU/R600AsmPrinter.cpp 60 unsigned HWReg = RI->getHWRegIndex(MO.getReg());
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 306 Register Reg = MO.getReg();
315 Register Reg = MO.getReg();
369 if (Src.first->getReg() != R600::ALU_LITERAL_X)
lib/Target/AMDGPU/R600EmitClauseMarkers.cpp 79 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X)
143 if (Consts[i].first->getReg() != R600::ALU_CONST)
174 if (Consts[i].first->getReg() != R600::ALU_CONST)
204 TRI.isPhysRegLiveAcrossClauses(MOI->getReg()))
228 if (UseI->readsRegister(MOI->getReg(), &TRI))
232 if (UseI != Def && UseI->killsRegister(MOI->getReg(), &TRI))
lib/Target/AMDGPU/R600ExpandSpecialInstrs.cpp 102 DstOp.getReg(), R600::OQAP);
110 MI.getOperand(LDSPredSelIdx).getReg());
122 MI.getOperand(0).getReg(), // dst
123 MI.getOperand(1).getReg(), // src0
138 Register DstReg = MI.getOperand(0).getReg();
160 .getReg();
163 .getReg();
209 MI.getOperand(TII->getOperandIdx(MI, R600::OpName::dst)).getReg();
211 MI.getOperand(TII->getOperandIdx(MI, R600::OpName::src0)).getReg();
218 Src1 = MI.getOperand(Src1Idx).getReg();
lib/Target/AMDGPU/R600ISelLowering.cpp 307 if (!MRI.use_empty(MI.getOperand(DstIdx).getReg()) ||
323 *BB, I, R600::MOV, MI.getOperand(0).getReg(),
324 MI.getOperand(1).getReg());
331 *BB, I, R600::MOV, MI.getOperand(0).getReg(),
332 MI.getOperand(1).getReg());
338 Register maskedRegister = MI.getOperand(0).getReg();
346 TII->buildMovImm(*BB, I, MI.getOperand(0).getReg(), MI.getOperand(1)
354 TII->buildMovImm(*BB, I, MI.getOperand(0).getReg(),
361 *BB, MI, R600::MOV, MI.getOperand(0).getReg(), R600::ALU_LITERAL_X);
370 *BB, MI, R600::MOV, MI.getOperand(0).getReg(), R600::ALU_CONST);
lib/Target/AMDGPU/R600InstrInfo.cpp 100 if (I->isReg() && !Register::isVirtualRegister(I->getReg()) && I->isUse() &&
101 RI.isPhysRegLiveAcrossClauses(I->getReg()))
245 if (!I->isReg() || !I->isUse() || Register::isVirtualRegister(I->getReg()))
248 if (R600::R600_LDS_SRC_REGRegClass.contains(I->getReg()))
296 Register Reg = MO.getReg();
319 Register Reg = MO.getReg();
350 Register Reg = Src.first->getReg();
618 if (Src.first->getReg() == R600::ALU_LITERAL_X)
622 if (Src.first->getReg() == R600::ALU_CONST)
624 if (R600::R600_KC0RegClass.contains(Src.first->getReg()) ||
625 R600::R600_KC1RegClass.contains(Src.first->getReg())) {
626 unsigned Index = RI.getEncodingValue(Src.first->getReg()) & 0xff;
627 unsigned Chan = RI.getHWRegChan(Src.first->getReg());
867 Register Reg = MI.getOperand(idx).getReg();
953 switch (MO2.getReg()) {
982 .setReg(Pred[2].getReg());
984 .setReg(Pred[2].getReg());
986 .setReg(Pred[2].getReg());
988 .setReg(Pred[2].getReg());
996 PMO.setReg(Pred[2].getReg());
1040 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg();
1042 buildMovInstr(MBB, MI, MI.getOperand(DstOpIdx).getReg(),
1045 buildIndirectRead(MBB, MI, MI.getOperand(DstOpIdx).getReg(), Address,
1054 Register OffsetReg = MI.getOperand(OffsetOpIdx).getReg();
1057 MI.getOperand(ValOpIdx).getReg());
1059 buildIndirectWrite(MBB, MI, MI.getOperand(ValOpIdx).getReg(),
1072 buildIndirectRead(MI.getParent(), MI, MI.getOperand(0).getReg(),
1073 RI.getHWRegIndex(MI.getOperand(1).getReg()), // Address
1074 MI.getOperand(2).getReg(),
1075 RI.getHWRegChan(MI.getOperand(1).getReg()));
1079 buildIndirectWrite(MI.getParent(), MI, MI.getOperand(2).getReg(), // Value
1080 RI.getHWRegIndex(MI.getOperand(1).getReg()), // Address
1081 MI.getOperand(3).getReg(), // Offset
1082 RI.getHWRegChan(MI.getOperand(1).getReg())); // Channel
1331 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
1331 MBB, I, Opcode, DstReg, Src0.getReg(), Src1.getReg());
1352 .setReg(MO.getReg());
lib/Target/AMDGPU/R600MachineScheduler.cpp 164 if (MO.isReg() && MO.getReg() == R600::ALU_LITERAL_X)
186 return !Register::isVirtualRegister(MI->getOperand(1).getReg());
273 Register DestReg = MI->getOperand(0).getReg();
360 Register DestReg = MI->getOperand(DstIndex).getReg();
367 MO.getReg() == DestReg)
lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp 80 if (isImplicitlyDef(MRI, MO.getReg()))
83 RegToChan[MO.getReg()] = Chan;
200 Register Reg = RSI->Instr->getOperand(0).getReg();
205 Register SrcVec = BaseRSI->Instr->getOperand(0).getReg();
298 if (PreviousRegSeqByReg[MOp->getReg()].empty())
300 for (MachineInstr *MI : PreviousRegSeqByReg[MOp->getReg()]) {
353 Register Reg = MI.getOperand(1).getReg();
366 Register Reg = MI.getOperand(0).getReg();
lib/Target/AMDGPU/R600Packetizer.cpp 63 return TRI.getHWRegChan(MI.getOperand(0).getReg());
93 Register Dst = BI->getOperand(DstIdx).getReg();
139 Register Src = MI.getOperand(OperandIdx).getReg();
189 Register PredI = (OpI > -1)?MII->getOperand(OpI).getReg() : Register(),
190 PredJ = (OpJ > -1)?MIJ->getOperand(OpJ).getReg() : Register();
201 if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
201 if (MII->getOperand(0).getReg() != MIJ->getOperand(0).getReg())
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 157 !Register::isVirtualRegister(MI.getOperand(i).getReg()))
160 if (TRI->hasVectorRegisters(MRI.getRegClass(MI.getOperand(i).getReg())))
170 Register DstReg = Copy.getOperand(0).getReg();
171 Register SrcReg = Copy.getOperand(1).getReg();
206 Register DstReg = MI.getOperand(0).getReg();
207 Register SrcReg = Src.getReg();
245 Register DstReg = MI.getOperand(0).getReg();
257 if (Register::isPhysicalRegister(CopyUse.getOperand(0).getReg()))
284 MI.getOperand(0).setReg(CopyUse.getOperand(0).getReg());
288 Register SrcReg = MI.getOperand(I).getReg();
439 if ((MO.isReg() && ((MO.isDef() && MO.getReg() != Reg) || !MO.isDef())) ||
611 Register DstReg = MI.getOperand(0).getReg();
635 Register SrcReg = MI.getOperand(1).getReg();
676 DstRC = MRI->getRegClass(MI.getOperand(0).getReg());
677 Src0RC = MRI->getRegClass(MI.getOperand(1).getReg());
678 Src1RC = MRI->getRegClass(MI.getOperand(2).getReg());
707 if ((Src0.isReg() && TRI->isSGPRReg(*MRI, Src0.getReg()) &&
708 Src0.getReg() != AMDGPU::M0) &&
709 (Src1.isReg() && TRI->isSGPRReg(*MRI, Src1.getReg()) &&
710 Src1.getReg() != AMDGPU::M0)) {
718 if (Register::isVirtualRegister(MO->getReg())) {
719 MachineInstr *DefMI = MRI->getVRegDef(MO->getReg());
723 MO->getReg() == Def.getReg() &&
723 MO->getReg() == Def.getReg() &&
767 unsigned Reg = Instr->getOperand(0).getReg();
771 TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg())) ||
772 TRI->isAGPR(*MRI, Use.getReg());
775 UseMI->getOperand(0).getReg().isPhysical() &&
776 !TRI->isSGPRReg(*MRI, UseMI->getOperand(0).getReg())) {
786 const TargetRegisterClass *UseRC = MRI->getRegClass(Use.getReg());
787 if (!TRI->isSGPRReg(*MRI, Use.getReg()) &&
802 Register PHIRes = MI.getOperand(0).getReg();
811 unsigned InputReg = MI.getOperand(i).getReg();
815 unsigned SrcReg = Def->getOperand(1).getReg();
825 TRI->isVectorRegister(*MRI, Def->getOperand(1).getReg())) {
lib/Target/AMDGPU/SIFixupVectorISel.cpp 94 if (!WOp->isReg() || !Register::isVirtualRegister(WOp->getReg()))
96 MachineInstr *DefInst = MRI.getUniqueVRegDef(WOp->getReg());
115 BaseReg = DefInst->getOperand(2).getReg();
118 IndexReg = DefInst->getOperand(3).getReg();
127 IdxRC = MRI.getRegClass(MI->getOperand(1).getReg());
130 IndexReg = MI->getOperand(1).getReg();
136 BaseReg = MI->getOperand(1).getReg();
lib/Target/AMDGPU/SIFoldOperands.cpp 255 bool HaveNonDbgCarryUse = !MRI.use_nodbg_empty(Dst1.getReg());
257 const TargetRegisterClass *Dst0RC = MRI.getRegClass(Dst0.getReg());
263 BuildMI(*MBB, MI, MI->getDebugLoc(), TII.get(AMDGPU::COPY), Dst1.getReg())
302 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI);
411 !TII->getRegisterInfo().isVGPR(MRI, OtherOp.getReg()))
460 for (MachineInstr *SubDef = MRI.getUniqueVRegDef(Sub->getReg());
463 SubDef = MRI.getUniqueVRegDef(Sub->getReg())) {
505 Register UseReg = OpToFold.getReg();
562 Register RegSeqDstReg = UseMI->getOperand(0).getReg();
594 if (!SOff->isReg() || (SOff->getReg() != MFI->getScratchWaveOffsetReg() &&
595 SOff->getReg() != MFI->getStackPtrOffsetReg()))
598 if (TII->getNamedOperand(*UseMI, AMDGPU::OpName::srsrc)->getReg() !=
613 Register DestReg = UseMI->getOperand(0).getReg();
623 Register SrcReg = UseMI->getOperand(1).getReg();
670 UseMI->getOperand(0).getReg().isVirtual() &&
675 Register UseReg = OpToFold.getReg();
687 if (Size > 4 && TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg()) &&
711 } else if (Def->isReg() && TRI->isAGPR(*MRI, Def->getReg())) {
763 if (TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg()) &&
764 TRI->isVGPR(*MRI, UseMI->getOperand(1).getReg()))
766 else if (TRI->isVGPR(*MRI, UseMI->getOperand(0).getReg()) &&
767 TRI->isAGPR(*MRI, UseMI->getOperand(1).getReg()))
783 UseMI->getOperand(UseOpIdx).getReg(),
800 if (OpToFold.isReg() && TRI->isSGPRReg(*MRI, OpToFold.getReg())) {
802 UseMI->getOperand(UseOpIdx).getReg(),
812 UseMI->getOperand(1).setReg(OpToFold.getReg());
846 Register UseReg = UseOp.getReg();
948 !Register::isVirtualRegister(Op.getReg()))
951 MachineInstr *Def = MRI.getVRegDef(Op.getReg());
1010 bool IsSGPR = TRI.isSGPRReg(MRI, MI->getOperand(0).getReg());
1130 Use = MRI->use_begin(Dst.getReg()), E = MRI->use_end();
1152 NextUse = MRI->use_begin(Dst.getReg());
1193 Use = MRI->use_begin(Dst.getReg()), E = MRI->use_end();
1211 if (Fold.isReg() && Register::isVirtualRegister(Fold.OpToFold->getReg())) {
1212 Register Reg = Fold.OpToFold->getReg();
1225 MRI->clearKillFlags(Fold.OpToFold->getReg());
1254 Src0->getReg() != Src1->getReg() ||
1254 Src0->getReg() != Src1->getReg() ||
1297 if (!ClampSrc || !hasOneNonDBGUseInst(*MRI, ClampSrc->getReg()))
1300 MachineInstr *Def = MRI->getVRegDef(ClampSrc->getReg());
1315 MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());
1315 MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());
1399 if (Src0->isReg() && Src1->isReg() && Src0->getReg() == Src1->getReg() &&
1399 if (Src0->isReg() && Src1->isReg() && Src0->getReg() == Src1->getReg() &&
1421 !hasOneNonDBGUseInst(*MRI, RegOp->getReg()))
1424 MachineInstr *Def = MRI->getVRegDef(RegOp->getReg());
1437 MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());
1437 MRI->replaceRegWith(MI.getOperand(0).getReg(), Def->getOperand(0).getReg());
1485 if (MI.getOperand(0).getReg() == AMDGPU::M0) {
1493 CurrentKnownM0Val = (NewM0Val.isReg() && NewM0Val.getReg().isPhysical()) ?
1506 if (OpToFold.isReg() && !Register::isVirtualRegister(OpToFold.getReg()))
1516 if (Dst.isReg() && !Register::isVirtualRegister(Dst.getReg()))
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 123 Register ResReg = ResMO.getReg();
127 if (MO.getReg() == ResReg)
147 if (Register::isPhysicalRegister(MO.getReg()) && MO.isRenamable())
219 Register Reg = MO.getReg();
268 Register Reg = MO.getReg();
lib/Target/AMDGPU/SIISelLowering.cpp 3203 .addReg(IdxReg.getReg(), getUndefRegState(IdxReg.isUndef()));
3208 .addReg(IdxReg.getReg(), 0, IdxReg.getSubReg());
3286 Register DstReg = MI.getOperand(0).getReg();
3343 const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
3345 assert(Idx->getReg() != AMDGPU::NoRegister);
3397 Register Dst = MI.getOperand(0).getReg();
3398 Register SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg();
3488 Register Dst = MI.getOperand(0).getReg();
3493 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
3496 assert(Val->getReg());
3500 SrcVec->getReg(),
3504 if (Idx->getReg() == AMDGPU::NoRegister) {
3525 .addReg(SrcVec->getReg(), RegState::Undef, SubReg) // vdst
3528 .addReg(SrcVec->getReg(), RegState::Implicit)
3537 .addReg(SrcVec->getReg())
3547 MRI.clearKillFlags(Val->getReg());
3553 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg,
3637 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
3678 Register InputReg = MI.getOperand(0).getReg();
3685 I->getOperand(0).getReg() != InputReg)
3753 Register Dst = MI.getOperand(0).getReg();
3754 Register Src0 = MI.getOperand(1).getReg();
3755 Register Src1 = MI.getOperand(2).getReg();
3757 Register SrcCond = MI.getOperand(3).getReg();
3838 auto I = BuildMI(*BB, MI, DL, TII->get(Opc), MI.getOperand(0).getReg());
10409 !Register::isVirtualRegister(Op.getReg()) ||
10410 !TRI->isAGPR(MRI, Op.getReg()))
10412 auto *Src = MRI.getUniqueVRegDef(Op.getReg());
10414 !TRI->isSGPRReg(MRI, Src->getOperand(1).getReg()))
10416 auto *RC = TRI->getRegClassForReg(MRI, Op.getReg());
10421 MRI.setRegClass(Op.getReg(), NewRC);
10447 Register Def = MI.getOperand(0).getReg();
lib/Target/AMDGPU/SIInsertSkips.cpp 254 MI.getOperand(0).getReg())) {
373 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) {
373 if (Op1.getReg() != ExecReg && Op2.isReg() && Op2.getReg() == ExecReg) {
377 if (Op1.getReg() != ExecReg)
384 SReg = Op2.getReg();
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 465 if (!Op.isReg() || !TRI->isInAllocatableClass(Op.getReg()) ||
466 (Def && !Op.isDef()) || TRI->isAGPR(*MRI, Op.getReg()))
476 unsigned Reg = TRI->getEncodingValue(Op.getReg());
478 if (TRI->isVGPR(MRIA, Op.getReg())) {
482 } else if (TRI->isSGPRReg(MRIA, Op.getReg())) {
509 assert(TRI->isVGPR(*MRI, Opnd.getReg()));
573 if (Op.isReg() && !Op.isDef() && TRI->isVGPR(MRIA, Op.getReg())) {
621 TRI->isVGPR(MRIA, DefMO.getReg())) {
622 setRegScore(TRI->getEncodingValue(DefMO.getReg()), EXP_CNT,
629 if (MO.isReg() && !MO.isDef() && TRI->isVGPR(MRIA, MO.getReg())) {
993 if (TRI->isVGPR(MRIA, Op.getReg())) {
1029 if (TRI->isVGPR(MRIA, Def.getReg())) {
1080 assert(II->getOperand(0).getReg() == AMDGPU::SGPR_NULL);
1128 assert(II->getOperand(0).getReg() == AMDGPU::SGPR_NULL);
1383 Inst.getOperand(0).getReg() == AMDGPU::SGPR_NULL)) {
lib/Target/AMDGPU/SIInstrInfo.cpp 331 if (RSrc->getReg() != MFI->getScratchRSrcReg())
478 const Register Reg = FirstDst->getReg();
630 if (I->modifiesRegister(DefOp.getReg(), &RI))
1419 Register Dst = MI.getOperand(0).getReg();
1437 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
1440 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
1455 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())
1468 MI.getOperand(0).getReg())
1482 Register VecReg = MI.getOperand(0).getReg();
1485 assert(VecReg == MI.getOperand(1).getReg());
1505 Register Reg = MI.getOperand(0).getReg();
1571 Register Dst = MI.getOperand(0).getReg();
1595 Register Src = SrcOp.getReg();
1612 .addReg(Split[0]->getOperand(0).getReg())
1614 .addReg(Split[1]->getOperand(0).getReg())
1645 Register Reg = RegOp.getReg();
2333 bool isVGPRCopy = RI.isVGPR(*MRI, UseMI.getOperand(0).getReg());
2335 if (RI.isAGPR(*MRI, UseMI.getOperand(0).getReg())) {
2373 if (Src0->isReg() && Src0->getReg() == Reg) {
2374 if (!Src1->isReg() || RI.isSGPRClass(MRI->getRegClass(Src1->getReg())))
2377 if (!Src2->isReg() || RI.isSGPRClass(MRI->getRegClass(Src2->getReg())))
2399 Register Src1Reg = Src1->getReg();
2425 if (Src2->isReg() && Src2->getReg() == Reg) {
2433 MachineInstr *Def = MRI->getUniqueVRegDef(Src0->getReg());
2436 MRI->hasOneUse(Src0->getReg())) {
2439 } else if ((Register::isPhysicalRegister(Src0->getReg()) &&
2441 RI.isSGPRClass(RI.getPhysRegClass(Src0->getReg())))) ||
2442 (Register::isVirtualRegister(Src0->getReg()) &&
2444 RI.isSGPRClass(MRI->getRegClass(Src0->getReg())))))
2451 MachineInstr *Def = MRI->getUniqueVRegDef(Src1->getReg());
2454 MRI->hasOneUse(Src1->getReg()) &&
2457 } else if ((Register::isPhysicalRegister(Src1->getReg()) &&
2458 RI.isSGPRClass(RI.getPhysRegClass(Src1->getReg()))) ||
2459 (Register::isVirtualRegister(Src1->getReg()) &&
2460 RI.isSGPRClass(MRI->getRegClass(Src1->getReg()))))
2598 auto Def = MRI.getUniqueVRegDef(MO->getReg());
2657 !RI.isSGPRReg(MBB->getParent()->getRegInfo(), Src0->getReg()))) {
2792 if (!RI.isSGPRReg(MRI, MI.getOperand(0).getReg()))
2916 return Op0.getReg() == Op1.getReg();
2916 return Op0.getReg() == Op1.getReg();
3006 if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()))
3015 if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) ||
3026 if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) ||
3050 if (Use.isUse() && Use.getReg() == AMDGPU::VCC) {
3071 assert(((MI.getOperand(0).getReg() == AMDGPU::VCC) ||
3072 (MI.getOperand(0).getReg() == AMDGPU::VCC_LO)) &&
3114 if (Register::isVirtualRegister(MO.getReg()))
3115 return RI.isSGPRClass(MRI.getRegClass(MO.getReg()));
3118 if (MO.getReg() == AMDGPU::SGPR_NULL)
3123 return MO.getReg() == AMDGPU::M0 ||
3124 MO.getReg() == AMDGPU::VCC ||
3125 MO.getReg() == AMDGPU::VCC_LO;
3127 return AMDGPU::SReg_32RegClass.contains(MO.getReg()) ||
3128 AMDGPU::SReg_64RegClass.contains(MO.getReg());
3138 switch (MO.getReg()) {
3144 return MO.getReg();
3183 if (Register::isPhysicalRegister(SubReg.getReg()))
3184 return TRI.isSubRegister(SuperVec.getReg(), SubReg.getReg());
3184 return TRI.isSubRegister(SuperVec.getReg(), SubReg.getReg());
3187 SubReg.getReg() == SuperVec.getReg();
3187 SubReg.getReg() == SuperVec.getReg();
3223 Register Reg = Op.getReg();
3288 Register Reg = MI.getOperand(i).getReg();
3318 if (!MO.isReg() || !RI.hasVGPRs(RI.getRegClassForReg(MRI, MO.getReg()))) {
3346 if (!Dst.isReg() || Dst.getReg() != AMDGPU::VCC) {
3382 } else if (Register::isPhysicalRegister(TiedMO.getReg()) &&
3383 Dst.getReg() != TiedMO.getReg()) {
3383 Dst.getReg() != TiedMO.getReg()) {
3453 SGPRUsed = MO.getReg();
3500 if (MO.isReg() && MO.getReg() != AMDGPU::M0) {
3501 if (MO.getReg() != SGPRUsed)
3503 SGPRUsed = MO.getReg();
3627 if (Soff && Soff->getReg() != AMDGPU::M0) {
3740 RI.isAGPR(MRI, MI.getOperand(0).getReg()) ?
3813 Register Reg = MI.getOperand(OpNo).getReg();
3865 .addReg(SuperReg.getReg(), 0, SubIdx);
3876 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
3919 Register Reg = MO.getReg();
3969 SGPRsUsed.insert(RegSubRegPair(MO->getReg(), MO->getSubReg()));
3976 RegSubRegPair SGPR(Op.getReg(), Op.getSubReg());
4027 Src0.isReg() && (RI.isSGPRReg(MRI, Src0.getReg()) ||
4036 if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) {
4042 if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) {
4053 if (Src0.isReg() && RI.isAGPR(MRI, Src0.getReg()))
4056 if (Src1.isReg() && RI.isAGPR(MRI, Src1.getReg()))
4068 RI.isVGPR(MRI, Src1.getReg())) {
4105 Register Src0Reg = Src0.getReg();
4112 Src0.ChangeToRegister(Src1.getReg(), false, false, Src1.isKill());
4140 if (Src1.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src1.getReg()))) {
4146 if (Src2.isReg() && !RI.isSGPRClass(MRI.getRegClass(Src2.getReg()))) {
4186 if (RI.hasAGPRs(MRI.getRegClass(MO.getReg())) &&
4192 if (!RI.isSGPRClass(MRI.getRegClass(MO.getReg())))
4197 if (SGPRsUsed.count(MO.getReg()))
4200 SGPRsUsed.insert(MO.getReg());
4261 if (SBase && !RI.isSGPRClass(MRI.getRegClass(SBase->getReg()))) {
4262 unsigned SGPR = readlaneVGPRToSGPR(SBase->getReg(), MI, MRI);
4266 if (SOff && !RI.isSGPRClass(MRI.getRegClass(SOff->getReg()))) {
4267 unsigned SGPR = readlaneVGPRToSGPR(SOff->getReg(), MI, MRI);
4278 Register OpReg = Op.getReg();
4305 if (Def->getOperand(1).getReg().isPhysical())
4307 Def = MRI.getUniqueVRegDef(Def->getOperand(1).getReg());
4336 Register VRsrc = Rsrc.getReg();
4424 MRI.clearKillFlags(MO.getReg());
4543 !Register::isVirtualRegister(MI.getOperand(i).getReg()))
4546 MRI.getRegClass(MI.getOperand(i).getReg());
4579 if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg()))
4604 if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg()))
4607 const TargetRegisterClass *OpRC = MRI.getRegClass(Op.getReg());
4623 Register Dst = MI.getOperand(0).getReg();
4624 Register Src0 = MI.getOperand(1).getReg();
4638 if (Src.isReg() && RI.hasVectorRegisters(MRI.getRegClass(Src.getReg())))
4639 Src.setReg(readlaneVGPRToSGPR(Src.getReg(), MI, MRI));
4652 if (SRsrc && !RI.isSGPRClass(MRI.getRegClass(SRsrc->getReg()))) {
4653 unsigned SGPR = readlaneVGPRToSGPR(SRsrc->getReg(), MI, MRI);
4658 if (SSamp && !RI.isSGPRClass(MRI.getRegClass(SSamp->getReg()))) {
4659 unsigned SGPR = readlaneVGPRToSGPR(SSamp->getReg(), MI, MRI);
4672 if (RI.getCommonSubClass(MRI.getRegClass(Rsrc->getReg()),
4714 .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
4721 .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
5014 if (Op.isReg() && Op.getReg() == AMDGPU::SCC) {
5056 Register DstReg = Inst.getOperand(0).getReg();
5066 Register::isVirtualRegister(Inst.getOperand(1).getReg()) &&
5067 NewDstRC == RI.getRegClassForReg(MRI, Inst.getOperand(1).getReg())) {
5075 MRI.replaceRegWith(DstReg, Inst.getOperand(1).getReg());
5076 MRI.clearKillFlags(Inst.getOperand(1).getReg());
5111 Register OldDstReg = Inst.getOperand(0).getReg();
5120 assert(Inst.getOperand(3).getReg() == AMDGPU::SCC);
5153 .addReg(Src.getReg());
5156 .addReg(Src.getReg())
5159 MRI.replaceRegWith(Dest.getReg(), ResultReg);
5183 MRI.replaceRegWith(Dest.getReg(), NewDest);
5191 RI.isSGPRClass(MRI.getRegClass(Src0.getReg()));
5193 RI.isSGPRClass(MRI.getRegClass(Src1.getReg()));
5220 MRI.replaceRegWith(Dest.getReg(), NewDest);
5253 MRI.replaceRegWith(Dest.getReg(), NewDest);
5282 MRI.replaceRegWith(Dest.getReg(), NewDest);
5300 MRI.getRegClass(Src0.getReg()) :
5308 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5328 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
5362 const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
5363 const TargetRegisterClass *Src1RC = MRI.getRegClass(Src1.getReg());
5401 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
5427 MRI.getRegClass(Src0.getReg()) :
5432 MRI.getRegClass(Src1.getReg()) :
5446 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5467 MRI.replaceRegWith(Dest.getReg(), FullDestReg);
5489 const TargetRegisterClass *DestRC = MRI.getRegClass(Dest.getReg());
5496 if (Src0.isReg() && RI.isSGPRReg(MRI, Src0.getReg())) {
5513 MRI.replaceRegWith(Dest.getReg(), NewDest);
5531 MRI.getRegClass(Src.getReg()) :
5548 MRI.replaceRegWith(Dest.getReg(), ResultReg);
5579 .addReg(Inst.getOperand(1).getReg(), 0, AMDGPU::sub0)
5593 MRI.replaceRegWith(Dest.getReg(), ResultReg);
5604 .addReg(Src.getReg(), 0, AMDGPU::sub0);
5607 .addReg(Src.getReg(), 0, AMDGPU::sub0)
5612 MRI.replaceRegWith(Dest.getReg(), ResultReg);
5710 MRI.replaceRegWith(Dest.getReg(), ResultReg);
5718 assert(Op.isReg() && Op.getReg() == AMDGPU::SCC && Op.isDef() &&
5817 return MO.getReg();
5820 Register Reg = MO.getReg();
5929 return getNamedOperand(MI, AMDGPU::OpName::vdata)->getReg();
5937 return getNamedOperand(MI, AMDGPU::OpName::data)->getReg();
6251 if (Op.isReg() && Op.getReg() == AMDGPU::VCC)
6430 if (Op1.isReg() && Register::isVirtualRegister(Op1.getReg())) {
lib/Target/AMDGPU/SIInstrInfo.h 672 unsigned Dest = MI.getOperand(0).getReg();
683 return MO.isReg() && RI.isVGPR(MRI, MO.getReg());});
823 getRegClass(MO.getReg()), SubReg)) >= 32 &&
1047 return TargetInstrInfo::RegSubRegPair(O.getReg(), O.getSubReg());
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 151 if (AddrReg[i]->getReg() != AddrRegNext.getReg() ||
151 if (AddrReg[i]->getReg() != AddrRegNext.getReg() ||
173 if (Register::isPhysicalRegister(AddrOp->getReg()))
178 if (MRI.hasOneNonDBGUse(AddrOp->getReg()))
565 RegDefs.insert(Op.getReg());
566 else if (Op.readsReg() && Register::isPhysicalRegister(Op.getReg()))
567 PhysRegUses.insert(Op.getReg());
596 ((Use.readsReg() && RegDefs.count(Use.getReg())) ||
597 (Use.isDef() && RegDefs.count(Use.getReg())) ||
598 (Use.isDef() && Register::isPhysicalRegister(Use.getReg()) &&
599 PhysRegUses.count(Use.getReg())))) {
907 Register BaseReg = AddrReg->getReg();
920 .addReg(AddrReg->getReg(), 0, BaseSubReg)
1000 Register BaseReg = AddrReg->getReg();
1013 .addReg(AddrReg->getReg(), 0, BaseSubReg)
1444 MachineInstr *Def = MRI->getUniqueVRegDef(Op.getReg());
1467 MachineInstr *Def = MRI->getUniqueVRegDef(Base.getReg());
1477 MachineInstr *BaseLoDef = MRI->getUniqueVRegDef(BaseLo.getReg());
1478 MachineInstr *BaseHiDef = MRI->getUniqueVRegDef(BaseHi.getReg());
1508 Addr.Base.LoReg = BaseLo.getReg();
1509 Addr.Base.HiReg = BaseHi.getReg();
lib/Target/AMDGPU/SILowerControlFlow.cpp 140 assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
149 Register SaveExecReg = MI.getOperand(0).getReg();
185 Register SaveExecReg = SaveExec.getReg();
191 J->getOperand(1).isReg() && J->getOperand(1).getReg() == SaveExecReg) {
192 SaveExecReg = J->getOperand(0).getReg();
207 assert(ImpDefSCC.getReg() == AMDGPU::SCC && ImpDefSCC.isDef());
365 if (MachineInstr *Def = MRI->getUniqueVRegDef(MI.getOperand(1).getReg())) {
419 unsigned CFMask = MI.getOperand(0).getReg();
444 if (!Op.isReg() || !Register::isVirtualRegister(Op.getReg())) {
449 MachineInstr *Def = MRI->getUniqueVRegDef(Op.getReg());
459 !(I->isCopy() && I->getOperand(0).getReg() != Exec))
464 (Register::isVirtualRegister(SrcOp.getReg()) || SrcOp.getReg() == Exec))
464 (Register::isVirtualRegister(SrcOp.getReg()) || SrcOp.getReg() == Exec))
487 Register Reg = MI.getOperand(OpToReplace).getReg();
lib/Target/AMDGPU/SILowerI1Copies.cpp 509 Register DstReg = MI.getOperand(0).getReg();
510 Register SrcReg = MI.getOperand(1).getReg();
554 if (isVreg1(MI.getOperand(0).getReg()))
569 Register DstReg = MI->getOperand(0).getReg();
576 Register IncomingReg = MI->getOperand(i).getReg();
581 IncomingReg = IncomingDef->getOperand(1).getReg();
680 Register DstReg = MI.getOperand(0).getReg();
697 Register SrcReg = MI.getOperand(1).getReg();
744 Reg = MI->getOperand(1).getReg();
775 if (MO.isReg() && MO.getReg() == AMDGPU::SCC) {
lib/Target/AMDGPU/SILowerSGPRSpills.cpp 282 TII->getNamedOperand(MI, AMDGPU::OpName::vdata)->getReg();
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 68 Src.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC))
69 return MI.getOperand(0).getReg();
84 Dst.getReg() == (ST.isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC) &&
86 return MI.getOperand(1).getReg();
110 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC)
111 return MI.getOperand(0).getReg();
113 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC)
114 return MI.getOperand(0).getReg();
126 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO)
127 return MI.getOperand(0).getReg();
129 if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC_LO)
130 return MI.getOperand(0).getReg();
325 Register CopyFromExec = CopyFromExecInst->getOperand(0).getReg();
393 if (Src0.isReg() && Src0.getReg() == CopyFromExec) {
395 } else if (Src1.isReg() && Src1.getReg() == CopyFromExec) {
410 .addReg(OtherOp->getReg());
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 99 if (MI.isCopy() && MI.getOperand(1).getReg() == Exec) {
112 if (Op->isReg() && Op->getReg() != Exec)
113 return Op->getReg();
115 if (Op->isReg() && Op->getReg() != Exec)
116 return Op->getReg();
214 Register CmpReg = AndCC->getReg();
218 CmpReg = AndCC->getReg();
220 } else if (And->getOperand(2).getReg() != ExecReg) {
237 Register SelReg = Op1->getReg();
256 Register CCReg = CC->getReg();
260 And->getOperand(0).getReg())
358 RecalcRegs.insert(Op.getReg());
399 RecalcRegs.insert(Op.getReg());
416 Register SavedExec = SaveExec->getOperand(0).getReg();
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 277 To.setReg(From.getReg());
290 LHS.getReg() == RHS.getReg() &&
290 LHS.getReg() == RHS.getReg() &&
300 for (MachineOperand &UseMO : MRI->use_nodbg_operands(Reg->getReg())) {
321 MachineInstr *DefInstr = MRI->getUniqueVRegDef(Reg->getReg());
326 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg())
326 if (DefMO.isReg() && DefMO.getReg() == Reg->getReg())
454 for (MachineInstr &UseInst : MRI->use_nodbg_instructions(PotentialMO->getReg())) {
500 getMRI()->clearKillFlags(MO.getReg());
510 MIB.addReg(getPreservedOperand()->getReg(),
530 for (const MachineOperand &Def : MRI->def_operands(Op.getReg())) {
577 if (Register::isPhysicalRegister(Src1->getReg()) ||
578 Register::isPhysicalRegister(Dst->getReg()))
616 if (Register::isPhysicalRegister(Src1->getReg()) ||
617 Register::isPhysicalRegister(Dst->getReg()))
680 if (Register::isPhysicalRegister(Src0->getReg()) ||
681 Register::isPhysicalRegister(Dst->getReg()))
709 if (Register::isPhysicalRegister(ValSrc->getReg()) ||
710 Register::isPhysicalRegister(Dst->getReg()))
909 if (!MRI->hasOneUse(CarryIn->getReg()) || !MRI->use_empty(CarryOut->getReg()))
909 if (!MRI->hasOneUse(CarryIn->getReg()) || !MRI->use_empty(CarryOut->getReg()))
957 if (SDst && (SDst->getReg() != AMDGPU::VCC &&
958 SDst->getReg() != AMDGPU::VCC_LO))
1178 if (!Op.isImm() && !(Op.isReg() && !TRI->isVGPR(*MRI, Op.getReg())))
1187 TRI->isSGPRReg(*MRI, Op.getReg())) {
1198 Copy.addReg(Op.getReg(), Op.isKill() ? RegState::Kill : 0,
lib/Target/AMDGPU/SIPreAllocateWWMRegs.cpp 93 Register Reg = MO.getReg();
127 const Register VirtReg = MO.getReg();
lib/Target/AMDGPU/SIRegisterInfo.cpp 401 assert(TII->getNamedOperand(MI, AMDGPU::OpName::soffset)->getReg() ==
591 if (spillVGPRtoAGPR(ST, MI, Index, 0, Reg->getReg(), false).getInstr())
647 hasAGPRs(RC) ? TII->getNamedOperand(*MI, AMDGPU::OpName::tmp)->getReg()
762 Register SuperReg = MI->getOperand(0).getReg();
881 Register SuperReg = MI->getOperand(0).getReg();
939 MIB.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
1043 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() ==
1048 VData->getReg(), VData->isKill(),
1049 TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)->getReg(),
1073 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() ==
1078 VData->getReg(), VData->isKill(),
1079 TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)->getReg(),
1107 MI->getOperand(0).getReg() :
1206 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() ==
1836 const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg());
1838 return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB, MRI);
lib/Target/AMDGPU/SIShrinkInstructions.cpp 80 Register Reg = Src0.getReg();
254 unsigned Vgpr = TRI.getHWRegIndex(Op.getReg());
363 if (Register::isVirtualRegister(Dest->getReg()) && SrcReg->isReg()) {
364 MRI.setRegAllocationHint(Dest->getReg(), 0, SrcReg->getReg());
364 MRI.setRegAllocationHint(Dest->getReg(), 0, SrcReg->getReg());
365 MRI.setRegAllocationHint(SrcReg->getReg(), 0, Dest->getReg());
365 MRI.setRegAllocationHint(SrcReg->getReg(), 0, Dest->getReg());
369 if (SrcReg->isReg() && SrcReg->getReg() == Dest->getReg()) {
369 if (SrcReg->isReg() && SrcReg->getReg() == Dest->getReg()) {
375 MI.getOperand(2).ChangeToRegister(Dest->getReg(), false);
397 Register::isPhysicalRegister(MO.getReg())) {
398 if (TRI.regsOverlap(Reg, MO.getReg()))
400 } else if (MO.getReg() == Reg && Register::isVirtualRegister(Reg)) {
460 Register T = MovT.getOperand(0).getReg();
466 Register X = Xop.getReg();
485 Register Y = MovY.getOperand(0).getReg();
511 I->getOperand(0).getReg() != X ||
580 Register::isPhysicalRegister(MI.getOperand(0).getReg())) {
644 if (Register::isVirtualRegister(Dest->getReg()) && Src0->isReg()) {
645 MRI.setRegAllocationHint(Dest->getReg(), 0, Src0->getReg());
645 MRI.setRegAllocationHint(Dest->getReg(), 0, Src0->getReg());
646 MRI.setRegAllocationHint(Src0->getReg(), 0, Dest->getReg());
646 MRI.setRegAllocationHint(Src0->getReg(), 0, Dest->getReg());
650 if (Src0->isReg() && Src0->getReg() == Dest->getReg()) {
650 if (Src0->isReg() && Src0->getReg() == Dest->getReg()) {
672 if (Src.isImm() && Register::isPhysicalRegister(Dst.getReg())) {
720 Register DstReg = MI.getOperand(0).getReg();
730 MRI.setRegAllocationHint(MI.getOperand(0).getReg(), 0, VCCReg);
744 Register SReg = Src2->getReg();
764 if (SDst->getReg() != VCCReg) {
765 if (Register::isVirtualRegister(SDst->getReg()))
766 MRI.setRegAllocationHint(SDst->getReg(), 0, VCCReg);
772 if (Src2 && Src2->getReg() != VCCReg) {
773 if (Register::isVirtualRegister(Src2->getReg()))
774 MRI.setRegAllocationHint(Src2->getReg(), 0, VCCReg);
lib/Target/AMDGPU/SIWholeQuadMode.cpp 276 Register Reg = Use.getReg();
303 for (MachineInstr &DefMI : MRI->def_instructions(Use.getReg()))
364 Register Reg = Inactive.getReg();
393 Register Reg = MO.getReg();
545 if (TRI->isSGPRReg(*MRI, Op.getReg())) {
843 Register Dest = MI->getOperand(0).getReg();
858 const Register Reg = MI->getOperand(0).getReg();
lib/Target/ARC/ARCBranchFinalize.cpp 120 .addReg(MI->getOperand(1).getReg())
134 .addReg(MI->getOperand(1).getReg())
lib/Target/ARC/ARCExpandPseudos.cpp 66 .addReg(SI.getOperand(1).getReg())
70 .addReg(SI.getOperand(0).getReg())
lib/Target/ARC/ARCInstrInfo.cpp 76 return MI.getOperand(0).getReg();
95 return MI.getOperand(0).getReg();
lib/Target/ARC/ARCMCInstLower.cpp 87 return MCOperand::createReg(MO.getReg());
lib/Target/ARC/ARCOptAddrMode.cpp 183 Register R = Add->getOperand(0).getReg();
207 Register B = Base.getReg();
254 unsigned NewBaseReg = Add.getOperand(0).getReg();
286 Register BaseReg = Ldst->getOperand(BasePos).getReg();
295 Register StReg = Ldst->getOperand(0).getReg();
296 if (Add->getOperand(0).getReg() == StReg || BaseReg == StReg) {
408 MachineInstr *OpDef = MRI->getVRegDef(O.getReg());
425 Register ValReg = IsLoad ? Ldst->getOperand(0).getReg() : Register();
448 Register BaseReg = Ldst.getOperand(BasePos).getReg();
lib/Target/ARC/ARCRegisterInfo.cpp 209 Register Reg = MI.getOperand(0).getReg();
lib/Target/ARM/A15SDOptimizer.cpp 136 Register Reg = MO.getReg();
166 SReg = MI->getOperand(1).getReg();
194 Register Reg = MO.getReg();
216 Register DefReg = MODef.getReg();
244 return optimizeAllLanesPattern(MI, MI->getOperand(1).getReg());
248 Register DPRReg = MI->getOperand(1).getReg();
249 Register SPRReg = MI->getOperand(2).getReg();
252 MachineInstr *DPRMI = MRI->getVRegDef(MI->getOperand(1).getReg());
253 MachineInstr *SPRMI = MRI->getVRegDef(MI->getOperand(2).getReg());
270 Register FullReg = SPRMI->getOperand(1).getReg();
272 MRI->getRegClass(MI->getOperand(1).getReg());
281 return optimizeAllLanesPattern(MI, MI->getOperand(2).getReg());
285 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
299 Register OpReg = MI->getOperand(I).getReg();
310 NonImplicitReg = MI->getOperand(I).getReg();
316 return optimizeAllLanesPattern(MI, MI->getOperand(0).getReg());
345 if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
347 MachineInstr *Def = MRI->getVRegDef(MI->getOperand(1).getReg());
372 Register Reg = MI->getOperand(I).getReg();
382 if (!Register::isVirtualRegister(MI->getOperand(1).getReg()))
384 MachineInstr *NewMI = MRI->getVRegDef(MI->getOperand(1).getReg());
411 Defs.push_back(MO.getReg());
625 Register DPRDefReg = MI->getOperand(0).getReg();
642 MRI->constrainRegClass(NewReg, MRI->getRegClass((*I)->getReg()));
lib/Target/ARM/ARMAsmPrinter.cpp 206 Register Reg = MO.getReg();
278 Register Reg = MI->getOperand(OpNum).getReg();
305 Register RegBegin = MO.getReg();
325 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
382 TRI->getSubReg(MO.getReg(), FirstHalf ? ARM::gsub_0 : ARM::gsub_1);
394 Register Reg = MO.getReg();
403 Register Reg = MI->getOperand(OpNum).getReg();
422 Register Reg = MO.getReg();
449 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
456 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
1087 SrcReg = MI->getOperand(1).getReg();
1088 DstReg = MI->getOperand(0).getReg();
1133 TargetRegInfo->getRegSizeInBits(MO.getReg(), MachineRegInfo) / 8;
1139 Register Reg = MO.getReg();
1148 assert(MI->getOperand(2).getReg() == ARM::SP &&
1279 .addReg(MI->getOperand(0).getReg())
1283 .addReg(MI->getOperand(3).getReg()));
1295 .addReg(MI->getOperand(0).getReg())
1299 .addReg(MI->getOperand(3).getReg()));
1316 .addReg(MI->getOperand(0).getReg()));
1329 Register TReg = MI->getOperand(0).getReg();
1362 .addReg(MI->getOperand(0).getReg())
1396 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1428 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1429 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1470 MCInst.addReg(MI->getOperand(1).getReg());
1500 .addReg(MI->getOperand(3).getReg());
1528 .addReg(MI->getOperand(0).getReg())
1529 .addReg(MI->getOperand(0).getReg())
1549 .addReg(MI->getOperand(0).getReg())
1551 .addReg(MI->getOperand(1).getReg())
1554 .addReg(MI->getOperand(4).getReg())
1593 .addReg(MI->getOperand(0).getReg())
1595 .addReg(MI->getOperand(1).getReg())
1599 .addReg(MI->getOperand(4).getReg()));
1643 .addReg(MI->getOperand(0).getReg())
1655 .addReg(MI->getOperand(0).getReg())
1656 .addReg(MI->getOperand(1).getReg())
1666 Register Base = MI->getOperand(0).getReg();
1667 Register Idx = MI->getOperand(1).getReg();
1755 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1770 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1783 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1784 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1796 .addReg(MI->getOperand(0).getReg())
1797 .addReg(MI->getOperand(1).getReg())
1847 Register SrcReg = MI->getOperand(0).getReg();
1848 Register ValReg = MI->getOperand(1).getReg();
1913 Register SrcReg = MI->getOperand(0).getReg();
1914 Register ValReg = MI->getOperand(1).getReg();
1970 Register SrcReg = MI->getOperand(0).getReg();
1971 Register ScratchReg = MI->getOperand(1).getReg();
2030 Register SrcReg = MI->getOperand(0).getReg();
2031 Register ScratchReg = MI->getOperand(1).getReg();
2098 Register SrcReg = MI->getOperand(0).getReg();
lib/Target/ARM/ARMBaseInstrInfo.cpp 175 Register WBReg = WB.getReg();
176 Register BaseReg = Base.getReg();
177 Register OffReg = Offset.getReg();
242 BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
248 .addReg(MI.getOperand(1).getReg())
258 BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
264 .addReg(MI.getOperand(1).getReg())
279 if (MO.isReg() && Register::isVirtualRegister(MO.getReg())) {
280 Register Reg = MO.getReg();
505 .addReg(Pred[1].getReg());
513 MI.getOperand(PIdx+1).setReg(Pred[1].getReg());
551 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
562 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
570 return Offset.getReg() != 0;
584 return (isSub && Offset.getReg() != 0);
687 if (MO.getReg() != ARM::CPSR)
1008 MI.getOperand(1).getReg() != MI.getOperand(2).getReg()))
1008 MI.getOperand(1).getReg() != MI.getOperand(2).getReg()))
1212 MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1215 return MI.getOperand(0).getReg();
1226 return MI.getOperand(0).getReg();
1241 return MI.getOperand(2).getReg();
1247 return MI.getOperand(0).getReg();
1449 MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1452 return MI.getOperand(0).getReg();
1463 return MI.getOperand(0).getReg();
1484 return MI.getOperand(0).getReg();
1490 return MI.getOperand(0).getReg();
1552 ScratchRegs.push_back(MI->getOperand(I).getReg());
1590 Register DstRegS = MI.getOperand(0).getReg();
1591 Register SrcRegS = MI.getOperand(1).getReg();
1701 MI->substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1801 Register Addr0 = MI0.getOperand(1).getReg();
1802 Register Addr1 = MI1.getOperand(1).getReg();
2133 PredReg = MI.getOperand(PIdx+1).getReg();
2201 if (Register::isPhysicalRegister(MO.getReg()))
2240 MachineInstr *DefMI = canFoldIntoMOVCC(MI.getOperand(2).getReg(), MRI, this);
2243 DefMI = canFoldIntoMOVCC(MI.getOperand(1).getReg(), MRI, this);
2249 Register DestReg = MI.getOperand(0).getReg();
2250 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
2420 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2421 MI->getOperand(1).getReg() == ARM::SP)) &&
2460 TRI->getEncodingValue(MO.getReg()) < FirstRegEnc)
2461 FirstRegEnc = TRI->getEncodingValue(MO.getReg());
2685 SrcReg = MI.getOperand(0).getReg();
2693 SrcReg = MI.getOperand(0).getReg();
2694 SrcReg2 = MI.getOperand(1).getReg();
2700 SrcReg = MI.getOperand(0).getReg();
2721 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2773 ((OI->getOperand(1).getReg() == SrcReg &&
2774 OI->getOperand(2).getReg() == SrcReg2) ||
2775 (OI->getOperand(1).getReg() == SrcReg2 &&
2776 OI->getOperand(2).getReg() == SrcReg))) {
2782 ((OI->getOperand(2).getReg() == SrcReg &&
2783 OI->getOperand(3).getReg() == SrcReg2) ||
2784 (OI->getOperand(2).getReg() == SrcReg2 &&
2785 OI->getOperand(3).getReg() == SrcReg))) {
2792 OI->getOperand(1).getReg() == SrcReg &&
2800 OI->getOperand(2).getReg() == SrcReg &&
2810 OI->getOperand(0).getReg() == SrcReg &&
2811 OI->getOperand(1).getReg() == SrcReg2) {
2819 OI->getOperand(0).getReg() == SrcReg &&
2820 OI->getOperand(2).getReg() == SrcReg2) {
3063 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
3114 (SrcReg2 != 0 && SubAdd->getOperand(OpI).getReg() == SrcReg2 &&
3115 SubAdd->getOperand(OpI + 1).getReg() == SrcReg)) {
3219 if (MO.getReg() == ARM::CPSR && !MO.isDead())
3228 if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR)
3249 Commute = UseMI.getOperand(2).getReg() != Reg;
3315 Register Reg1 = UseMI.getOperand(OpIdx).getReg();
3359 if (!MI.getOperand(2).getReg())
3379 Register Rt = MI.getOperand(0).getReg();
3380 Register Rm = MI.getOperand(3).getReg();
3386 Register Rt = MI.getOperand(0).getReg();
3387 Register Rm = MI.getOperand(3).getReg();
3416 Register Rt = MI.getOperand(0).getReg();
3417 Register Rm = MI.getOperand(3).getReg();
3428 Register Rt = MI.getOperand(0).getReg();
3429 Register Rm = MI.getOperand(3).getReg();
3448 Register Rm = MI.getOperand(3).getReg();
3451 Register Rt = MI.getOperand(0).getReg();
3466 Register Rt = MI.getOperand(0).getReg();
3467 Register Rn = MI.getOperand(2).getReg();
3468 Register Rm = MI.getOperand(3).getReg();
3476 Register Rm = MI.getOperand(3).getReg();
3492 Register Rt = MI.getOperand(0).getReg();
3493 Register Rn = MI.getOperand(3).getReg();
3494 Register Rm = MI.getOperand(4).getReg();
3502 Register Rt = MI.getOperand(0).getReg();
3503 Register Rn = MI.getOperand(3).getReg();
3508 Register Rm = MI.getOperand(4).getReg();
3539 Register Rt = MI.getOperand(0).getReg();
3540 Register Rn = MI.getOperand(2).getReg();
3789 Register BaseReg = MI.getOperand(0).getReg();
3792 if (Op.isReg() && Op.getReg() == BaseReg)
4263 Register Reg = DefMO.getReg();
4739 if (!ARM::hGPRRegClass.contains(MI.getOperand(0).getReg()) &&
4740 !ARM::hGPRRegClass.contains(MI.getOperand(1).getReg())) {
4752 Register Reg = MI.getOperand(i).getReg();
4775 Register Reg = MI->getOperand(0).getReg();
4949 DstReg = MI.getOperand(0).getReg();
4950 SrcReg = MI.getOperand(1).getReg();
4968 DstReg = MI.getOperand(0).getReg();
4969 SrcReg = MI.getOperand(1).getReg();
4995 DstReg = MI.getOperand(0).getReg();
4996 SrcReg = MI.getOperand(1).getReg();
5028 DstReg = MI.getOperand(0).getReg();
5029 SrcReg = MI.getOperand(1).getReg();
5148 Register Reg = MO.getReg();
5203 Register Reg = MO.getReg();
5264 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(),
5269 InputRegs.push_back(RegSubRegPairAndIdx(MOReg->getReg(),
5291 InputReg.Reg = MOReg.getReg();
5313 BaseReg.Reg = MOBaseReg.getReg();
5316 InsertedReg.Reg = MOInsertedReg.getReg();
5381 Register Reg = CmpMI->getOperand(0).getReg();
lib/Target/ARM/ARMBaseInstrInfo.h 456 return MI.getOperand(3).getReg();
lib/Target/ARM/ARMBaseRegisterInfo.cpp 811 Register PredReg = (PIdx == -1) ? Register() : MI.getOperand(PIdx+1).getReg();
lib/Target/ARM/ARMCallLowering.cpp 531 auto CalleeReg = Info.Callee.getReg();
lib/Target/ARM/ARMConstantIslandPass.cpp 1661 Register CCReg = MI->getOperand(2).getReg();
1747 MI->getOperand(2).getReg() == ARM::PC &&
1756 MI->getOperand(2).getReg() == ARM::LR &&
1779 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1786 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1954 Register Reg = Cmp.MI->getOperand(0).getReg();
2007 if (I.getOperand(0).getReg() != EntryReg)
2010 if (I.getOperand(1).getReg() != BaseReg)
2047 Register EntryReg = JumpMI->getOperand(0).getReg();
2048 Register BaseReg = LEAMI->getOperand(0).getReg();
2062 if (!MO.isReg() || !MO.getReg())
2064 if (MO.isDef() && MO.getReg() == BaseReg)
2066 if (MO.isUse() && MO.getReg() == BaseReg) {
2081 if (!MO.isReg() || !MO.getReg())
2083 if (MO.isDef() && MO.getReg() == BaseReg)
2085 if (MO.isUse() && MO.getReg() == EntryReg)
2125 Register EntryReg = JumpMI->getOperand(0).getReg();
2130 if (I->getOpcode() == ARM::t2ADDrs && I->getOperand(0).getReg() == EntryReg)
2142 if (!MO.isReg() || !MO.getReg())
2144 if (MO.isDef() && MO.getReg() == EntryReg)
2146 if (MO.isUse() && MO.getReg() == EntryReg)
2210 IdxReg = MI->getOperand(1).getReg();
2222 Register BaseReg = User.MI->getOperand(0).getReg();
2231 IdxReg = Shift->getOperand(2).getReg();
2232 Register ShiftedIdxReg = Shift->getOperand(0).getReg();
2243 if (Load->getOperand(1).getReg() != BaseReg ||
2244 Load->getOperand(2).getReg() != ShiftedIdxReg ||
2262 Add->getOperand(2).getReg() != BaseReg ||
2263 Add->getOperand(3).getReg() != Load->getOperand(0).getReg() ||
2263 Add->getOperand(3).getReg() != Load->getOperand(0).getReg() ||
2266 if (Add->getOperand(0).getReg() != MI->getOperand(0).getReg())
2266 if (Add->getOperand(0).getReg() != MI->getOperand(0).getReg())
2274 if (Load->getOperand(0).getReg() != MI->getOperand(0).getReg())
2274 if (Load->getOperand(0).getReg() != MI->getOperand(0).getReg())
2297 .addReg(User.MI->getOperand(0).getReg(),
lib/Target/ARM/ARMExpandPseudoInsts.cpp 98 assert(MO.isReg() && MO.getReg());
484 Register DstReg = MI.getOperand(OpIdx++).getReg();
536 assert(AM6Offset.getReg() == 0 &&
617 assert(AM6Offset.getReg() == 0 &&
627 Register SrcReg = MI.getOperand(OpIdx++).getReg();
687 DstReg = MI.getOperand(OpIdx++).getReg();
711 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
763 Register SrcReg = MI.getOperand(OpIdx++).getReg();
832 Register DstReg = MI.getOperand(0).getReg();
936 Register TempReg = MI.getOperand(1).getReg();
940 Register AddrReg = MI.getOperand(2).getReg();
941 Register DesiredReg = MI.getOperand(3).getReg();
942 Register NewReg = MI.getOperand(4).getReg();
968 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg());
976 .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
1039 Register RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
1040 Register RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1);
1044 MIB.addReg(Reg.getReg(), Flags);
1055 Register TempReg = MI.getOperand(1).getReg();
1059 Register AddrReg = MI.getOperand(2).getReg();
1060 Register DesiredReg = MI.getOperand(3).getReg();
1064 Register DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);
1065 Register DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);
1201 .addReg(JumpTarget.getReg(), RegState::Kill);
1220 MI.getOperand(1).getReg())
1233 MI.getOperand(1).getReg())
1245 (MI.getOperand(1).getReg()))
1258 (MI.getOperand(1).getReg()))
1274 MI.getOperand(1).getReg())
1286 MI.getOperand(1).getReg())
1300 MI.getOperand(1).getReg())
1323 MI.getOperand(1).getReg())
1385 MI.getOperand(0).getReg())
1398 MI.getOperand(0).getReg())
1419 Register Reg = MI.getOperand(0).getReg();
1450 Register DstReg = MI.getOperand(0).getReg();
1472 Register DstReg = MI.getOperand(0).getReg();
1530 Register DstReg = MI.getOperand(0).getReg();
1594 Register DstReg = MI.getOperand(OpIdx++).getReg();
1625 Register SrcReg = MI.getOperand(OpIdx++).getReg();
1927 Register Reg = MI.getOperand(0).getReg();
lib/Target/ARM/ARMFastISel.cpp 257 if (MO.getReg() == ARM::CPSR)
2940 Register ResultReg = MI->getOperand(0).getReg();
lib/Target/ARM/ARMFeatures.h 78 return Instr->getOperand(2).getReg() != ARM::PC;
83 return Instr->getOperand(0).getReg() != ARM::PC;
85 return Instr->getOperand(0).getReg() != ARM::PC &&
86 Instr->getOperand(2).getReg() != ARM::PC;
89 return Instr->getOperand(0).getReg() != ARM::PC &&
90 Instr->getOperand(1).getReg() != ARM::PC;
lib/Target/ARM/ARMFrameLowering.cpp 152 if (!isCalleeSavedRegister(MI.getOperand(i).getReg(), CSRegs))
159 isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs) &&
160 MI.getOperand(1).getReg() == ARM::SP)
lib/Target/ARM/ARMHazardRecognizer.cpp 29 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
lib/Target/ARM/ARMISelLowering.cpp 9844 DefRegs[OI->getReg()] = true;
10017 Register dest = MI.getOperand(0).getReg();
10018 Register src = MI.getOperand(1).getReg();
10349 .addReg(MI.getOperand(0).getReg())
10516 .addReg(MI.getOperand(4).getReg());
10530 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), MI.getOperand(0).getReg())
10531 .addReg(MI.getOperand(1).getReg())
10533 .addReg(MI.getOperand(2).getReg())
10549 Register LHS1 = MI.getOperand(1).getReg();
10550 Register LHS2 = MI.getOperand(2).getReg();
10560 Register RHS1 = MI.getOperand(3).getReg();
10561 Register RHS2 = MI.getOperand(4).getReg();
10622 Register ABSSrcReg = MI.getOperand(1).getReg();
10623 Register ABSDstReg = MI.getOperand(0).getReg();
10785 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR) {
10799 assert(!MI.getOperand(ccOutIdx).getReg() &&
lib/Target/ARM/ARMInstrInfo.cpp 120 Register Reg = MI->getOperand(0).getReg();
lib/Target/ARM/ARMInstructionSelector.cpp 213 Register DstReg = I.getOperand(0).getReg();
239 Register VReg0 = MIB->getOperand(0).getReg();
244 Register VReg1 = MIB->getOperand(1).getReg();
249 Register VReg2 = MIB->getOperand(2).getReg();
271 Register VReg0 = MIB->getOperand(0).getReg();
276 Register VReg1 = MIB->getOperand(1).getReg();
281 Register VReg2 = MIB->getOperand(2).getReg();
530 auto ResReg = MIB->getOperand(0).getReg();
542 auto LHSReg = MIB->getOperand(2).getReg();
543 auto RHSReg = MIB->getOperand(3).getReg();
687 auto ResultReg = MIB->getOperand(0).getReg();
773 auto CondReg = MIB->getOperand(1).getReg();
785 auto ResReg = MIB->getOperand(0).getReg();
786 auto TrueReg = MIB->getOperand(2).getReg();
787 auto FalseReg = MIB->getOperand(3).getReg();
864 assert(MRI.getType(I.getOperand(0).getReg()).getSizeInBits() <= 32 &&
867 LLT SrcTy = MRI.getType(I.getOperand(1).getReg());
876 Register SExtResult = I.getOperand(0).getReg();
914 auto SrcReg = I.getOperand(1).getReg();
915 auto DstReg = I.getOperand(0).getReg();
960 if (!MRI.getType(I.getOperand(0).getReg()).isPointer()) {
988 unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits() / 8;
1009 auto SrcReg = I.getOperand(1).getReg();
1010 auto DstReg = I.getOperand(0).getReg();
1041 Register OpReg = I.getOperand(2).getReg();
1084 Register Reg = I.getOperand(0).getReg();
1099 Register OriginalValue = I.getOperand(0).getReg();
1134 if (!validReg(MRI, I.getOperand(0).getReg(), 1, ARM::GPRRegBankID)) {
1142 .addReg(I.getOperand(0).getReg())
1161 Register DstReg = I.getOperand(0).getReg();
lib/Target/ARM/ARMLegalizerInfo.cpp 374 Register OriginalResult = MI.getOperand(0).getReg();
390 {{MI.getOperand(1).getReg(), ArgTy},
391 {MI.getOperand(2).getReg(), ArgTy}});
397 assert(MRI.getType(MI.getOperand(2).getReg()) ==
398 MRI.getType(MI.getOperand(3).getReg()) &&
400 auto OpSize = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
402 auto OriginalResult = MI.getOperand(0).getReg();
426 {{MI.getOperand(2).getReg(), ArgTy},
427 {MI.getOperand(3).getReg(), ArgTy}});
465 MIRBuilder.buildConstant(MI.getOperand(0).getReg(),
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 207 if (MO.isDef() && MO.getReg() == ARM::CPSR && !MO.isDead())
512 Register InstrSrcReg = getLoadStoreRegOp(*MBBI).getReg();
862 Register Reg = MO.getReg();
877 Register DefReg = MO.getReg();
896 Register Base = getLoadStoreBaseOp(*First).getReg();
939 if (!MO.isReg() || MO.getReg() != ImpDefReg)
959 if (UsedRegs.count(MO.getReg()))
988 if (getLoadStoreBaseOp(MI).getReg() == ARM::SP &&
1008 Register PReg = PMO.getReg();
1019 PReg == getLoadStoreBaseOp(*MI).getReg())
1055 Register Reg = MO.getReg();
1198 if (MI.getOperand(0).getReg() != Reg ||
1199 MI.getOperand(1).getReg() != Reg ||
1264 Register Base = BaseOP.getReg();
1274 if (MI->getOperand(i).getReg() == Base)
1302 if (MI->getOperand(i).getReg() >= ARM::R8) {
1390 Register Base = getLoadStoreBaseOp(*MI).getReg();
1405 if (MI->getOperand(0).getReg() == Base)
1445 .addReg(MO.getReg(), (isLd ? getDefRegState(true) :
1452 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1458 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1468 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1484 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
1493 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
1515 Register Base = BaseOp.getReg();
1518 if (Reg0Op.getReg() == Base || Reg1Op.getReg() == Base)
1518 if (Reg0Op.getReg() == Base || Reg1Op.getReg() == Base)
1543 MIB.add(Reg0Op).add(Reg1Op).addReg(BaseOp.getReg(), RegState::Define);
1546 MIB.addReg(BaseOp.getReg(), RegState::Define).add(Reg0Op).add(Reg1Op);
1548 MIB.addReg(BaseOp.getReg(), RegState::Kill)
1658 Register BaseReg = BaseOp.getReg();
1659 Register EvenReg = MI->getOperand(0).getReg();
1660 Register OddReg = MI->getOperand(1).getReg();
1685 assert((isT2 || MI->getOperand(3).getReg() == ARM::NoRegister) &&
1786 Register Reg = MO.getReg();
1787 Register Base = getLoadStoreBaseOp(*MBBI).getReg();
1813 if (TRI->regsOverlap(Reg, E.MI->getOperand(0).getReg())) {
1944 if (MO.getReg() != ARM::LR)
1985 .addReg(Use.getReg(), RegState::Kill)
2124 Register Reg = MO.getReg();
2205 FirstReg = Op0->getOperand(0).getReg();
2206 SecondReg = Op1->getOperand(0).getReg();
2209 BaseReg = Op0->getOperand(1).getReg();
2286 MemRegs.insert(Ops[i]->getOperand(0).getReg());
2418 Register Base = MI.getOperand(1).getReg();
lib/Target/ARM/ARMLowOverheadLoops.cpp 123 if (!MO.isReg() || !MO.isDef() || MO.getReg() != Reg)
136 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg)
151 MI->getOperand(0).getReg() == ARM::LR &&
152 MI->getOperand(1).getReg() == Reg &&
157 unsigned CountReg = Start->getOperand(0).getReg();
190 if (Start->getOperand(0).getReg() == ARM::LR)
295 MO.getReg() == ARM::LR) {
lib/Target/ARM/ARMMCInstLower.cpp 81 MCOp = MCOperand::createReg(MO.getReg());
lib/Target/ARM/ARMRegisterBankInfo.cpp 234 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
269 LLT LargeTy = MRI.getType(MI.getOperand(1).getReg());
279 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
292 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
299 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
313 LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
314 LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
322 LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
323 LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
332 LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
333 LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
346 LLT ToTy = MRI.getType(MI.getOperand(0).getReg());
347 LLT FromTy = MRI.getType(MI.getOperand(1).getReg());
359 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
373 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
375 LLT Ty2 = MRI.getType(MI.getOperand(1).getReg());
387 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
397 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
399 LLT Ty1 = MRI.getType(MI.getOperand(2).getReg());
400 LLT Ty2 = MRI.getType(MI.getOperand(3).getReg());
419 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
420 LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
421 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
434 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
435 LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
436 LLT Ty2 = MRI.getType(MI.getOperand(2).getReg());
456 if (MaybeReg.isReg() && MaybeReg.getReg()) {
457 unsigned Size = MRI.getType(MaybeReg.getReg()).getSizeInBits();
lib/Target/ARM/MLxExpansionPass.cpp 89 Register Reg = MI->getOperand(1).getReg();
99 Reg = DefMI->getOperand(1).getReg();
105 Reg = DefMI->getOperand(2).getReg();
117 Register Reg = MI->getOperand(0).getReg();
127 Reg = UseMI->getOperand(0).getReg();
141 Register Reg = MI->getOperand(1).getReg();
155 Register SrcReg = DefMI->getOperand(i).getReg();
163 Reg = DefMI->getOperand(1).getReg();
169 Reg = DefMI->getOperand(2).getReg();
272 Register DstReg = MI->getOperand(0).getReg();
274 Register AccReg = MI->getOperand(1).getReg();
275 Register Src1Reg = MI->getOperand(2).getReg();
276 Register Src2Reg = MI->getOperand(3).getReg();
282 Register PredReg = MI->getOperand(++NextOp).getReg();
lib/Target/ARM/MVEVPTBlockPass.cpp 159 if (registerDefinedBetween(CmpMI->getOperand(1).getReg(), std::next(CmpMI),
162 if (registerDefinedBetween(CmpMI->getOperand(2).getReg(), std::next(CmpMI),
lib/Target/ARM/Thumb1FrameLowering.cpp 457 isCalleeSavedRegister(MI.getOperand(0).getReg(), CSRegs))
462 Register Dst = MI.getOperand(0).getReg();
463 Register Src = MI.getOperand(1).getReg();
758 MO.getReg() != ARM::PC) {
980 CopyRegs[Op.getReg()] = false;
lib/Target/ARM/Thumb2ITBlockPass.cpp 90 Register Reg = MO.getReg();
117 if (!Uses.count(MO.getReg()))
148 Register DstReg = MI->getOperand(0).getReg();
149 Register SrcReg = MI->getOperand(1).getReg();
173 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR)
lib/Target/ARM/Thumb2InstrInfo.cpp 520 (!HasCCOut || MI.getOperand(MI.getNumOperands()-1).getReg() == 0)) {
555 Register OffsetReg = MI.getOperand(FrameRegIdx + 1).getReg();
726 PredReg = MI.getOperand(PIdx+1).getReg();
lib/Target/ARM/Thumb2SizeReduction.cpp 303 Register Reg = MO.getReg();
312 Register Reg = MO.getReg();
383 Register Reg = MO.getReg();
423 if (MI->getOperand(1).getReg() == ARM::SP) {
467 Register Rt = MI->getOperand(IsStore ? 1 : 0).getReg();
468 Register Rn = MI->getOperand(IsStore ? 0 : 1).getReg();
471 Register PredReg = MI->getOperand(5).getReg();
499 Register BaseReg = MI->getOperand(0).getReg();
506 if (MI->getOperand(i).getReg() == BaseReg) {
527 Register BaseReg = MI->getOperand(1).getReg();
540 Register BaseReg = MI->getOperand(1).getReg();
561 OffsetReg = MI->getOperand(2).getReg();
587 MIB.addReg(MI->getOperand(0).getReg(), RegState::Define | RegState::Dead);
629 if (MI->getOperand(1).getReg() != ARM::SP) {
641 if (!isARMLowRegister(MI->getOperand(0).getReg()))
647 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR)
746 Register Reg0 = MI->getOperand(0).getReg();
747 Register Reg1 = MI->getOperand(1).getReg();
750 Register Reg2 = MI->getOperand(2).getReg();
770 MI->getOperand(CommOpIdx2).getReg() != Reg0)
785 Register Reg2 = MI->getOperand(2).getReg();
808 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
871 Register Reg = MO.getReg();
900 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR);
952 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR)
977 if (MO.getReg() != ARM::CPSR)
992 if (MO.getReg() != ARM::CPSR)
lib/Target/ARM/ThumbRegisterInfo.cpp 375 Register DestReg = MI.getOperand(0).getReg();
513 Register TmpReg = MI.getOperand(0).getReg();
lib/Target/AVR/AVRAsmPrinter.cpp 66 O << AVRInstPrinter::getPrettyRegisterName(MO.getReg(), MRI);
100 Register Reg = RegOp.getReg();
118 Reg = MI->getOperand(OpNum + RegIdx).getReg();
151 if (MI->getOperand(OpNum).getReg() == AVR::R31R30) {
154 assert(MI->getOperand(OpNum).getReg() == AVR::R29R28 &&
lib/Target/AVR/AVRExpandPseudoInsts.cpp 143 Register DstReg = MI.getOperand(0).getReg();
144 Register SrcReg = MI.getOperand(2).getReg();
176 Register DstReg = MI.getOperand(0).getReg();
177 Register SrcReg = MI.getOperand(2).getReg();
223 Register DstReg = MI.getOperand(0).getReg();
275 unsigned DstReg = MI.getOperand(0).getReg();
327 unsigned DstReg = MI.getOperand(0).getReg();
390 unsigned DstReg = MI.getOperand(0).getReg();
420 unsigned DstReg = MI.getOperand(0).getReg();
421 unsigned SrcReg = MI.getOperand(1).getReg();
453 unsigned DstReg = MI.getOperand(0).getReg();
454 unsigned SrcReg = MI.getOperand(1).getReg();
488 unsigned DstReg = MI.getOperand(0).getReg();
537 unsigned DstReg = MI.getOperand(0).getReg();
581 unsigned DstReg = MI.getOperand(0).getReg();
583 unsigned SrcReg = MI.getOperand(1).getReg();
630 unsigned DstReg = MI.getOperand(0).getReg();
631 unsigned SrcReg = MI.getOperand(1).getReg();
661 unsigned DstReg = MI.getOperand(0).getReg();
662 unsigned SrcReg = MI.getOperand(1).getReg();
692 unsigned DstReg = MI.getOperand(0).getReg();
694 unsigned SrcReg = MI.getOperand(1).getReg();
747 unsigned DstReg = MI.getOperand(0).getReg();
749 unsigned SrcReg = MI.getOperand(1).getReg();
876 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
877 !Register::isVirtualRegister(MO.getReg()))
878 Candidates.reset(MO.getReg());
970 unsigned SrcReg = MI.getOperand(1).getReg();
1016 unsigned DstReg = MI.getOperand(0).getReg();
1017 unsigned SrcReg = MI.getOperand(1).getReg();
1044 unsigned DstReg = MI.getOperand(0).getReg();
1045 unsigned SrcReg = MI.getOperand(2).getReg();
1078 unsigned DstReg = MI.getOperand(0).getReg();
1079 unsigned SrcReg = MI.getOperand(2).getReg();
1112 unsigned DstReg = MI.getOperand(0).getReg();
1113 unsigned SrcReg = MI.getOperand(2).getReg();
1147 unsigned DstReg = MI.getOperand(0).getReg();
1177 unsigned SrcReg = MI.getOperand(1).getReg();
1207 unsigned SrcReg = MI.getOperand(0).getReg();
1232 unsigned DstReg = MI.getOperand(0).getReg();
1249 unsigned DstReg = MI.getOperand(0).getReg();
1282 unsigned DstReg = MI.getOperand(0).getReg();
1325 unsigned DstReg = MI.getOperand(0).getReg();
1368 unsigned DstReg = MI.getOperand(0).getReg();
1369 unsigned SrcReg = MI.getOperand(1).getReg();
1422 unsigned DstReg = MI.getOperand(0).getReg();
1423 unsigned SrcReg = MI.getOperand(1).getReg();
1451 unsigned DstReg = MI.getOperand(0).getReg();
1478 unsigned SrcReg = MI.getOperand(1).getReg();
lib/Target/AVR/AVRFrameLowering.cpp 323 assert(MI.getOperand(0).getReg() == AVR::SP &&
327 Register SrcReg = MI.getOperand(2).getReg();
lib/Target/AVR/AVRISelLowering.cpp 1522 Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1523 Register SrcReg = MI.getOperand(1).getReg();
1524 Register DstReg = MI.getOperand(0).getReg();
1571 Register SrcReg = I->getOperand(1).getReg();
1673 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg())
1674 .addReg(MI.getOperand(1).getReg())
1676 .addReg(MI.getOperand(2).getReg())
lib/Target/AVR/AVRInstrInfo.cpp 90 return MI.getOperand(0).getReg();
109 return MI.getOperand(2).getReg();
lib/Target/AVR/AVRMCInstLower.cpp 76 MCOp = MCOperand::createReg(MO.getReg());
lib/Target/AVR/AVRRegisterInfo.cpp 109 if (DstReg != MI.getOperand(0).getReg()) {
161 Register DstReg = MI.getOperand(0).getReg();
lib/Target/AVR/AVRRelaxMemOperations.cpp 100 .addReg(Ptr.getReg());
104 .addReg(Ptr.getReg(), RegState::Define)
105 .addReg(Ptr.getReg())
111 .addReg(Ptr.getReg())
112 .addReg(Src.getReg(), getKillRegState(Src.isKill()));
116 .addReg(Ptr.getReg(), getKillRegState(Ptr.isKill()));
lib/Target/BPF/BPFAsmPrinter.cpp 78 O << BPFInstPrinter::getRegisterName(MO.getReg());
133 O << "(" << BPFInstPrinter::getRegisterName(BaseMO.getReg()) << " - " << -Offset << ")";
135 O << "(" << BPFInstPrinter::getRegisterName(BaseMO.getReg()) << " + " << Offset << ")";
lib/Target/BPF/BPFISelLowering.cpp 701 Register LHS = MI.getOperand(1).getReg();
718 Register RHS = MI.getOperand(2).getReg();
744 BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI.getOperand(0).getReg())
745 .addReg(MI.getOperand(5).getReg())
747 .addReg(MI.getOperand(4).getReg())
lib/Target/BPF/BPFInstrInfo.cpp 46 Register DstReg = MI->getOperand(0).getReg();
47 Register SrcReg = MI->getOperand(1).getReg();
50 Register ScratchReg = MI->getOperand(4).getReg();
lib/Target/BPF/BPFMCInstLower.cpp 62 MCOp = MCOperand::createReg(MO.getReg());
lib/Target/BPF/BPFMIChecking.cpp 118 RegIsGPR64 = GPR64RegClass->contains(MO.getReg());
126 GPR32LiveDefs.push_back(MO.getReg());
133 GPR64DeadDefs.push_back(MO.getReg());
lib/Target/BPF/BPFMIPeephole.cpp 80 MachineInstr *DefInsn = MRI->getVRegDef(MovMI->getOperand(1).getReg());
95 MachineInstr *PhiDef = MRI->getVRegDef(opnd.getReg());
108 Register Reg = opnd.getReg();
138 Register DstReg = MI.getOperand(0).getReg();
139 Register ShfReg = MI.getOperand(1).getReg();
154 MachineInstr *MovMI = MRI->getVRegDef(SllMI->getOperand(1).getReg());
163 Register SubReg = MovMI->getOperand(1).getReg();
261 Register dst = MI.getOperand(0).getReg();
262 Register src = MI.getOperand(1).getReg();
379 SrcReg = MI.getOperand(1).getReg();
381 DstReg = MI.getOperand(0).getReg();
389 SrcReg = MI2->getOperand(1).getReg();
395 SrcReg = MI.getOperand(1).getReg();
396 DstReg = MI.getOperand(0).getReg();
423 MachineInstr *PhiDef = MRI->getVRegDef(opnd.getReg());
lib/Target/BPF/BPFMISimplifyPatchable.cpp 100 Register DstReg = MI.getOperand(0).getReg();
101 Register SrcReg = MI.getOperand(1).getReg();
lib/Target/BPF/BPFRegisterInfo.cpp 89 Register reg = MI.getOperand(i - 1).getReg();
108 Register reg = MI.getOperand(i - 1).getReg();
lib/Target/BPF/BTFDebug.cpp 1133 OutMI.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
lib/Target/Hexagon/BitTracker.h 144 : Reg(MO.getReg()), Sub(MO.getSubReg()) {}
lib/Target/Hexagon/HexagonAsmPrinter.cpp 83 O << HexagonInstPrinter::getRegisterName(MO.getReg());
133 Register RegNumber = MO.getReg();
lib/Target/Hexagon/HexagonBitSimplify.cpp 293 Register R = Op.getReg();
305 Register R = Op.getReg();
436 auto &DstRC = *MRI.getRegClass(I.getOperand(0).getReg());
979 Register DR = UseI->getOperand(0).getReg();
1018 Register R = Op.getReg();
1220 Register DefR = UseI.getOperand(0).getReg();
2281 if (Op1.getReg() != SrcR || Op1.getSubReg() != SrcSR)
2287 MachineInstr *DefI = MRI.getVRegDef(Op0.getReg());
2294 NewR = Op0.getReg();
2535 if (SrcOp.getReg() == R)
2680 .addReg(InpDef->getOperand(1).getReg())
3014 if (Op.getReg() == InpR)
3095 unsigned UseR = RegMap[Op.getReg()];
lib/Target/Hexagon/HexagonBitTracker.cpp 1045 Register R = Op.getReg();
lib/Target/Hexagon/HexagonBlockRanges.cpp 323 RegisterRef R = { Op.getReg(), Op.getSubReg() };
339 RegisterRef R = { Op.getReg(), Op.getSubReg() };
lib/Target/Hexagon/HexagonConstExtenders.cpp 233 : Reg(Op.getReg()), Sub(Op.getSubReg()) {}
236 Reg = Op.getReg();
1187 ED.Rd = { MI.getOperand(0).getReg(), Hexagon::isub_hi };
1191 ED.Rd = { MI.getOperand(0).getReg(), Hexagon::isub_lo };
1926 MRI->getRegClass(Op.getReg()) != &Hexagon::PredRegsRegClass)
lib/Target/Hexagon/HexagonConstPropagation.cpp 90 : Reg(MO.getReg()), SubReg(MO.getSubReg()) {}
2816 Register R = MO.getReg();
2834 Register R = MO.getReg();
3015 .addReg(Src1.getReg(), getRegState(Src1), Src1.getSubReg())
3016 .addReg(OpR2.getReg(), getRegState(OpR2), OpR2.getSubReg())
lib/Target/Hexagon/HexagonCopyToCombine.cpp 136 Register DestReg = Op0.getReg();
137 Register SrcReg = Op1.getReg();
149 Register DestReg = Op0.getReg();
240 if (!Op.isReg() || Op.getReg() != RegNotKilled || !Op.isKill())
258 return MO.isReg() ? MO.getReg() : Register();
409 if (!Op.isReg() || !Op.isUse() || !Op.getReg())
413 Register Reg = Op.getReg();
443 if (!Op.isDef() || !Op.getReg())
445 Register Reg = Op.getReg();
531 Register I1DestReg = I1.getOperand(0).getReg();
547 Register I2DestReg = I2->getOperand(0).getReg();
582 Register I1DestReg = I1.getOperand(0).getReg();
583 Register I2DestReg = I2.getOperand(0).getReg();
761 Register LoReg = LoOperand.getReg();
810 Register HiReg = HiOperand.getReg();
834 .addReg(HiOperand.getReg(), HiRegKillFlag)
841 .addReg(HiOperand.getReg(), HiRegKillFlag)
860 Register LoReg = LoOperand.getReg();
861 Register HiReg = HiOperand.getReg();
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 253 Register PredR = T1I->getOperand(0).getReg();
387 Register R = MO.getReg();
404 Register R = MO.getReg();
440 Register DefR = MI.getOperand(0).getReg();
479 const MachineInstr *Def1 = MRI->getVRegDef(RA.getReg());
480 const MachineInstr *Def3 = MRI->getVRegDef(RB.getReg());
494 Register R = MO.getReg();
821 SR = RO.getReg(), SSR = RO.getSubReg();
823 TR = RO.getReg(), TSR = RO.getSubReg();
825 FR = RO.getReg(), FSR = RO.getSubReg();
840 Register DR = PN->getOperand(0).getReg();
991 Register UseR = UO.getReg(), UseSR = UO.getSubReg();
992 Register DefR = PN->getOperand(0).getReg();
lib/Target/Hexagon/HexagonExpandCondsets.cpp 177 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()),
320 if (!Op.isReg() || !Op.isUse() || Op.getReg() != Reg ||
375 Register DR = Op.getReg(), DSR = Op.getSubReg();
647 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
648 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg());
652 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
674 Register DR = MD.getReg(), DSR = MD.getSubReg();
681 UpdRegs.insert(Op.getReg());
884 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg());
885 MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0,
901 UpdRegs.insert(Op.getReg());
953 if (MD.getSubReg() && !MRI->shouldTrackSubRegLiveness(MD.getReg()))
957 Register PredR = MP.getReg();
1083 UpdRegs.insert(Op.getReg());
1230 UpdRegs.insert(S1.getReg());
1241 UpdRegs.insert(S2.getReg());
1285 if (!CoalUpd.count(Op.getReg()))
1286 KillUpd.insert(Op.getReg());
lib/Target/Hexagon/HexagonFrameLowering.cpp 306 Register R = MO.getReg();
1389 AP = AI->getOperand(0).getReg();
1573 Register DstR = MI->getOperand(0).getReg();
1574 Register SrcR = MI->getOperand(1).getReg();
1598 Register SrcR = MI->getOperand(2).getReg();
1631 Register DstR = MI->getOperand(0).getReg();
1661 Register SrcR = MI->getOperand(2).getReg();
1698 Register DstR = MI->getOperand(0).getReg();
1748 Register SrcR = MI->getOperand(2).getReg();
1796 Register DstR = MI->getOperand(0).getReg();
1837 Register SrcR = MI->getOperand(2).getReg();
1866 Register DstR = MI->getOperand(0).getReg();
2253 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(),
2302 Register DstR = MI.getOperand(0).getReg();
2353 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg();
2353 unsigned Rd = RdOp.getReg(), Rs = RsOp.getReg();
lib/Target/Hexagon/HexagonGenInsert.cpp 609 Register R = MO.getReg();
727 Register R = MO.getReg();
740 Register R = MO.getReg();
1480 Register R = MO.getReg();
lib/Target/Hexagon/HexagonGenMux.cpp 174 Register R = MO.getReg();
242 Register DR = MI->getOperand(0).getReg();
249 Register PR = PredOp.getReg();
306 Register SR1 = Src1->isReg() ? Src1->getReg() : Register();
307 Register SR2 = Src2->isReg() ? Src2->getReg() : Register();
368 bool Live = IsLive(Op.getReg());
lib/Target/Hexagon/HexagonGenPredicate.cpp 53 RegisterSubReg(const MachineOperand &MO) : R(MO.getReg()), S(MO.getSubReg()) {}
214 if (isPredReg(MI->getOperand(1).getReg())) {
355 WorkQ.push(RegisterSubReg(MO.getReg()));
lib/Target/Hexagon/HexagonHardwareLoops.cpp 438 Register PhiOpReg = Phi->getOperand(i).getReg();
444 Register IndReg = DI->getOperand(1).getReg();
448 Register UpdReg = DI->getOperand(0).getReg();
611 IVReg = IV_Phi->getOperand(i).getReg(); // Want IV reg after bump.
677 if (Op2.isImm() || Op1.getReg() == IVReg)
697 Register R = InitialValue->getReg();
707 Register R = EndValue->getReg();
737 const MachineInstr *StartValInstr = MRI->getVRegDef(Start->getReg());
743 const MachineInstr *EndValInstr = MRI->getVRegDef(End->getReg());
888 R = Start->getReg();
891 R = End->getReg();
906 DistR = End->getReg();
918 SubIB.addReg(End->getReg(), 0, End->getSubReg())
919 .addReg(Start->getReg(), 0, Start->getSubReg());
922 .addReg(Start->getReg(), 0, Start->getSubReg());
928 const MachineInstr *EndValInstr = MRI->getVRegDef(End->getReg());
932 DistR = EndValInstr->getOperand(1).getReg();
937 SubIB.addReg(End->getReg(), 0, End->getSubReg())
1041 Register Reg = MO.getReg();
1061 Register OPReg = OPO.getReg();
1095 Register Reg = MO.getReg();
1336 Register PredR = CmpI->getOperand(0).getReg();
1344 if (MO.getReg() == PredR) // Found an intervening use of PredR.
1368 if (LoopFeederPhi.find(MO->getReg()) == LoopFeederPhi.end()) {
1376 MachineInstr *Def = MRI->getVRegDef(MO->getReg());
1377 LoopFeederPhi.insert(std::make_pair(MO->getReg(), Def));
1431 Register Reg = InitVal->getReg();
1511 Register R = MO.getReg();
1585 Register R = MO.getReg();
1637 Register PhiReg = Phi->getOperand(i).getReg();
1643 Register IndReg = DI->getOperand(1).getReg();
1647 Register UpdReg = DI->getOperand(0).getReg();
1705 Register P = Cond[CSz - 1].getReg();
1727 CmpRegs.insert(MO.getReg());
1769 if (MO.isReg() && MO.getReg() == RB.first) {
1779 << ") = " << *(MRI->getVRegDef(MO.getReg())));
1783 nonIndI = MRI->getVRegDef(MO.getReg());
1794 nonIndMO->setReg(nonIndI->getOperand(1).getReg());
1836 if (MO.isReg() && MO.getReg() == RB.first) {
1906 Register PR = PN->getOperand(0).getReg();
1914 Register PredR = PN->getOperand(i).getReg();
lib/Target/Hexagon/HexagonHazardRecognizer.cpp 51 if (!MO.isReg() || RegDefs.count(MO.getReg()) == 0)
117 RegDefs.insert(MO.getReg());
lib/Target/Hexagon/HexagonInstrInfo.cpp 196 Register Reg = MO.getReg();
201 Uses.push_back(MO.getReg());
204 Defs.push_back(MO.getReg());
261 return MI.getOperand(0).getReg();
275 return MI.getOperand(0).getReg();
309 return MI.getOperand(2).getReg();
327 return MI.getOperand(3).getReg();
635 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
636 addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
638 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
646 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
670 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
697 LoopCount = Loop->getOperand(1).getReg();
741 Register LoopCount = Loop->getOperand(1).getReg();
1030 Register Mx = MI.getOperand(MxOp).getReg();
1048 if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1048 if (MD.getReg() != MS.getReg() && !MS.isUndef()) {
1049 copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1049 copyPhysReg(MBB, MI, DL, MD.getReg(), MS.getReg(), MS.isKill());
1056 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1062 Register SrcReg = MI.getOperand(1).getReg();
1063 Register DstReg = MI.getOperand(0).getReg();
1072 Register SrcReg = MI.getOperand(1).getReg();
1073 Register DstReg = MI.getOperand(0).getReg();
1081 Register SrcReg = MI.getOperand(1).getReg();
1082 Register DstReg = MI.getOperand(0).getReg();
1092 Register SrcReg = MI.getOperand(2).getReg();
1116 Register DstReg = MI.getOperand(0).getReg();
1135 Register Reg = MI.getOperand(0).getReg();
1143 Register Reg = MI.getOperand(0).getReg();
1151 BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1158 BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1165 Register Vd = MI.getOperand(0).getReg();
1174 Register DstReg = MI.getOperand(0).getReg();
1175 Register Src1Reg = MI.getOperand(1).getReg();
1176 Register Src2Reg = MI.getOperand(2).getReg();
1198 Register DstReg = MI.getOperand(0).getReg();
1199 Register Src1Reg = MI.getOperand(1).getReg();
1200 Register Src2Reg = MI.getOperand(2).getReg();
1201 Register Src3Reg = MI.getOperand(3).getReg();
1232 Register Rd = Op0.getReg();
1233 Register Pu = Op1.getReg();
1234 Register Rs = Op2.getReg();
1235 Register Rt = Op3.getReg();
1258 bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1259 Register PReg = Op1.getReg();
1263 if (Op0.getReg() != Op2.getReg()) {
1263 if (Op0.getReg() != Op2.getReg()) {
1264 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1264 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1271 T.addReg(Op0.getReg(), RegState::Implicit);
1274 if (Op0.getReg() != Op3.getReg()) {
1274 if (Op0.getReg() != Op3.getReg()) {
1280 T.addReg(Op0.getReg(), RegState::Implicit);
1292 bool IsDestLive = !LiveAtMI.available(MRI, Op0.getReg());
1293 Register PReg = Op1.getReg();
1297 if (Op0.getReg() != Op2.getReg()) {
1297 if (Op0.getReg() != Op2.getReg()) {
1298 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1298 unsigned S = Op0.getReg() != Op3.getReg() ? PState & ~RegState::Kill
1300 Register SrcLo = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_lo);
1301 Register SrcHi = HRI.getSubReg(Op2.getReg(), Hexagon::vsub_hi);
1308 T.addReg(Op0.getReg(), RegState::Implicit);
1311 if (Op0.getReg() != Op3.getReg()) {
1311 if (Op0.getReg() != Op3.getReg()) {
1312 Register SrcLo = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_lo);
1313 Register SrcHi = HRI.getSubReg(Op3.getReg(), Hexagon::vsub_hi);
1320 T.addReg(Op0.getReg(), RegState::Implicit);
1626 const TargetRegisterClass* RC = HRI.getMinimalPhysRegClass(MO.getReg());
1785 SrcReg = MI.getOperand(1).getReg();
1794 SrcReg = MI.getOperand(1).getReg();
1803 SrcReg = MI.getOperand(1).getReg();
1825 SrcReg2 = MI.getOperand(2).getReg();
1884 Register BaseRegA = BaseA.getReg();
1892 Register BaseRegB = BaseB.getReg();
2617 Register DstReg = MI1.getOperand(0).getReg();
2620 if (MI2.getOperand(I).isReg() && DstReg == MI2.getOperand(I).getReg())
2626 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2626 MI1.getOperand(0).getReg() == MI2.getOperand(3).getReg())
2955 if (Op.isReg() && Op.isUse() && Op.getReg() == Hexagon::R29)
2969 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
2969 if (Op.isReg() && Op.isDef() && Op.getReg() == Stored.getReg())
3101 if (MO.isReg() && MO.isDef() && MO.isImplicit() && (MO.getReg() == PredReg))
3307 DstReg = MI.getOperand(0).getReg();
3308 Src1Reg = MI.getOperand(1).getReg();
3309 Src2Reg = MI.getOperand(2).getReg();
3319 DstReg = MI.getOperand(0).getReg();
3320 SrcReg = MI.getOperand(1).getReg();
3330 DstReg = MI.getOperand(0).getReg();
3331 SrcReg = MI.getOperand(1).getReg();
3339 DstReg = MI.getOperand(0).getReg();
3344 DstReg = MI.getOperand(0).getReg();
3345 Src1Reg = MI.getOperand(1).getReg();
3360 Src1Reg = MI.getOperand(0).getReg();
3386 Register DestReg = GA.getOperand(0).getReg();
3737 DstReg = MI.getOperand(0).getReg();
3738 SrcReg = MI.getOperand(1).getReg();
3756 DstReg = MI.getOperand(0).getReg();
3757 SrcReg = MI.getOperand(1).getReg();
3775 DstReg = MI.getOperand(0).getReg();
3776 SrcReg = MI.getOperand(1).getReg();
3784 DstReg = MI.getOperand(0).getReg();
3785 SrcReg = MI.getOperand(1).getReg();
3793 DstReg = MI.getOperand(0).getReg();
3794 SrcReg = MI.getOperand(1).getReg();
3814 DstReg = MI.getOperand(0).getReg();
3827 DstReg = MI.getOperand(1).getReg();
3828 SrcReg = MI.getOperand(0).getReg();
3842 SrcReg = MI.getOperand(0).getReg();
3854 Src1Reg = MI.getOperand(0).getReg();
3855 Src2Reg = MI.getOperand(2).getReg();
3869 Src1Reg = MI.getOperand(0).getReg();
3870 Src2Reg = MI.getOperand(2).getReg();
3886 Src1Reg = MI.getOperand(0).getReg();
3887 Src2Reg = MI.getOperand(2).getReg();
3895 Src1Reg = MI.getOperand(0).getReg();
3896 Src2Reg = MI.getOperand(2).getReg();
3905 Src1Reg = MI.getOperand(0).getReg();
3913 Src1Reg = MI.getOperand(0).getReg();
3943 DstReg = MI.getOperand(0).getReg();
3944 SrcReg = MI.getOperand(1).getReg();
3965 DstReg = MI.getOperand(0).getReg();
3966 Src1Reg = MI.getOperand(1).getReg();
3967 Src2Reg = MI.getOperand(2).getReg();
3976 DstReg = MI.getOperand(0).getReg();
3977 SrcReg = MI.getOperand(1).getReg();
3986 DstReg = MI.getOperand(0).getReg();
3987 SrcReg = MI.getOperand(1).getReg();
3996 DstReg = MI.getOperand(0).getReg();
4007 DstReg = MI.getOperand(0).getReg();
4008 SrcReg = MI.getOperand(1).getReg();
4016 DstReg = MI.getOperand(0).getReg();
4017 SrcReg = MI.getOperand(1).getReg();
4026 DstReg = MI.getOperand(0).getReg();
4038 DstReg = MI.getOperand(0).getReg();
4039 SrcReg = MI.getOperand(1).getReg();
4047 DstReg = MI.getOperand(0).getReg();
4048 SrcReg = MI.getOperand(2).getReg();
4059 DstReg = MI.getOperand(0).getReg();
4060 SrcReg = MI.getOperand(1).getReg();
4103 if (DefMO.isReg() && Register::isPhysicalRegister(DefMO.getReg())) {
4105 for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
4116 for (MCSuperRegIterator SR(UseMO.getReg(), &HRI); SR.isValid(); ++SR) {
4268 PredReg = Cond[1].getReg();
lib/Target/Hexagon/HexagonMCInstLower.cpp 127 MCO = MCOperand::createReg(MO.getReg());
lib/Target/Hexagon/HexagonNewValueJump.cpp 156 if (!Hexagon::IntRegsRegClass.contains(Op.getReg()))
180 Register Reg = II->getOperand(i).getReg();
279 cmpReg1 = MI.getOperand(1).getReg();
282 cmpOp2 = MI.getOperand(2).getReg();
518 predReg = MI.getOperand(0).getReg();
566 MI.getOperand(0).getReg() == predReg) {
584 cmpReg1 = MI.getOperand(1).getReg();
587 cmpOp2 = MI.getOperand(2).getReg();
602 (MI.getOperand(0).getReg() == cmpReg1 ||
604 MI.getOperand(0).getReg() == (unsigned)cmpOp2))) {
606 Register feederReg = MI.getOperand(0).getReg();
654 Register UseR = MO.getReg();
661 if (Op.getReg() != UseR)
lib/Target/Hexagon/HexagonOptAddrMode.cpp 133 if (StOp.isReg() && StOp.getReg() == TfrDefR)
165 Register OffsetReg = MI.getOperand(2).getReg();
201 UseMI.getOperand(2).getReg() == MI.getOperand(0).getReg())
201 UseMI.getOperand(2).getReg() == MI.getOperand(0).getReg())
351 Register AddDefR = AddMI->getOperand(0).getReg();
365 if (!BaseOp.isReg() || BaseOp.getReg() != AddDefR)
384 Register BaseReg = AddMI->getOperand(1).getReg();
414 Register newReg = AddRegOp.getReg();
727 Register DefR = MI->getOperand(0).getReg();
756 if (op.isReg() && op.isUse() && DefR == op.getReg())
lib/Target/Hexagon/HexagonPeephole.cpp 139 Register DstReg = Dst.getReg();
140 Register SrcReg = Src.getReg();
160 Register DstReg = Dst.getReg();
161 Register SrcReg = Src2.getReg();
177 Register DstReg = Dst.getReg();
178 Register SrcReg = Src1.getReg();
188 Register DstReg = Dst.getReg();
189 Register SrcReg = Src.getReg();
211 Register DstReg = Dst.getReg();
212 Register SrcReg = Src.getReg();
240 Register Reg0 = Op0.getReg();
278 Register PSrc = MI.getOperand(PR).getReg();
281 QII->get(NewOp), MI.getOperand(0).getReg())
lib/Target/Hexagon/HexagonRDFOpt.cpp 124 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_hi),
125 DFG.makeRegRef(HiOp.getReg(), HiOp.getSubReg()));
126 mapRegs(DFG.makeRegRef(DstOp.getReg(), Hexagon::isub_lo),
127 DFG.makeRegRef(LoOp.getReg(), LoOp.getSubReg()));
139 mapRegs(DFG.makeRegRef(DstOp.getReg(), DstOp.getSubReg()),
140 DFG.makeRegRef(SrcOp.getReg(), SrcOp.getSubReg()));
lib/Target/Hexagon/HexagonRegisterInfo.cpp 252 Register DstReg = MI->getOperand(0).getReg();
253 Register SrcReg = MI->getOperand(1).getReg();
lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp 79 Register DestReg = MI.getOperand(0).getReg();
86 Register DestReg = MI.getOperand(0).getReg();
lib/Target/Hexagon/HexagonSplitDouble.cpp 213 Register R = Op.getReg();
261 Register T = MO.getReg();
375 Register Rs = MI->getOperand(1).getReg();
376 Register Rt = MI->getOperand(2).getReg();
443 if (Op.isReg() && Part.count(Op.getReg()))
502 Register PR = Cond[1].getReg();
510 CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg());
538 Register R = MD.getReg();
554 Register T = UseI->getOperand(0).getReg();
606 Register R = Op.getReg();
646 UUPairMap::const_iterator F = PairMap.find(ValOp.getReg());
653 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
656 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
662 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
666 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
676 const TargetRegisterClass *RC = MRI->getRegClass(UpdOp.getReg());
680 .addReg(AdrOp.getReg(), RSA)
682 MRI->replaceRegWith(UpdOp.getReg(), NewR);
709 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
736 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
745 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg());
753 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
765 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
771 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());
773 .addReg(Op1.getReg(), RS, Op1.getSubReg())
789 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
811 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
813 .addReg(Op1.getReg(), RS, HiSR);
836 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
839 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
842 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
848 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
854 .addReg(Op1.getReg(), RS, HiSR)
859 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)
864 .addReg(Op1.getReg(), RS, HiSR)
870 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));
876 .addReg(Op1.getReg(), RS, HiSR)
882 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
885 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);
888 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))
893 .addReg(Op1.getReg(), RS, HiSR)
914 UUPairMap::const_iterator F = PairMap.find(Op0.getReg());
946 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
947 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);
949 .addReg(Op1.getReg(), RS1, HiSR)
950 .addReg(Op2.getReg(), RS2, HiSR);
953 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
954 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
958 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
963 .addReg(Op1.getReg(), RS1, HiSR)
967 .addReg(Op2.getReg(), RS2, HiSR)
975 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
977 .addReg(Op1.getReg(), RS1, HiSR)
978 .addReg(Op2.getReg(), RS2, LoSR);
986 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
988 .addReg(Op1.getReg(), RS1, HiSR)
989 .addReg(Op2.getReg(), RS2, LoSR)
1005 Register DstR = MI->getOperand(0).getReg();
1082 Register R = Op.getReg();
1107 Register R = Op.getReg();
lib/Target/Hexagon/HexagonStoreWidening.cpp 124 return MO.getReg();
435 .addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg())
458 .addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg())
lib/Target/Hexagon/HexagonSubtarget.cpp 233 Register::isPhysicalRegister(MI->getOperand(1).getReg())) {
235 VRegHoldingReg[MI->getOperand(0).getReg()] = MI->getOperand(1).getReg();
235 VRegHoldingReg[MI->getOperand(0).getReg()] = MI->getOperand(1).getReg();
236 LastVRegUse.erase(MI->getOperand(1).getReg());
243 VRegHoldingReg.count(MO.getReg())) {
245 LastVRegUse[VRegHoldingReg[MO.getReg()]] = &DAG->SUnits[su];
246 } else if (MO.isDef() && Register::isPhysicalRegister(MO.getReg())) {
247 for (MCRegAliasIterator AI(MO.getReg(), &TRI, true); AI.isValid();
294 BaseOp0->getReg() != BaseOp1->getReg())
294 BaseOp0->getReg() != BaseOp1->getReg())
347 Register DReg = DstInst->getOperand(0).getReg();
352 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) {
352 if (MO.isReg() && MO.getReg() && MO.isUse() && MO.getReg() == DReg) {
427 if (MO.isReg() && MO.isDef() && MO.getReg() == DepR)
435 if (MO.isReg() && MO.isUse() && MO.getReg() == DepR) {
lib/Target/Hexagon/HexagonVExtract.cpp 72 Register ExtIdxR = ExtI->getOperand(2).getReg();
114 Register VecR = MI.getOperand(1).getReg();
143 assert(ExtI->getOperand(1).getReg() == VecR);
153 Register ExtR = ExtI->getOperand(0).getReg();
lib/Target/Hexagon/HexagonVLIWPacketizer.cpp 152 Register R = MO.getReg();
312 if (MO.isReg() && MO.getReg() == DepReg && !MO.isImplicit())
387 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg())
387 if (MO.isReg() && MO.getReg() == MI->getOperand(0).getReg())
426 Register DestReg = MI.getOperand(0).getReg();
429 if (MO.isReg() && MO.getReg() == DestReg)
519 Register Reg = MI.getOperand(BPI).getReg();
520 if (Reg != MJ.getOperand(BPJ).getReg())
578 DefRegsSet.insert(MO.getReg());
581 if (MO.isReg() && MO.isUse() && DefRegsSet.count(MO.getReg()))
651 if (Val.isReg() && Val.getReg() != DepReg)
673 getPostIncrementOperand(MI, HII).getReg() == DepReg) {
678 getPostIncrementOperand(PacketMI, HII).getReg() == DepReg) {
687 if (isLoadAbsSet(PacketMI) && getAbsSetOperand(PacketMI).getReg() == DepReg)
706 predRegNumSrc = MO.getReg();
718 predRegNumDst = MO.getReg();
765 if (MO.isReg() && TempSU->getInstr()->modifiesRegister(MO.getReg(), HRI))
778 if (MO.isReg() && MO.getReg() == DepReg)
792 Register R = MO.getReg();
803 if (MO.isReg() && MO.isUse() && MO.isImplicit() && MO.getReg() == DepReg)
833 if (!MO.isReg() || MO.getReg() != DepReg || !MO.isImplicit())
947 if (Op.isReg() && Op.getReg() && Op.isUse() &&
948 Hexagon::PredRegsRegClass.contains(Op.getReg()))
949 return Op.getReg();
1206 DeadDefs[MO.getReg()] = true;
1212 Register R = MO.getReg();
1274 if (OpJ.clobbersPhysReg(OpI.getReg()))
1356 if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
1356 if (NOp1.isReg() && I.getOperand(0).getReg() == NOp1.getReg())
1380 if (OpR.isReg() && PI->modifiesRegister(OpR.getReg(), HRI)) {
1562 if (I.getOperand(0).getReg() == HRI->getStackRegister()) {
1589 Register R = Op.getReg();
lib/Target/Hexagon/HexagonVectorPrint.cpp 111 Reg = MI.getOperand(0).getReg();
117 Reg = MI.getOperand(2).getReg();
123 Reg = MI.getOperand(3).getReg();
lib/Target/Hexagon/RDFCopy.cpp 46 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg());
47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg());
lib/Target/Hexagon/RDFDeadCode.cpp 67 if (Op.isReg() && MRI.isReserved(Op.getReg()))
lib/Target/Hexagon/RDFGraph.cpp 636 Register Reg = Op.getReg();
976 return makeRegRef(Op.getReg(), Op.getSubReg());
1272 if (!Op.isReg() || Op.getReg() == 0 || !Op.isUse() || Op.isUndef())
1294 Register R = Op.getReg();
1339 Register R = Op.getReg();
1368 Register R = Op.getReg();
lib/Target/Hexagon/RDFLiveness.cpp 892 Register R = Op.getReg();
901 Register R = Op.getReg();
lib/Target/Lanai/LanaiAsmPrinter.cpp 70 O << LanaiInstPrinter::getRegisterName(MO.getReg());
136 Register Reg = MO.getReg();
182 .addReg(MI->getOperand(0).getReg())
lib/Target/Lanai/LanaiDelaySlotFiller.cpp 109 RI->getOperand(0).getReg() == Lanai::FP &&
111 RI->getOperand(1).getReg() == Lanai::FP &&
116 RI->getOperand(0).getReg() == Lanai::SP &&
118 RI->getOperand(1).getReg() == Lanai::FP);
207 if (!MO.isReg() || !(Reg = MO.getReg()))
236 if (!MO.isReg() || !(Reg = MO.getReg()))
lib/Target/Lanai/LanaiFrameLowering.cpp 75 Register Dst = MI.getOperand(0).getReg();
76 Register Src = MI.getOperand(1).getReg();
lib/Target/Lanai/LanaiInstrInfo.cpp 185 SrcReg = MI.getOperand(0).getReg();
191 SrcReg = MI.getOperand(0).getReg();
192 SrcReg2 = MI.getOperand(1).getReg();
210 ((OI->getOperand(1).getReg() == SrcReg &&
211 OI->getOperand(2).getReg() == SrcReg2) ||
212 (OI->getOperand(1).getReg() == SrcReg2 &&
213 OI->getOperand(2).getReg() == SrcReg)))
220 OI->getOperand(1).getReg() == SrcReg &&
364 if (!MO.isReg() || MO.getReg() != Lanai::SR)
382 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
383 Sub->getOperand(2).getReg() == SrcReg) {
481 if (Register::isPhysicalRegister(MO.getReg()))
498 MachineInstr *DefMI = canFoldIntoSelect(MI.getOperand(1).getReg(), MRI);
501 DefMI = canFoldIntoSelect(MI.getOperand(2).getReg(), MRI);
507 Register DestReg = MI.getOperand(0).getReg();
508 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
723 return MI.getOperand(0).getReg();
752 return MI.getOperand(2).getReg();
lib/Target/Lanai/LanaiMCInstLower.cpp 105 MCOp = MCOperand::createReg(MO.getReg());
lib/Target/Lanai/LanaiMemAluCombiner.cpp 176 return Op1.getReg() == Op2.getReg();
176 return Op1.getReg() == Op2.getReg();
185 return ((Op.isReg() && Op.getReg() == Lanai::R0) ||
260 InstrBuilder.addReg(Dest.getReg(), getDefRegState(true));
261 InstrBuilder.addReg(Base.getReg(), getKillRegState(true));
265 InstrBuilder.addReg(AluOffset.getReg());
307 if (Offset.isReg() && Offset.getReg() == Lanai::R0)
320 if (Offset.isReg() && Op2.getReg() == Offset.getReg())
320 if (Offset.isReg() && Op2.getReg() == Offset.getReg())
373 unsigned int DestReg = MBBIter->getOperand(0).getReg(),
374 BaseReg = MBBIter->getOperand(1).getReg();
lib/Target/Lanai/LanaiRegisterInfo.cpp 203 MI.getOperand(0).getReg())
239 MI.getOperand(0).getReg())
lib/Target/MSP430/MSP430AsmPrinter.cpp 84 O << MSP430InstPrinter::getRegisterName(MO.getReg());
115 if (Disp.isImm() && Base.getReg() == MSP430::SR)
120 if (Base.getReg() != MSP430::SR && Base.getReg() != MSP430::PC) {
120 if (Base.getReg() != MSP430::SR && Base.getReg() != MSP430::PC) {
lib/Target/MSP430/MSP430ISelLowering.cpp 1452 Register SrcReg = MI.getOperand(1).getReg();
1453 Register DstReg = MI.getOperand(0).getReg();
1489 Register ShiftAmtSrcReg = MI.getOperand(2).getReg();
1490 Register SrcReg = MI.getOperand(1).getReg();
1491 Register DstReg = MI.getOperand(0).getReg();
1600 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg())
1601 .addReg(MI.getOperand(2).getReg())
1603 .addReg(MI.getOperand(1).getReg())
lib/Target/MSP430/MSP430MCInstLower.cpp 129 MCOp = MCOperand::createReg(MO.getReg());
lib/Target/MSP430/MSP430RegisterInfo.cpp 142 Register DstReg = MI.getOperand(0).getReg();
lib/Target/Mips/MicroMipsSizeReduction.cpp 287 if (MO.isReg() && ((MO.getReg() == Mips::SP)))
294 if (MO.isReg() && Mips::GPRMM16RegClass.contains(MO.getReg()))
301 if (MO.isReg() && Mips::GPRMM16ZeroRegClass.contains(MO.getReg()))
364 Register reg = MI->getOperand(0).getReg();
371 if (ReduceToLwp && (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
371 if (ReduceToLwp && (MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
406 Register Reg1 = MI1->getOperand(0).getReg();
407 Register Reg2 = MI2->getOperand(0).getReg();
478 Register Reg1 = MI1->getOperand(1).getReg();
479 Register Reg2 = MI2->getOperand(1).getReg();
624 Register RegDstMI1 = MI1->getOperand(0).getReg();
625 Register RegSrcMI1 = MI1->getOperand(1).getReg();
636 Register RegDstMI2 = MI2->getOperand(0).getReg();
637 Register RegSrcMI2 = MI2->getOperand(1).getReg();
664 if (!(MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) &&
664 if (!(MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) &&
665 !(MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
665 !(MI->getOperand(0).getReg() == MI->getOperand(1).getReg()))
722 if (MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) {
722 if (MI->getOperand(0).getReg() == MI->getOperand(2).getReg()) {
lib/Target/Mips/Mips16ISelLowering.cpp 547 .addReg(MI.getOperand(3).getReg())
563 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
564 .addReg(MI.getOperand(1).getReg())
566 .addReg(MI.getOperand(2).getReg())
610 .addReg(MI.getOperand(3).getReg())
611 .addReg(MI.getOperand(4).getReg());
627 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
628 .addReg(MI.getOperand(1).getReg())
630 .addReg(MI.getOperand(2).getReg())
676 .addReg(MI.getOperand(3).getReg())
693 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
694 .addReg(MI.getOperand(1).getReg())
696 .addReg(MI.getOperand(2).getReg())
711 Register regX = MI.getOperand(0).getReg();
712 Register regY = MI.getOperand(1).getReg();
728 Register regX = MI.getOperand(0).getReg();
761 Register CC = MI.getOperand(0).getReg();
762 Register regX = MI.getOperand(1).getReg();
763 Register regY = MI.getOperand(2).getReg();
780 Register CC = MI.getOperand(0).getReg();
781 Register regX = MI.getOperand(1).getReg();
lib/Target/Mips/Mips16InstrInfo.cpp 360 if (MO.isReg() && MO.getReg() != 0 && !MO.isDef() &&
361 !Register::isVirtualRegister(MO.getReg()))
362 Candidates.reset(MO.getReg());
377 DefReg = MO.getReg();
lib/Target/Mips/Mips16RegisterInfo.cpp 110 FrameReg = MI.getOperand(OpNo+2).getReg();
lib/Target/Mips/MipsAsmPrinter.cpp 575 Register Reg = MO.getReg();
601 Register Reg = MO.getReg();
649 O << Offset << "($" << MipsInstPrinter::getRegisterName(BaseMO.getReg())
685 << StringRef(MipsInstPrinter::getRegisterName(MO.getReg())).lower();
lib/Target/Mips/MipsBranchExpansion.cpp 350 MIB.addReg(MO.getReg());
lib/Target/Mips/MipsConstantIslandPass.cpp 1619 .addReg(MI->getOperand(0).getReg())
lib/Target/Mips/MipsDelaySlotFiller.cpp 331 if (!MO.isReg() || !MO.isDef() || !(R = MO.getReg()))
420 if (MO.isReg() && MO.getReg())
421 HasHazard |= checkRegDefsUses(NewDefs, NewUses, MO.getReg(), MO.isDef());
710 baseRegNeedsLoadStoreMask(CurrI->getOperand(AddrIdx).getReg())) ||
lib/Target/Mips/MipsExpandPseudo.cpp 102 Register Dest = I->getOperand(0).getReg();
103 Register Ptr = I->getOperand(1).getReg();
104 Register Mask = I->getOperand(2).getReg();
105 Register ShiftCmpVal = I->getOperand(3).getReg();
106 Register Mask2 = I->getOperand(4).getReg();
107 Register ShiftNewVal = I->getOperand(5).getReg();
108 Register ShiftAmnt = I->getOperand(6).getReg();
109 Register Scratch = I->getOperand(7).getReg();
110 Register Scratch2 = I->getOperand(8).getReg();
243 Register Dest = I->getOperand(0).getReg();
244 Register Ptr = I->getOperand(1).getReg();
245 Register OldVal = I->getOperand(2).getReg();
246 Register NewVal = I->getOperand(3).getReg();
247 Register Scratch = I->getOperand(4).getReg();
377 Register Dest = I->getOperand(0).getReg();
378 Register Ptr = I->getOperand(1).getReg();
379 Register Incr = I->getOperand(2).getReg();
380 Register Mask = I->getOperand(3).getReg();
381 Register Mask2 = I->getOperand(4).getReg();
382 Register ShiftAmnt = I->getOperand(5).getReg();
383 Register OldVal = I->getOperand(6).getReg();
384 Register BinOpRes = I->getOperand(7).getReg();
385 Register StoreVal = I->getOperand(8).getReg();
516 Register OldVal = I->getOperand(0).getReg();
517 Register Ptr = I->getOperand(1).getReg();
518 Register Incr = I->getOperand(2).getReg();
519 Register Scratch = I->getOperand(3).getReg();
lib/Target/Mips/MipsISelLowering.cpp 1276 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
1478 Register OldVal = MI.getOperand(0).getReg();
1479 Register Ptr = MI.getOperand(1).getReg();
1480 Register Incr = MI.getOperand(2).getReg();
1582 Register Dest = MI.getOperand(0).getReg();
1583 Register Ptr = MI.getOperand(1).getReg();
1584 Register Incr = MI.getOperand(2).getReg();
1739 Register Dest = MI.getOperand(0).getReg();
1740 Register Ptr = MI.getOperand(1).getReg();
1741 Register OldVal = MI.getOperand(2).getReg();
1742 Register NewVal = MI.getOperand(3).getReg();
1791 Register Dest = MI.getOperand(0).getReg();
1792 Register Ptr = MI.getOperand(1).getReg();
1793 Register CmpVal = MI.getOperand(2).getReg();
1794 Register NewVal = MI.getOperand(3).getReg();
4458 .addReg(MI.getOperand(1).getReg())
4463 .addReg(MI.getOperand(1).getReg())
4481 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4482 .addReg(MI.getOperand(2).getReg())
4484 .addReg(MI.getOperand(3).getReg())
4533 .addReg(MI.getOperand(2).getReg())
4551 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4552 .addReg(MI.getOperand(3).getReg())
4554 .addReg(MI.getOperand(5).getReg())
4556 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg())
4557 .addReg(MI.getOperand(4).getReg())
4559 .addReg(MI.getOperand(6).getReg())
lib/Target/Mips/MipsInstrInfo.cpp 451 if (I->getOperand(1).getReg() == Subtarget.getABI().GetZeroReg())
467 (I->getOperand(0).getReg() == Mips::ZERO ||
468 I->getOperand(0).getReg() == Mips::ZERO_64)) &&
470 (I->getOperand(1).getReg() == Mips::ZERO ||
471 I->getOperand(1).getReg() == Mips::ZERO_64)))
484 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
484 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
491 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
491 else if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
495 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
495 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
499 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
499 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
509 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
509 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
513 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
513 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
519 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
519 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
523 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
523 if (I->getOperand(0).getReg() == I->getOperand(1).getReg())
lib/Target/Mips/MipsInstructionSelector.cpp 89 Register DstReg = I.getOperand(0).getReg();
168 const Register DestReg = I.getOperand(0).getReg();
243 (RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI)->getID() ==
277 .addDef(I.getOperand(0).getReg())
320 .addUse(I.getOperand(2).getReg())
328 .addUse(I.getOperand(0).getReg())
371 const Register DestReg = I.getOperand(0).getReg();
401 MachineInstr *Addr = MRI.getVRegDef(I.getOperand(1).getReg());
403 MachineInstr *Offset = MRI.getVRegDef(Addr->getOperand(2).getReg());
439 .addDef(I.getOperand(0).getReg())
461 MRI.setRegClass(MI->getOperand(0).getReg(),
463 MRI.getType(I.getOperand(0).getReg()).getSizeInBits(),
464 *RBI.getRegBank(I.getOperand(0).getReg(), MRI, TRI),
470 if (!materialize32BitImm(I.getOperand(0).getReg(),
480 unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
489 B.buildInstr(Mips::MTC1, {I.getOperand(0).getReg()}, {GPRReg});
504 {I.getOperand(0).getReg()}, {GPRRegLow, GPRRegHigh});
513 unsigned Size = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
523 unsigned FromSize = MRI.getType(I.getOperand(1).getReg()).getSizeInBits();
524 unsigned ToSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
538 .addUse(I.getOperand(1).getReg());
543 .addDef(I.getOperand(0).getReg())
555 .addDef(I.getOperand(0).getReg())
579 .addDef(I.getOperand(0).getReg())
598 .addDef(I.getOperand(0).getReg())
611 .addDef(I.getOperand(0).getReg())
621 .addDef(I.getOperand(0).getReg())
641 Register ICMPReg = I.getOperand(0).getReg();
643 Register LHS = I.getOperand(2).getReg();
644 Register RHS = I.getOperand(3).getReg();
762 unsigned Size = MRI.getType(I.getOperand(2).getReg()).getSizeInBits();
767 .addUse(I.getOperand(2).getReg())
768 .addUse(I.getOperand(3).getReg())
774 .addDef(I.getOperand(0).getReg())
803 .addUse(I.getOperand(0).getReg())
lib/Target/Mips/MipsLegalizerInfo.cpp 256 Register Dst = MI.getOperand(0).getReg();
257 Register Src = MI.getOperand(1).getReg();
lib/Target/Mips/MipsMCInstLower.cpp 188 return MCOperand::createReg(MO.getReg());
lib/Target/Mips/MipsOptimizePICCall.cpp 130 if (!MO.isReg() || !MO.isUse() || !Register::isVirtualRegister(MO.getReg()))
154 Register SrcReg = I->getOperand(0).getReg();
167 MVT::SimpleValueType Ty = getRegTy(MI.getOperand(0).getReg(), MF);
172 if (MO.isReg() && MO.getReg() == Reg) {
278 Reg = MO->getReg();
lib/Target/Mips/MipsRegisterBankInfo.cpp 179 !Register::isPhysicalRegister(NonCopyInstr->getOperand(0).getReg()))
180 addDefUses(NonCopyInstr->getOperand(0).getReg(), MRI);
201 !Register::isPhysicalRegister(Ret->getOperand(0).getReg()) &&
202 MRI.hasOneUse(Ret->getOperand(0).getReg())) {
203 Ret = &(*MRI.use_instr_begin(Ret->getOperand(0).getReg()));
215 !Register::isPhysicalRegister(Ret->getOperand(1).getReg()))
216 Ret = MRI.getVRegDef(Ret->getOperand(1).getReg());
228 addDefUses(MI->getOperand(0).getReg(), MRI);
231 addUseDef(MI->getOperand(0).getReg(), MRI);
234 addDefUses(MI->getOperand(0).getReg(), MRI);
237 addUseDef(MI->getOperand(i).getReg(), MRI);
241 addDefUses(MI->getOperand(0).getReg(), MRI);
243 addUseDef(MI->getOperand(2).getReg(), MRI);
244 addUseDef(MI->getOperand(3).getReg(), MRI);
248 addDefUses(MI->getOperand(0).getReg(), MRI);
336 assert((Register::isPhysicalRegister(CopyInst->getOperand(Op).getReg())) &&
345 RBI.getRegBank(CopyInst->getOperand(Op).getReg(), MRI, TRI);
423 LLT RegTy = MRI.getType(Op.getReg());
434 const LLT Op0Ty = MRI.getType(MI.getOperand(0).getReg());
556 unsigned Op2Size = MRI.getType(MI.getOperand(2).getReg()).getSizeInBits();
572 unsigned SizeFP = MRI.getType(MI.getOperand(1).getReg()).getSizeInBits();
578 assert((MRI.getType(MI.getOperand(1).getReg()).getSizeInBits() == 32) &&
627 Register Dest = MI.getOperand(0).getReg();
lib/Target/Mips/MipsSEFrameLowering.cpp 175 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
190 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
209 Register Dst = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
234 Register Src = I->getOperand(0).getReg(), FI = I->getOperand(1).getIndex();
245 Register Src = I->getOperand(1).getReg();
261 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
261 unsigned Dst = I->getOperand(0).getReg(), Src = I->getOperand(1).getReg();
306 && I->getOperand(3).getReg() == Mips::SP) {
307 Register DstReg = I->getOperand(0).getReg();
308 Register LoReg = I->getOperand(1).getReg();
309 Register HiReg = I->getOperand(2).getReg();
349 Register DstReg = I->getOperand(0).getReg();
371 && I->getOperand(3).getReg() == Mips::SP) {
372 Register DstReg = I->getOperand(0).getReg();
373 Register SrcReg = Op1.getReg();
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 88 (MI.getOperand(1).getReg() == Mips::ZERO) &&
91 DstReg = MI.getOperand(0).getReg();
94 (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
97 DstReg = MI.getOperand(0).getReg();
118 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg))
lib/Target/Mips/MipsSEISelLowering.cpp 3079 MI.getOperand(0).getReg())
3132 .addReg(MI.getOperand(1).getReg())
3148 MI.getOperand(0).getReg())
3174 Register Fd = MI.getOperand(0).getReg();
3175 Register Ws = MI.getOperand(1).getReg();
3219 Register Fd = MI.getOperand(0).getReg();
3220 Register Ws = MI.getOperand(1).getReg();
3249 Register Wd = MI.getOperand(0).getReg();
3250 Register Wd_in = MI.getOperand(1).getReg();
3252 Register Fs = MI.getOperand(3).getReg();
3285 Register Wd = MI.getOperand(0).getReg();
3286 Register Wd_in = MI.getOperand(1).getReg();
3288 Register Fs = MI.getOperand(3).getReg();
3331 Register Wd = MI.getOperand(0).getReg();
3332 Register SrcVecReg = MI.getOperand(1).getReg();
3333 Register LaneReg = MI.getOperand(2).getReg();
3334 Register SrcValReg = MI.getOperand(3).getReg();
3445 Register Wd = MI.getOperand(0).getReg();
3446 Register Fs = MI.getOperand(1).getReg();
3480 Register Wd = MI.getOperand(0).getReg();
3481 Register Fs = MI.getOperand(1).getReg();
3514 Register Ws = MI.getOperand(0).getReg();
3515 Register Rt = MI.getOperand(1).getReg();
3523 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3569 Register Wd = MI.getOperand(0).getReg();
3575 MI.getOperand(1).isReg() ? RegInfo.getRegClass(MI.getOperand(1).getReg())
3663 Register Wd = MI.getOperand(0).getReg();
3664 Register Fs = MI.getOperand(1).getReg();
3768 Register Fd = MI.getOperand(0).getReg();
3769 Register Ws = MI.getOperand(1).getReg();
3831 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())
3833 .addReg(MI.getOperand(1).getReg());
3860 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg())
3862 .addReg(MI.getOperand(1).getReg());
lib/Target/Mips/MipsSEInstrInfo.cpp 55 return MI.getOperand(0).getReg();
77 return MI.getOperand(0).getReg();
192 if (MI.getOperand(2).getReg() == Mips::ZERO)
196 if (MI.getOperand(2).getReg() == Mips::ZERO_64)
715 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
737 Register DstReg = I->getOperand(0).getReg();
744 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
745 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
754 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
754 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
776 Register DstReg = I->getOperand(0).getReg();
777 Register SrcReg = I->getOperand(1).getReg();
818 Register DstReg = I->getOperand(0).getReg();
819 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
819 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
886 Register OffsetReg = I->getOperand(0).getReg();
887 Register TargetReg = I->getOperand(1).getReg();
lib/Target/NVPTX/NVPTXAsmPrinter.cpp 244 MCOp = MCOperand::createReg(encodeVirtualRegister(MO.getReg()));
510 Register RegNo = MI->getOperand(0).getReg();
2213 if (Register::isPhysicalRegister(MO.getReg())) {
2214 if (MO.getReg() == NVPTX::VRDepot)
2217 O << NVPTXInstPrinter::getRegisterName(MO.getReg());
2219 emitVirtualRegister(MO.getReg(), O);
lib/Target/NVPTX/NVPTXInstrInfo.cpp 198 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
204 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
lib/Target/NVPTX/NVPTXPeephole.cpp 84 if (Op.isReg() && Register::isVirtualRegister(Op.getReg())) {
85 GenericAddrDef = MRI.getUniqueVRegDef(Op.getReg());
97 if (BaseAddrOp.isReg() && BaseAddrOp.getReg() == NVPTX::VRFrame) {
109 auto &Prev = *MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
113 Root.getOperand(0).getReg())
120 if (MRI.hasOneNonDBGUse(Prev.getOperand(0).getReg())) {
lib/Target/NVPTX/NVPTXProxyRegErasure.cpp 113 if (Op.isReg() && Op.getReg() == From.getReg()) {
113 if (Op.isReg() && Op.getReg() == From.getReg()) {
114 Op.setReg(To.getReg());
lib/Target/NVPTX/NVPTXReplaceImageHandles.cpp 140 MachineInstr &TexHandleDef = *MRI.getVRegDef(Op.getReg());
lib/Target/PowerPC/PPCAsmPrinter.cpp 213 const char *RegName = PPCInstPrinter::getRegisterName(MO.getReg());
278 Register Reg = MI->getOperand(OpNo).getReg();
391 Register ScratchReg = MI.getOperand(Opers.getNextScratchIdx()).getReg();
485 ((Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::X3) ||
486 (!Subtarget->isPPC64() && MI->getOperand(0).getReg() == PPC::R3)) &&
489 ((Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::X3) ||
490 (!Subtarget->isPPC64() && MI->getOperand(1).getReg() == PPC::R3)) &&
549 Register Reg = MO.getReg();
931 .addReg(MI->getOperand(0).getReg())
932 .addReg(MI->getOperand(1).getReg())
972 .addReg(MI->getOperand(0).getReg()));
974 .addReg(MI->getOperand(1).getReg())
976 .addReg(MI->getOperand(0).getReg()));
978 .addReg(MI->getOperand(0).getReg())
979 .addReg(MI->getOperand(1).getReg())
980 .addReg(MI->getOperand(0).getReg()));
991 .addReg(MI->getOperand(0).getReg())
994 .addReg(MI->getOperand(0).getReg())
995 .addReg(MI->getOperand(0).getReg())
1010 .addReg(MI->getOperand(0).getReg())
1011 .addReg(MI->getOperand(1).getReg())
1030 .addReg(MI->getOperand(0).getReg())
1031 .addReg(MI->getOperand(1).getReg())
1055 .addReg(MI->getOperand(0).getReg())
1056 .addReg(MI->getOperand(1).getReg())
1075 .addReg(MI->getOperand(0).getReg())
1076 .addReg(MI->getOperand(1).getReg())
1104 .addReg(MI->getOperand(0).getReg())
1105 .addReg(MI->getOperand(1).getReg())
1123 .addReg(MI->getOperand(0).getReg())
1124 .addReg(MI->getOperand(1).getReg())
1136 getRegisterName(MI->getOperand(1).getReg()));
1138 .addReg(MI->getOperand(0).getReg()));
1150 ->getEncodingValue(MI->getOperand(0).getReg());
1152 getRegisterName(MI->getOperand(0).getReg()));
1155 .addReg(MI->getOperand(1).getReg()));
1274 .addReg(MI->getOperand(2).getReg())
lib/Target/PowerPC/PPCBranchCoalescing.cpp 344 Register::isPhysicalRegister(Op1.getReg())
347 && !(Op1.isUse() && MRI->isConstantPhysReg(Op1.getReg()))) {
359 Register::isVirtualRegister(Op1.getReg()) &&
360 Register::isVirtualRegister(Op2.getReg())) {
361 MachineInstr *Op1Def = MRI->getVRegDef(Op1.getReg());
362 MachineInstr *Op2Def = MRI->getVRegDef(Op2.getReg());
429 for (auto &Use : MRI->use_instructions(Def.getReg())) {
460 if (Use.isReg() && Register::isVirtualRegister(Use.getReg())) {
461 MachineInstr *DefInst = MRI->getVRegDef(Use.getReg());
540 for (auto &Use : MRI->use_instructions(Def.getReg())) {
lib/Target/PowerPC/PPCBranchSelector.cpp 339 Register CRReg = I->getOperand(1).getReg();
345 Register CRBit = I->getOperand(0).getReg();
348 Register CRBit = I->getOperand(0).getReg();
lib/Target/PowerPC/PPCCTRLoops.cpp 117 if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8))
117 if (MO.isDef() && (MO.getReg() == PPC::CTR || MO.getReg() == PPC::CTR8))
lib/Target/PowerPC/PPCEarlyReturn.cpp 94 .addReg(J->getOperand(1).getReg())
109 .addReg(J->getOperand(0).getReg())
lib/Target/PowerPC/PPCExpandISEL.cpp 88 return (Op1.getReg() == Op2.getReg());
88 return (Op1.getReg() == Op2.getReg());
465 TrueBlock->addLiveIn(TrueValue.getReg());
470 FalseBlock->addLiveIn(FalseValue.getReg());
475 NewSuccessor->addLiveIn(Dest.getReg());
476 NewSuccessor->addLiveIn(TrueValue.getReg());
477 NewSuccessor->addLiveIn(FalseValue.getReg());
478 NewSuccessor->addLiveIn(ConditionRegister.getReg());
lib/Target/PowerPC/PPCFastISel.cpp 2355 Register ResultReg = MI->getOperand(0).getReg();
lib/Target/PowerPC/PPCFrameLowering.cpp 367 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
369 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
381 Register SrcReg = MI.getOperand(1).getReg();
382 Register DstReg = MI.getOperand(0).getReg();
577 switch (MO.getReg()) {
lib/Target/PowerPC/PPCISelLowering.cpp10335 Register dest = MI.getOperand(0).getReg();
10336 Register ptrA = MI.getOperand(1).getReg();
10337 Register ptrB = MI.getOperand(2).getReg();
10338 Register incr = MI.getOperand(3).getReg();
10439 Register dest = MI.getOperand(0).getReg();
10440 Register ptrA = MI.getOperand(1).getReg();
10441 Register ptrB = MI.getOperand(2).getReg();
10442 Register incr = MI.getOperand(3).getReg();
10622 Register DstReg = MI.getOperand(0).getReg();
10679 Register BufReg = MI.getOperand(1).getReg();
10783 Register BufReg = MI.getOperand(0).getReg();
10900 TII->insertSelect(*BB, MI, dl, MI.getOperand(0).getReg(), Cond,
10901 MI.getOperand(2).getReg(), MI.getOperand(3).getReg());
10901 MI.getOperand(2).getReg(), MI.getOperand(3).getReg());
10969 .addReg(MI.getOperand(1).getReg())
10975 .addReg(MI.getOperand(1).getReg())
10991 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::PHI), MI.getOperand(0).getReg())
10992 .addReg(MI.getOperand(3).getReg())
10994 .addReg(MI.getOperand(2).getReg())
11025 Register LoReg = MI.getOperand(0).getReg();
11026 Register HiReg = MI.getOperand(1).getReg();
11174 Register dest = MI.getOperand(0).getReg();
11175 Register ptrA = MI.getOperand(1).getReg();
11176 Register ptrB = MI.getOperand(2).getReg();
11177 Register oldval = MI.getOperand(3).getReg();
11178 Register newval = MI.getOperand(4).getReg();
11253 Register dest = MI.getOperand(0).getReg();
11254 Register ptrA = MI.getOperand(1).getReg();
11255 Register ptrB = MI.getOperand(2).getReg();
11256 Register oldval = MI.getOperand(3).getReg();
11257 Register newval = MI.getOperand(4).getReg();
11434 Register Dest = MI.getOperand(0).getReg();
11435 Register Src1 = MI.getOperand(1).getReg();
11436 Register Src2 = MI.getOperand(2).getReg();
11471 .addReg(MI.getOperand(1).getReg())
11474 MI.getOperand(0).getReg())
11482 MI.getOperand(0).getReg())
11489 MI.getOperand(0).getReg())
11493 Register OldFPSCRReg = MI.getOperand(0).getReg();
11574 Register OldFPSCRReg = MI.getOperand(0).getReg();
lib/Target/PowerPC/PPCInstrInfo.cpp 186 Register Reg = DefMO.getReg();
291 SrcReg = MI.getOperand(1).getReg();
292 DstReg = MI.getOperand(0).getReg();
310 return MI.getOperand(0).getReg();
362 return MI.getOperand(0).getReg();
395 Register Reg0 = MI.getOperand(0).getReg();
396 Register Reg1 = MI.getOperand(1).getReg();
397 Register Reg2 = MI.getOperand(2).getReg();
425 Register Reg0 = ChangeReg0 ? Reg2 : MI.getOperand(0).getReg();
720 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
720 else if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
737 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
737 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
764 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
764 if (Cond[1].getReg() == PPC::CTR || Cond[1].getReg() == PPC::CTR8)
874 .addReg(Cond[1].getReg(), 0, SubIdx);
1316 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1316 if (Cond[1].getReg() == PPC::CTR8 || Cond[1].getReg() == PPC::CTR)
1349 UseMI.getOperand(UseIdx).getReg() == Reg)
1441 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1441 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1460 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1460 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR) {
1494 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1494 if (Pred[1].getReg() == PPC::CTR8 || Pred[1].getReg() == PPC::CTR)
1528 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1528 if (Pred1[1].getReg() == PPC::CTR8 || Pred1[1].getReg() == PPC::CTR)
1530 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1530 if (Pred2[1].getReg() == PPC::CTR8 || Pred2[1].getReg() == PPC::CTR)
1534 if (Pred1[1].getReg() != Pred2[1].getReg())
1534 if (Pred1[1].getReg() != Pred2[1].getReg())
1572 if (MO.isDef() && RC->contains(MO.getReg())) {
1617 SrcReg = MI.getOperand(1).getReg();
1628 SrcReg = MI.getOperand(1).getReg();
1629 SrcReg2 = MI.getOperand(2).getReg();
1643 Register CRReg = CmpInstr.getOperand(0).getReg();
1817 ((Instr.getOperand(1).getReg() == SrcReg &&
1818 Instr.getOperand(2).getReg() == SrcReg2) ||
1819 (Instr.getOperand(1).getReg() == SrcReg2 &&
1820 Instr.getOperand(2).getReg() == SrcReg))) {
1865 ShouldSwap = SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
1866 Sub->getOperand(2).getReg() == SrcReg;
1932 Register GPRRes = MI->getOperand(0).getReg();
2117 Register TargetReg = MI.getOperand(0).getReg();
2179 Register TargetReg = MI.getOperand(0).getReg();
2189 Register SrcReg = MI.getOperand(0).getReg();
2201 Register TargetReg = MI.getOperand(0).getReg();
2209 Register SrcReg = MI.getOperand(0).getReg();
2221 auto Val = MI.getOperand(0).getReg();
2274 Register InUseReg = MI.getOperand(OpNo).getReg();
2354 Register Reg = MI.getOperand(i).getReg();
2383 ? isVFRegister(MI.getOperand(0).getReg())
2390 MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2390 MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
2396 Register Reg = MI.getOperand(i).getReg();
2469 getRegisterInfo().regsOverlap(MO.getReg(), RegNo))
2600 unsigned ToBeChangedReg = ADDIMI->getOperand(0).getReg();
2601 unsigned ScaleReg = ADDMI->getOperand(ScaleRegIdx).getReg();
2682 if (!instrHasImmForm(XFormOpcode, isVFRegister(MI.getOperand(0).getReg()),
2701 ToBeDeletedReg = RegOperand.getReg();
2719 ADDIMI = getDefMIPostRA(MO.getReg(), *ADDMI, OtherIntermediateUse);
2767 Register ForwardingOperandReg = MI.getOperand(ForwardingOperand).getReg();
2773 ? isVFRegister(MI.getOperand(0).getReg())
2823 Register DefReg = MI.getOperand(0).getReg();
2833 Register TrueReg = CompareUseMI.getOperand(1).getReg();
2834 Register FalseReg = CompareUseMI.getOperand(2).getReg();
2965 if (MRI->hasOneUse(DefMI->getOperand(0).getReg()))
2970 else if (MRI->use_empty(MI.getOperand(0).getReg())) {
3472 if (MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO &&
3473 MI.getOperand(III.ZeroIsSpecialOrig).getReg() != PPC::ZERO8)
3518 Register Reg = RegMO.getReg();
3638 ForwardKilledOperandReg = MI.getOperand(OpNoForForwarding).getReg();
3649 MI.getOperand(III.OpNoForForwarding).ChangeToRegister(RegMO->getReg(),
3699 fixupIsDeadOrKill(DefMI, MI, RegMO->getReg());
3742 Register OrigZeroReg = MI.getOperand(PosForOrigZero).getReg();
3743 Register NewZeroReg = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3757 ForwardKilledOperandReg = MI.getOperand(ConstantOpNo).getReg();
3836 Register RegToModify = MI.getOperand(III.ZeroIsSpecialNew).getReg();
3982 Register StackReg = MI.getOperand(2).getReg();
4007 Register SrcReg = MI.getOperand(1).getReg();
4016 Register VReg = MI.getOperand(0).getReg();
4076 Register SrcReg = MI.getOperand(1).getReg();
4105 Register SrcReg = MI.getOperand(I).getReg();
4128 Register SrcReg1 = MI.getOperand(1).getReg();
4129 Register SrcReg2 = MI.getOperand(2).getReg();
4239 Register LoopCountReg = LoopInst->getOperand(0).getReg();
lib/Target/PowerPC/PPCMCInstLower.cpp 170 assert(MO.getReg() > PPC::NoRegister &&
171 MO.getReg() < PPC::NUM_TARGET_REGS &&
173 OutMO = MCOperand::createReg(MO.getReg());
lib/Target/PowerPC/PPCMIPeephole.cpp 151 Register Reg = Op->getReg();
343 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI);
345 TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI);
359 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI);
373 MI.getOperand(0).getReg())
385 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI);
387 TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI);
394 MI.getOperand(0).getReg())
407 MI.getOperand(1).setReg(DefMI->getOperand(1).getReg());
408 MI.getOperand(2).setReg(DefMI->getOperand(2).getReg());
419 MI.getOperand(0).getReg())
429 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg());
445 TRI->lookThruCopyLike(MI.getOperand(OpNo).getReg(), MRI);
455 Register ConvReg = DefMI->getOperand(1).getReg();
475 MI.getOperand(0).getReg())
483 Register ShiftRes = DefMI->getOperand(0).getReg();
484 Register ShiftOp1 = DefMI->getOperand(1).getReg();
485 Register ShiftOp2 = DefMI->getOperand(2).getReg();
508 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI);
517 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI);
519 TRI->lookThruCopyLike(DefMI->getOperand(2).getReg(), MRI);
533 MRI->hasOneNonDBGUse(RoundInstr->getOperand(0).getReg())) {
535 Register ConvReg1 = RoundInstr->getOperand(1).getReg();
536 Register FRSPDefines = RoundInstr->getOperand(0).getReg();
540 Use.getOperand(i).getReg() == FRSPDefines)
568 Register NarrowReg = MI.getOperand(1).getReg();
577 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
601 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
612 Register NarrowReg = MI.getOperand(1).getReg();
621 if (!MRI->hasOneNonDBGUse(SrcMI->getOperand(0).getReg()))
645 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg());
659 MI.getOperand(0).getReg())
681 Register SrcReg = MI.getOperand(1).getReg();
691 ImpDefMI = MRI->getVRegDef(SrcMI->getOperand(1).getReg());
692 SubRegMI = MRI->getVRegDef(SrcMI->getOperand(2).getReg());
697 Register CopyReg = SubRegMI->getOperand(1).getReg();
706 MI.getOperand(0).getReg())
726 MRI->hasOneNonDBGUse(DefPhiMI->getOperand(0).getReg());
743 || !MRI->hasOneNonDBGUse(LiMI->getOperand(0).getReg()) ||
759 Register DominatorReg = Op2.getReg();
796 MI.getOperand(0).getReg())
907 return Phi->getOperand(I-1).getReg();
928 NextReg = Inst->getOperand(1).getReg();
951 Register CndReg = (*BII).getOperand(1).getReg();
962 if (MO.isReg() && !Register::isVirtualRegister(MO.getReg()))
1013 MachineInstr *CMPI = MRI->getVRegDef(BI->getOperand(1).getReg());
1016 MachineInstr *Inst = MRI->getVRegDef(CMPI->getOperand(I).getReg());
1112 MachineInstr *CMPI1 = MRI->getVRegDef(BI1->getOperand(1).getReg());
1115 MachineInstr *CMPI2 = MRI->getVRegDef(BI2->getOperand(1).getReg());
1158 unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(),
1160 unsigned Cmp1Operand2 = getSrcVReg(CMPI1->getOperand(2).getReg(),
1162 unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(),
1164 unsigned Cmp2Operand2 = getSrcVReg(CMPI2->getOperand(2).getReg(),
1184 unsigned Cmp1Operand1 = getSrcVReg(CMPI1->getOperand(1).getReg(),
1186 unsigned Cmp2Operand1 = getSrcVReg(CMPI2->getOperand(1).getReg(),
1272 Register Op1 = CMPI2->getOperand(1).getReg();
1273 Register Op2 = CMPI2->getOperand(2).getReg();
1282 MachineInstr *Inst = MRI->getVRegDef(CMPI2->getOperand(I).getReg());
1299 .addReg(BI1->getOperand(1).getReg()).addMBB(MBB1)
1300 .addReg(BI2->getOperand(1).getReg()).addMBB(MBBtoMoveCmp);
1305 BI2->getOperand(1).setReg(BI1->getOperand(1).getReg());
1335 Register SrcReg = MI.getOperand(1).getReg();
1374 MI.getOperand(1).setReg(SrcMI->getOperand(1).getReg());
1415 Register SrcReg = MI.getOperand(1).getReg();
1432 if (!Register::isVirtualRegister(SrcMI->getOperand(1).getReg()))
1443 MI.getOperand(0).getReg())
lib/Target/PowerPC/PPCPreEmitPeephole.cpp 96 Register Reg = BBI->getOperand(0).getReg();
180 MI.getOperand(0).getReg() == MI.getOperand(1).getReg() &&
180 MI.getOperand(0).getReg() == MI.getOperand(1).getReg() &&
181 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
181 MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
189 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
189 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
226 Register CRBit = Br->getOperand(0).getReg();
234 It->getOperand(0).getReg() == CRBit)
lib/Target/PowerPC/PPCQPXLoadSplat.cpp 82 Register SplatReg = SMI->getOperand(0).getReg();
83 Register SrcReg = SMI->getOperand(1).getReg();
104 TRI->getSubRegIndex(SrcReg, MI->getOperand(0).getReg());
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 67 MachineInstr *DefMI = MRI->getVRegDef(MI.getOperand(i - 1).getReg());
99 MIB.addReg(MI.getOperand(i - 1).getReg()).addMBB(NewMBB);
221 .addReg(BSI.SplitCond->getOperand(0).getReg())
234 FirstTerminator->getOperand(0).setReg(BSI.NewCond->getOperand(0).getReg());
471 MachineInstr *Def1 = lookThroughCRCopy(MIParam.getOperand(1).getReg(),
474 MRI->hasOneNonDBGUse(Def1->getOperand(0).getReg());
476 MRI->hasOneNonDBGUse(Ret.CopyDefs.first->getOperand(0).getReg());
480 MachineInstr *Def2 = lookThroughCRCopy(MIParam.getOperand(2).getReg(),
484 MRI->hasOneNonDBGUse(Def2->getOperand(0).getReg());
486 MRI->hasOneNonDBGUse(Ret.CopyDefs.second->getOperand(0).getReg());
498 MRI->use_nodbg_instructions(MIParam.getOperand(0).getReg())) {
509 Ret.SingleUse = MRI->hasOneNonDBGUse(MIParam.getOperand(0).getReg()) ? 1 : 0;
544 Register CopySrc = Copy->getOperand(1).getReg();
657 MRI->use_nodbg_begin(CRI.MI->getOperand(0).getReg())->getParent();
lib/Target/PowerPC/PPCRegisterInfo.cpp 551 Register NegSizeReg = MI.getOperand(1).getReg();
577 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
602 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
629 MI.getOperand(0).getReg())
658 Register SrcReg = MI.getOperand(0).getReg();
703 Register DestReg = MI.getOperand(0).getReg();
747 Register SrcReg = MI.getOperand(0).getReg();
826 Register DestReg = MI.getOperand(0).getReg();
873 Register SrcReg = MI.getOperand(0).getReg();
899 Register DestReg = MI.getOperand(0).getReg();
1130 Register StackReg = MI.getOperand(FIOperandNum).getReg();
lib/Target/PowerPC/PPCTLSDynamicCall.cpp 77 Register OutReg = MI.getOperand(0).getReg();
78 Register InReg = MI.getOperand(1).getReg();
lib/Target/PowerPC/PPCVSXCopy.cpp 94 if ( IsVSReg(DstMO.getReg(), MRI) &&
95 !IsVSReg(SrcMO.getReg(), MRI)) {
100 assert((IsF8Reg(SrcMO.getReg(), MRI) ||
101 IsVSSReg(SrcMO.getReg(), MRI) ||
102 IsVSFReg(SrcMO.getReg(), MRI)) &&
115 } else if (!IsVSReg(DstMO.getReg(), MRI) &&
116 IsVSReg(SrcMO.getReg(), MRI)) {
121 assert((IsF8Reg(DstMO.getReg(), MRI) ||
122 IsVSFReg(DstMO.getReg(), MRI) ||
123 IsVSSReg(DstMO.getReg(), MRI)) &&
lib/Target/PowerPC/PPCVSXFMAMutate.cpp 111 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn();
129 Register AddendSrcReg = AddendMI->getOperand(1).getReg();
131 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) !=
137 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg())
163 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) {
185 Register OldFMAReg = MI.getOperand(0).getReg();
189 Register Reg2 = MI.getOperand(2).getReg();
190 Register Reg3 = MI.getOperand(3).getReg();
217 Register KilledProdReg = MI.getOperand(KilledProdOp).getReg();
218 Register OtherProdReg = MI.getOperand(OtherProdOp).getReg();
240 assert(OldFMAReg == AddendMI->getOperand(0).getReg() &&
263 if (OtherProdReg == AddendMI->getOperand(0).getReg()) {
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 256 Register Reg = MO.getReg();
297 unsigned trueReg1 = lookThruCopyLike(MI.getOperand(1).getReg(),
299 unsigned trueReg2 = lookThruCopyLike(MI.getOperand(2).getReg(),
322 unsigned trueReg1 = lookThruCopyLike(MI.getOperand(1).getReg(),
324 unsigned trueReg2 = lookThruCopyLike(MI.getOperand(2).getReg(),
378 if (isVecReg(MI.getOperand(0).getReg()) &&
379 isVecReg(MI.getOperand(1).getReg()))
385 else if (isScalarVecReg(MI.getOperand(0).getReg()) &&
386 isScalarVecReg(MI.getOperand(1).getReg()))
397 if (isVecReg(MI.getOperand(0).getReg()) &&
398 isVecReg(MI.getOperand(2).getReg()))
400 else if (isVecReg(MI.getOperand(0).getReg()) &&
401 isScalarVecReg(MI.getOperand(2).getReg())) {
563 CopySrcReg = MI->getOperand(1).getReg();
566 CopySrcReg = MI->getOperand(2).getReg();
604 Register Reg = MO.getReg();
670 Register DefReg = MI->getOperand(0).getReg();
698 Register UseReg = MI->getOperand(0).getReg();
700 Register DefReg = DefMI->getOperand(0).getReg();
759 Register DefReg = MI->getOperand(0).getReg();
775 Register UseReg = MI->getOperand(0).getReg();
872 Register Reg1 = MI->getOperand(1).getReg();
873 Register Reg2 = MI->getOperand(2).getReg();
897 Register DstReg = MI->getOperand(0).getReg();
952 MI->getOperand(0).getReg())
lib/Target/RISCV/RISCVAsmPrinter.cpp 116 OS << RISCVInstPrinter::getRegisterName(MO.getReg());
136 OS << "0(" << RISCVInstPrinter::getRegisterName(MO.getReg()) << ")";
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 238 Register DestReg = MI.getOperand(0).getReg();
239 Register ScratchReg = MI.getOperand(1).getReg();
240 Register AddrReg = MI.getOperand(2).getReg();
241 Register IncrReg = MI.getOperand(3).getReg();
300 Register DestReg = MI.getOperand(0).getReg();
301 Register ScratchReg = MI.getOperand(1).getReg();
302 Register AddrReg = MI.getOperand(2).getReg();
303 Register IncrReg = MI.getOperand(3).getReg();
304 Register MaskReg = MI.getOperand(4).getReg();
439 Register DestReg = MI.getOperand(0).getReg();
440 Register Scratch1Reg = MI.getOperand(1).getReg();
441 Register Scratch2Reg = MI.getOperand(2).getReg();
442 Register AddrReg = MI.getOperand(3).getReg();
443 Register IncrReg = MI.getOperand(4).getReg();
444 Register MaskReg = MI.getOperand(5).getReg();
469 insertSext(TII, DL, LoopHeadMBB, Scratch2Reg, MI.getOperand(6).getReg());
477 insertSext(TII, DL, LoopHeadMBB, Scratch2Reg, MI.getOperand(6).getReg());
552 Register DestReg = MI.getOperand(0).getReg();
553 Register ScratchReg = MI.getOperand(1).getReg();
554 Register AddrReg = MI.getOperand(2).getReg();
555 Register CmpValReg = MI.getOperand(3).getReg();
556 Register NewValReg = MI.getOperand(4).getReg();
585 Register MaskReg = MI.getOperand(5).getReg();
632 Register DestReg = MI.getOperand(0).getReg();
lib/Target/RISCV/RISCVFrameLowering.cpp 281 Register DestReg = I->getOperand(0).getReg();
lib/Target/RISCV/RISCVISelLowering.cpp 1123 Register LoReg = MI.getOperand(0).getReg();
1124 Register HiReg = MI.getOperand(1).getReg();
1159 Register LoReg = MI.getOperand(0).getReg();
1160 Register HiReg = MI.getOperand(1).getReg();
1161 Register SrcReg = MI.getOperand(2).getReg();
1191 Register DstReg = MI.getOperand(0).getReg();
1192 Register LoReg = MI.getOperand(1).getReg();
1193 Register HiReg = MI.getOperand(2).getReg();
1252 Register LHS = MI.getOperand(1).getReg();
1253 Register RHS = MI.getOperand(2).getReg();
1258 SelectDests.insert(MI.getOperand(0).getReg());
1267 if (SequenceMBBI->getOperand(1).getReg() != LHS ||
1268 SequenceMBBI->getOperand(2).getReg() != RHS ||
1270 SelectDests.count(SequenceMBBI->getOperand(4).getReg()) ||
1271 SelectDests.count(SequenceMBBI->getOperand(5).getReg()))
1275 SelectDests.insert(SequenceMBBI->getOperand(0).getReg());
1281 return MO.isReg() && MO.isUse() && SelectDests.count(MO.getReg());
1335 TII.get(RISCV::PHI), SelectMBBI->getOperand(0).getReg())
1336 .addReg(SelectMBBI->getOperand(4).getReg())
1338 .addReg(SelectMBBI->getOperand(5).getReg())
lib/Target/RISCV/RISCVInstrInfo.cpp 56 return MI.getOperand(0).getReg();
79 return MI.getOperand(2).getReg();
486 return (MI.getOperand(1).isReg() && MI.getOperand(1).getReg() == RISCV::X0);
lib/Target/RISCV/RISCVMCInstLower.cpp 99 MCOp = MCOperand::createReg(MO.getReg());
lib/Target/RISCV/RISCVMergeBaseOffset.cpp 86 !MRI->hasOneUse(HiLUI.getOperand(0).getReg()))
88 Register HiLuiDestReg = HiLUI.getOperand(0).getReg();
94 !MRI->hasOneUse(LoADDI->getOperand(0).getReg()))
110 MRI->replaceRegWith(Tail.getOperand(0).getReg(),
111 LoADDI.getOperand(0).getReg());
138 Register Rs = TailAdd.getOperand(1).getReg();
139 Register Rt = TailAdd.getOperand(2).getReg();
155 *MRI->getVRegDef(OffsetTail.getOperand(1).getReg());
159 !MRI->hasOneUse(OffsetLui.getOperand(0).getReg()))
181 Register DestReg = LoADDI.getOperand(0).getReg();
235 Register BaseAddrReg = Tail.getOperand(1).getReg();
250 Tail.getOperand(1).setReg(HiLUI.getOperand(0).getReg());
lib/Target/Sparc/DelaySlotFiller.cpp 256 Register Reg = MO.getReg();
305 RegUses.insert(Reg.getReg());
312 RegUses.insert(Operand1.getReg());
327 Register Reg = MO.getReg();
383 Register reg = AddMI->getOperand(0).getReg();
411 Register reg = OrMI->getOperand(0).getReg();
417 && OrMI->getOperand(1).getReg() != SP::G0
418 && OrMI->getOperand(2).getReg() != SP::G0)
422 && OrMI->getOperand(1).getReg() != SP::G0
449 Register reg = SetHiMI->getOperand(0).getReg();
489 && MBBI->getOperand(0).getReg() == SP::G0
490 && MBBI->getOperand(1).getReg() == SP::G0
491 && MBBI->getOperand(2).getReg() == SP::G0);
lib/Target/Sparc/SparcAsmPrinter.cpp 176 assert(MO.getReg() != SP::O7 &&
179 MCOperand MCRegOP = MCOperand::createReg(MO.getReg());
351 O << "%" << StringRef(getRegisterName(MO.getReg())).lower();
394 MI->getOperand(opNum+1).getReg() == SP::G0)
lib/Target/Sparc/SparcISelLowering.cpp 3162 MI.getOperand(0).getReg())
3163 .addReg(MI.getOperand(1).getReg())
3165 .addReg(MI.getOperand(2).getReg())
lib/Target/Sparc/SparcInstrInfo.cpp 51 return MI.getOperand(0).getReg();
70 return MI.getOperand(2).getReg();
lib/Target/Sparc/SparcMCInstLower.cpp 75 return MCOperand::createReg(MO.getReg());
lib/Target/Sparc/SparcRegisterInfo.cpp 185 Register SrcReg = MI.getOperand(2).getReg();
197 Register DestReg = MI.getOperand(0).getReg();
lib/Target/SystemZ/SystemZAsmPrinter.cpp 34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg()))
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg()))
61 .addReg(MI->getOperand(0).getReg())
62 .addReg(MI->getOperand(1).getReg())
63 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()))
108 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
109 .addReg(MI->getOperand(1).getReg())
111 .addReg(MI->getOperand(3).getReg());
118 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
119 .addReg(MI->getOperand(1).getReg())
121 .addReg(MI->getOperand(3).getReg())
142 .addReg(MI->getOperand(0).getReg())
143 .addReg(MI->getOperand(1).getReg())
151 .addReg(MI->getOperand(0).getReg())
152 .addReg(MI->getOperand(1).getReg())
160 .addReg(MI->getOperand(0).getReg())
169 .addReg(MI->getOperand(0).getReg())
178 .addReg(MI->getOperand(0).getReg())
179 .addReg(MI->getOperand(1).getReg())
187 .addReg(MI->getOperand(0).getReg())
188 .addReg(MI->getOperand(1).getReg())
196 .addReg(MI->getOperand(0).getReg())
205 .addReg(MI->getOperand(0).getReg())
221 .addReg(MI->getOperand(0).getReg());
249 .addReg(MI->getOperand(0).getReg())
250 .addReg(MI->getOperand(1).getReg())
258 .addReg(MI->getOperand(0).getReg())
259 .addReg(MI->getOperand(1).getReg())
267 .addReg(MI->getOperand(0).getReg())
276 .addReg(MI->getOperand(0).getReg())
285 .addReg(MI->getOperand(0).getReg())
286 .addReg(MI->getOperand(1).getReg())
294 .addReg(MI->getOperand(0).getReg())
295 .addReg(MI->getOperand(1).getReg())
303 .addReg(MI->getOperand(0).getReg())
312 .addReg(MI->getOperand(0).getReg())
335 .addReg(MI->getOperand(0).getReg())
341 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg()))
347 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg()))
363 .addReg(MI->getOperand(0).getReg())
364 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(1).getReg()))
365 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(2).getReg()));
371 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
372 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()));
413 .addReg(SystemZMC::getRegAsGR64(MI->getOperand(0).getReg()))
414 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()))
420 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
421 .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
422 .addReg(MI->getOperand(1).getReg())
617 ScratchReg = MI.getOperand(ScratchIdx).getReg();
697 SystemZInstPrinter::printAddress(MI->getOperand(OpNo).getReg(),
699 MI->getOperand(OpNo + 2).getReg(), OS);
lib/Target/SystemZ/SystemZElimCompare.cpp 129 if (MI.getOperand(1).getReg() == Reg)
140 MI.getOperand(0).isDef() && MI.getOperand(0).getReg() == Reg)
155 if (Register MOReg = MO.getReg()) {
184 reg = Compare.getOperand(0).getReg();
186 reg = Compare.getOperand(1).getReg();
525 Register SrcReg = Compare.getOperand(0).getReg();
527 Compare.getOperand(1).isReg() ? Compare.getOperand(1).getReg() : Register();
lib/Target/SystemZ/SystemZFrameLowering.cpp 500 emitIncrement(MBB, MBBI, DL, MBBI->getOperand(AddrOpNo).getReg(),
lib/Target/SystemZ/SystemZISelLowering.cpp 6505 return Base.getReg();
6589 Register DestReg = MI->getOperand(0).getReg();
6590 Register TrueReg = MI->getOperand(1).getReg();
6591 Register FalseReg = MI->getOperand(2).getReg();
6652 if (NextMIIt->readsVirtualRegister(SelMI->getOperand(0).getReg())) {
6721 Register SrcReg = MI.getOperand(0).getReg();
6724 Register IndexReg = MI.getOperand(3).getReg();
6816 Register Dest = MI.getOperand(0).getReg();
6820 Register BitShift = IsSubWord ? MI.getOperand(4).getReg() : Register();
6821 Register NegBitShift = IsSubWord ? MI.getOperand(5).getReg() : Register();
6842 MRI.createVirtualRegister(RC) : Src2.getReg());
6899 .addReg(RotatedOldVal).addReg(Src2.getReg())
6934 Register Dest = MI.getOperand(0).getReg();
6937 Register Src2 = MI.getOperand(3).getReg();
6938 Register BitShift = (IsSubWord ? MI.getOperand(4).getReg() : Register());
6939 Register NegBitShift = (IsSubWord ? MI.getOperand(5).getReg() : Register());
7048 Register Dest = MI.getOperand(0).getReg();
7051 Register OrigCmpVal = MI.getOperand(3).getReg();
7052 Register OrigSwapVal = MI.getOperand(4).getReg();
7053 Register BitShift = MI.getOperand(5).getReg();
7054 Register NegBitShift = MI.getOperand(6).getReg();
7172 Register Dest = MI.getOperand(0).getReg();
7173 Register Hi = MI.getOperand(1).getReg();
7174 Register Lo = MI.getOperand(2).getReg();
7200 Register Dest = MI.getOperand(0).getReg();
7201 Register Src = MI.getOperand(1).getReg();
7245 Register StartCountReg = MI.getOperand(5).getReg();
7410 uint64_t End1Reg = MI.getOperand(0).getReg();
7411 uint64_t Start1Reg = MI.getOperand(1).getReg();
7412 uint64_t Start2Reg = MI.getOperand(2).getReg();
7413 uint64_t CharReg = MI.getOperand(3).getReg();
7517 Register SrcReg = MI.getOperand(0).getReg();
lib/Target/SystemZ/SystemZInstrInfo.cpp 78 Register Reg128 = LowRegOp.getReg();
81 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
82 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
140 Register Reg = MI.getOperand(0).getReg();
154 Register DestReg = MI.getOperand(0).getReg();
155 Register SrcReg = MI.getOperand(1).getReg();
177 Register Reg = MI.getOperand(0).getReg();
189 Register Reg = MI.getOperand(0).getReg();
201 MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
201 MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
214 const Register Reg64 = MI->getOperand(0).getReg();
313 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
315 return MI.getOperand(0).getReg();
523 SrcReg = MI.getOperand(0).getReg();
615 if (DefMI.getOperand(0).getReg() != Reg)
632 if (UseMI.getOperand(2).getReg() == Reg)
634 else if (UseMI.getOperand(1).getReg() == Reg)
646 if (UseMI.getOperand(2).getReg() == Reg)
648 else if (UseMI.getOperand(1).getReg() == Reg)
906 MI->getOperand(3).getReg() == 0);
977 .addReg(Src.getReg(), getKillRegState(Src.isKill()),
987 LV->replaceKillInstruction(Op.getReg(), MI, *MIB);
1008 isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
1040 .getRegClass(MI.getOperand(OpNum).getReg())) &&
1168 Register DstReg = MI.getOperand(0).getReg();
1171 Register SrcReg = (OpNum == 2 ? MI.getOperand(1).getReg()
1173 ? MI.getOperand(2).getReg()
1372 bool DestIsHigh = SystemZ::isHighReg(MI.getOperand(0).getReg());
1373 bool SrcIsHigh = SystemZ::isHighReg(MI.getOperand(2).getReg());
1616 if (!(MI && MI->getOperand(3).getReg() == 0))
lib/Target/SystemZ/SystemZMCInstLower.cpp 82 return MCOperand::createReg(MO.getReg());
lib/Target/SystemZ/SystemZPostRewrite.cpp 89 Register DestReg = MBBI->getOperand(0).getReg();
90 Register SrcReg = MBBI->getOperand(2).getReg();
110 Register DestReg = MBBI->getOperand(0).getReg();
111 Register Src1Reg = MBBI->getOperand(1).getReg();
112 Register Src2Reg = MBBI->getOperand(2).getReg();
124 .addReg(MBBI->getOperand(1).getReg(), getRegState(MBBI->getOperand(1)));
131 .addReg(MBBI->getOperand(2).getReg(), getRegState(MBBI->getOperand(2)));
164 Register DestReg = MI.getOperand(0).getReg();
165 Register SrcReg = MI.getOperand(2).getReg();
168 assert(DestReg == MI.getOperand(1).getReg() &&
201 .addReg(MI.getOperand(2).getReg(), getRegState(MI.getOperand(2)));
225 Register DstReg = MI.getOperand(0).getReg();
227 if (DstReg != SrcMO.getReg()) {
229 .addReg(SrcMO.getReg());
lib/Target/SystemZ/SystemZRegisterInfo.cpp 32 const TargetRegisterClass *RC = MRI->getRegClass(MO.getReg());
43 if (VRM && VRM->hasPhys(MO.getReg())) {
44 Register PhysReg = VRM->getPhys(MO.getReg());
124 (TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
124 (TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
124 (TrueMO.getReg() == Reg ? FalseMO.getReg() : TrueMO.getReg());
156 if (VirtReg == Use.getOperand(0).getReg()) {
161 } else if (VirtReg == Use.getOperand(1).getReg()) {
164 } else if (VirtReg == Use.getOperand(2).getReg() && Use.isCommutable()) {
171 Register Reg = MO->getReg();
306 && MI->getOperand(FIOperandNum + 2).getReg() == 0) {
355 Register GR128Reg = MI->getOperand(WideOpNo).getReg();
356 Register GRNarReg = MI->getOperand((WideOpNo == 1) ? 0 : 1).getReg();
389 if (MO.isReg() && Register::isPhysicalRegister(MO.getReg())) {
390 for (MCSuperRegIterator SI(MO.getReg(), this, true/*IncludeSelf*/);
lib/Target/SystemZ/SystemZShortenInst.cpp 78 Register Reg = MI.getOperand(0).getReg();
110 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) {
120 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
121 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
132 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
133 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
133 MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
134 SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) {
158 if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
159 SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
182 if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
182 if (MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
187 if (MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
187 if (MI.getOperand(0).getReg() == MI.getOperand(2).getReg()) {
338 if ((MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) &&
338 if ((MI.getOperand(0).getReg() != MI.getOperand(1).getReg()) &&
340 MI.getOperand(0).getReg() != MI.getOperand(2).getReg() ||
340 MI.getOperand(0).getReg() != MI.getOperand(2).getReg() ||
lib/Target/WebAssembly/WebAssemblyAsmPrinter.cpp 70 Register RegNo = MO.getReg();
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 716 if (!MO.isReg() || Register::isPhysicalRegister(MO.getReg()))
718 if (MachineInstr *Def = MRI.getUniqueVRegDef(MO.getReg()))
720 MFI.unstackifyVReg(MO.getReg());
1019 ExnReg = Catch->getOperand(0).getReg();
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 171 Register Reg = MO.getReg();
210 Register Reg = MI.getOperand(0).getReg();
239 assert(MFI.isVRegStackified(MI.getOperand(0).getReg()));
240 assert(!MFI.isVRegStackified(MI.getOperand(1).getReg()));
241 Register OldReg = MI.getOperand(2).getReg();
257 getLocalId(Reg2Local, CurLocal, MI.getOperand(1).getReg());
260 MI.getOperand(0).getReg())
262 .addReg(MI.getOperand(2).getReg());
273 Register OldReg = MI.getOperand(0).getReg();
313 Register OldReg = MO.getReg();
360 MRI.replaceRegWith(MI.getOperand(1).getReg(),
361 MI.getOperand(0).getReg());
390 (!MO.isReg() || MRI.use_empty(MO.getReg()) ||
391 MFI.isVRegStackified(MO.getReg())) &&
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 338 Register OutReg = MI.getOperand(0).getReg();
339 Register InReg = MI.getOperand(1).getReg();
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp 92 if (MFI.isVRegStackified(MI.getOperand(OpIdx1).getReg()) ||
93 MFI.isVRegStackified(MI.getOperand(OpIdx2).getReg()))
196 bool IsBrOnExn = Cond[1].isReg() && MRI.getRegClass(Cond[1].getReg()) ==
227 MRI.getRegClass(Cond[1].getReg()) == &WebAssembly::EXNREFRegClass)
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 172 Register ExnReg = Catch->getOperand(0).getReg();
297 Register ExnReg = Catch->getOperand(0).getReg();
lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp 71 Register Cond = MI->getOperand(1).getReg();
178 Cond = Def->getOperand(1).getReg();
lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp 228 unsigned WAReg = MFI.getWAReg(MO.getReg());
242 Returns.push_back(getType(MRI.getRegClass(MO.getReg())));
245 Params.push_back(getType(MRI.getRegClass(MO.getReg())));
lib/Target/WebAssembly/WebAssemblyMemIntrinsicResults.cpp 169 Register FromReg = MI.getOperand(2).getReg();
170 Register ToReg = MI.getOperand(0).getReg();
lib/Target/WebAssembly/WebAssemblyOptimizeLiveIntervals.cpp 99 LiveInterval &LI = LIS.getInterval(MI->getOperand(0).getReg());
lib/Target/WebAssembly/WebAssemblyPeephole.cpp 94 Register Reg = MO.getReg();
167 Register OldReg = MO.getReg();
168 Register NewReg = Op2.getReg();
lib/Target/WebAssembly/WebAssemblyRegNumbering.cpp 79 LLVM_DEBUG(dbgs() << "Arg VReg " << MI.getOperand(0).getReg()
81 MFI.setWAReg(MI.getOperand(0).getReg(), Imm);
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 105 const auto *RegClass = MRI.getRegClass(MI->getOperand(0).getReg());
337 Register Reg = MO.getReg();
392 if (MO.isReg() && MO.isDef() && MO.getReg() == Reg)
439 Register DefReg = MO.getReg();
712 if (MO.isReg() && MO.getReg() == Reg)
810 Register Reg = Op.getReg();
918 Register Reg = MO.getReg();
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 94 Register OtherMOReg = OtherMO.getReg();
101 MRI.hasOneNonDBGUse(Def->getOperand(0).getReg())) {
lib/Target/WebAssembly/WebAssemblyUtilities.cpp 35 Register Reg = MO.getReg();
lib/Target/X86/X86AsmPrinter.cpp 211 O << X86ATTInstPrinter::getRegisterName(MO.getReg());
245 Register Reg = MO.getReg();
283 bool HasBaseReg = BaseReg.getReg() != 0;
285 BaseReg.getReg() == X86::RIP)
289 bool HasParenPart = IndexReg.getReg() || HasBaseReg;
310 assert(IndexReg.getReg() != X86::ESP &&
317 if (IndexReg.getReg()) {
332 if (Segment.getReg()) {
348 if (SegReg.getReg()) {
356 if (BaseReg.getReg()) {
361 if (IndexReg.getReg()) {
374 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
374 if (DispVal || (!IndexReg.getReg() && !BaseReg.getReg())) {
391 Register Reg = MO.getReg();
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 318 if (!((Base.isReg() && Base.getReg() != X86::NoRegister) || Base.isFI()))
324 if (!(Index.isReg() && Index.getReg() == X86::NoRegister))
326 if (!(Segment.isReg() && Segment.getReg() == X86::NoRegister))
541 int DefVR = MI.getOperand(0).getReg();
623 return LoadBase.getReg() == StoreBase.getReg();
623 return LoadBase.getReg() == StoreBase.getReg();
lib/Target/X86/X86CallFrameOptimization.cpp 338 Register Reg = MO.getReg();
395 J->getOperand(1).getReg() == StackPtr) {
398 StackPtr = Context.SPCopy->getOperand(0).getReg();
428 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) ||
431 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) ||
432 (I->getOperand(X86::AddrSegmentReg).getReg() != X86::NoRegister) ||
456 Register Reg = MO.getReg();
537 Register Reg = PushOp.getReg();
590 if (Context.SPCopy && MRI->use_empty(Context.SPCopy->getOperand(0).getReg()))
lib/Target/X86/X86CallLowering.cpp 142 ExtReg = MIB->getOperand(0).getReg();
lib/Target/X86/X86CmovConversion.cpp 321 MRI->use_nodbg_instructions(I.defs().begin()->getReg()),
439 Register Reg = MO.getReg();
459 Register Reg = MO.getReg();
537 auto UIs = MRI->use_instructions(MI->defs().begin()->getReg());
714 MI.getOperand(X86::getCondFromCMov(MI) == CC ? 1 : 2).getReg();
722 FalseBBRegRewriteTable[MI.getOperand(0).getReg()] = FalseReg;
755 const TargetRegisterClass *RC = MRI->getRegClass(MI.getOperand(0).getReg());
784 auto It = FalseBBRegRewriteTable.find(MOp.getReg());
801 FalseBBRegRewriteTable[NewCMOV->getOperand(0).getReg()] = TmpReg;
813 Register DestReg = MIIt->getOperand(0).getReg();
814 Register Op1Reg = MIIt->getOperand(1).getReg();
815 Register Op2Reg = MIIt->getOperand(2).getReg();
lib/Target/X86/X86CondBrFolding.cpp 466 SrcReg = MI.getOperand(SrcRegIndex).getReg();
lib/Target/X86/X86DomainReassignment.cpp 146 !TII->get(DstOpcode).hasImplicitDefOfPhysReg(MO.getReg()))
222 Register DstReg = MI->getOperand(0).getReg();
227 Register SrcReg = MI->getOperand(1).getReg();
244 if (Register::isPhysicalRegister(MO.getReg()))
247 RegDomain OpDomain = getDomain(MRI->getRegClass(MO.getReg()),
541 if (Op.isReg() && Op.getReg() == Reg)
579 visitRegister(C, Op.getReg(), Domain, Worklist);
596 Register DefReg = DefOp.getReg();
lib/Target/X86/X86EvexToVex.cpp 134 Register Reg = MO.getReg();
lib/Target/X86/X86ExpandPseudo.cpp 91 MBB->addLiveIn(Selector.getReg());
294 .addReg(DestAddr.getReg());
351 Register SaveRbx = MBBI->getOperand(7).getReg();
357 TII->copyPhysReg(MBB, MBBI, DL, ActualInArg, InArg.getReg(),
lib/Target/X86/X86FastISel.cpp 3957 if (!MO.isReg() || MO.isDef() || MO.getReg() != AM.IndexReg)
3961 MO.getReg(), OperandNo);
3962 if (IndexReg == MO.getReg())
lib/Target/X86/X86FixupBWInsts.cpp 181 Register OrigDestReg = OrigMI->getOperand(0).getReg();
255 if (MO.isDef() && TRI->isSuperRegisterEq(OrigDestReg, MO.getReg()))
262 if (MO.isUse() && !TRI->isSubRegisterEq(OrigDestReg, MO.getReg()) &&
263 TRI->regsOverlap(SuperDestReg, MO.getReg()))
308 Register NewSrcReg = getX86SubSuperRegister(OldSrc.getReg(), 32);
313 if (TRI->getSubRegIndex(NewSrcReg, OldSrc.getReg()) !=
314 TRI->getSubRegIndex(NewDestReg, OldDest.getReg()))
325 .addReg(OldSrc.getReg(), RegState::Implicit);
329 if (Op.getReg() != (Op.isDef() ? NewDestReg : NewSrcReg))
345 MI->getOperand(0).getReg() == X86::AX &&
346 MI->getOperand(1).getReg() == X86::AL)
lib/Target/X86/X86FixupLEAs.cpp 245 if (opnd.isReg() && opnd.getReg() == p.getReg()) {
245 if (opnd.isReg() && opnd.getReg() == p.getReg()) {
306 return Base.isReg() && isInefficientLEAReg(Base.getReg()) && Index.isReg() &&
307 Index.getReg() != X86::NoRegister;
363 if (Segment.getReg() != 0 || !Disp.isImm() || Scale.getImm() > 1 ||
367 Register DestReg = MI.getOperand(0).getReg();
368 Register BaseReg = Base.getReg();
369 Register IndexReg = Index.getReg();
397 .addReg(Base.getReg(), RegState::Implicit)
398 .addReg(Index.getReg(), RegState::Implicit);
417 .addReg(BaseReg).addReg(Base.getReg(), RegState::Implicit);
428 .addReg(Base.getReg(), RegState::Implicit);
451 if (p.isReg() && p.getReg() != X86::ESP) {
455 if (q.isReg() && q.getReg() != X86::ESP) {
492 if (Segment.getReg() != 0 || !Offset.isImm() ||
495 const Register DstR = Dst.getReg();
496 const Register SrcR1 = Base.getReg();
497 const Register SrcR2 = Index.getReg();
544 Segment.getReg() != X86::NoRegister)
547 Register DestReg = Dest.getReg();
548 Register BaseReg = Base.getReg();
549 Register IndexReg = Index.getReg();
586 .addReg(Base.getReg(), RegState::Implicit)
587 .addReg(Index.getReg(), RegState::Implicit);
lib/Target/X86/X86FixupSetCC.cpp 81 if (Op.isReg() && (Op.getReg() == X86::EFLAGS) && Op.isDef())
89 if (Op.isReg() && (Op.getReg() == X86::EFLAGS) && Op.isUse())
111 for (auto &Use : MRI->use_instructions(MI.getOperand(0).getReg()))
151 .addReg(MI.getOperand(0).getReg())
153 MRI->replaceRegWith(ZExt->getOperand(0).getReg(), InsertReg);
lib/Target/X86/X86FlagsCopyLowering.cpp 361 MI.getOperand(0).getReg() == X86::EFLAGS)
370 MachineInstr &CopyDefI = *MRI->getVRegDef(VOp.getReg());
397 if (MRI->use_empty(CopyDefI.getOperand(0).getReg()))
404 assert(DOp.getReg() == X86::EFLAGS && "Unexpected copy def register!");
703 (MI.getOperand(0).getReg() == X86::EFLAGS ||
704 MI.getOperand(1).getReg() == X86::EFLAGS)) {
726 Register::isVirtualRegister(MI.getOperand(0).getReg())) {
729 CondRegs[Cond] = MI.getOperand(0).getReg();
881 MRI->replaceRegWith(MI.getOperand(0).getReg(),
882 CopyDefI.getOperand(0).getReg());
904 MRI->replaceRegWith(SetBI.getOperand(0).getReg(), Reg);
909 auto &SetBRC = *MRI->getRegClass(SetBI.getOperand(0).getReg());
1029 MRI->replaceRegWith(SetCCI.getOperand(0).getReg(), CondReg);
lib/Target/X86/X86FloatingPoint.cpp 291 Register DstReg = MI.getOperand(0).getReg();
292 Register SrcReg = MI.getOperand(1).getReg();
316 Register Reg = MO.getReg();
429 X86::RFP80RegClass.contains(MI.getOperand(0).getReg()))
451 DeadRegs.push_back(MO.getReg());
981 unsigned R = MO.getReg() - X86::FP0;
1019 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1019 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1026 MI.killsRegister(Op.getReg())) && // Later use is marked kill.
1456 bool KillsSrc = MI.killsRegister(MO1.getReg());
1478 unsigned Reg = MI.getOperand(0).getReg() - X86::FP0;
1535 unsigned STReg = MO.getReg() - X86::FP0;
1604 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1604 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1633 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1633 if (!Op.isReg() || Op.getReg() < X86::FP0 || Op.getReg() > X86::FP6)
1702 unsigned Reg = MO.getReg() - X86::FP0;
1709 if (!LPR.contains(MO.getReg()))
1716 if (Defs.test(getFPReg(*MO)) || !LPR.contains(MO->getReg()))
lib/Target/X86/X86FrameLowering.cpp 179 Register Reg = MO.getReg();
219 Register Reg = MO.getReg();
423 PI->getOperand(0).getReg() == StackPtr){
424 assert(PI->getOperand(1).getReg() == StackPtr);
427 PI->getOperand(0).getReg() == StackPtr &&
428 PI->getOperand(1).getReg() == StackPtr &&
430 PI->getOperand(3).getReg() == X86::NoRegister &&
431 PI->getOperand(5).getReg() == X86::NoRegister) {
436 PI->getOperand(0).getReg() == StackPtr) {
437 assert(PI->getOperand(1).getReg() == StackPtr);
1188 Register Reg = MBBI->getOperand(0).getReg();
2764 TRI->isSuperOrSubRegisterEq(MO.getReg(), Candidate)) {
lib/Target/X86/X86ISelLowering.cpp29212 Register DstReg = MI.getOperand(0).getReg();
29269 Register DestReg = MI.getOperand(0).getReg();
29547 Register CountReg = MI.getOperand(0).getReg();
29562 MI.getOperand(MI.getNumOperands() - 1).getReg() == X86::EFLAGS) &&
29578 .addReg(MI.getOperand(i).getReg())
29684 Register DestReg = MIIt->getOperand(0).getReg();
29685 Register Op1Reg = MIIt->getOperand(1).getReg();
29686 Register Op2Reg = MIIt->getOperand(2).getReg();
29844 Register DestReg = FirstCMOV.getOperand(0).getReg();
29845 Register Op1Reg = FirstCMOV.getOperand(1).getReg();
29846 Register Op2Reg = FirstCMOV.getOperand(2).getReg();
29856 MIB.addReg(FirstCMOV.getOperand(2).getReg()).addMBB(FirstInsertedMBB);
29860 SecondCascadedCMOV.getOperand(0).getReg())
29861 .addReg(FirstCMOV.getOperand(0).getReg());
29948 NextMIIt->getOperand(2).getReg() == MI.getOperand(2).getReg() &&
29948 NextMIIt->getOperand(2).getReg() == MI.getOperand(2).getReg() &&
29949 NextMIIt->getOperand(1).getReg() == MI.getOperand(0).getReg() &&
29949 NextMIIt->getOperand(1).getReg() == MI.getOperand(0).getReg() &&
30056 sizeVReg = MI.getOperand(1).getReg(),
30133 MI.getOperand(0).getReg())
30364 Register CalleeVReg = MI.getOperand(0).getReg();
30383 if (Reg == MO.getReg())
30485 DstReg = MI.getOperand(CurOp++).getReg();
30721 MIB.addReg(MO.getReg());
30845 MIB.addReg(MO.getReg());
30859 MIB.addReg(MO.getReg());
31138 DefRegs[MOp.getReg()] = true;
31223 assert(Push->getOperand(2).getReg() == X86::EFLAGS &&
31226 assert(Push->getOperand(3).getReg() == X86::DF &&
31229 BuildMI(*BB, MI, DL, TII->get(Pop), MI.getOperand(0).getReg());
31241 BuildMI(*BB, MI, DL, TII->get(Push)).addReg(MI.getOperand(0).getReg());
31306 .addReg(MI.getOperand(X86::AddrNumOperands).getReg());
lib/Target/X86/X86InsertPrefetch.cpp 82 Register BaseReg = MI.getOperand(Op + X86::AddrBaseReg).getReg();
83 Register IndexReg = MI.getOperand(Op + X86::AddrIndexReg).getReg();
225 MIB.addReg(Current->getOperand(MemOpOffset + X86::AddrBaseReg).getReg())
229 Current->getOperand(MemOpOffset + X86::AddrIndexReg).getReg())
233 .getReg());
lib/Target/X86/X86InstrBuilder.h 98 AM.Base.Reg = Op0.getReg();
108 AM.IndexReg = Op2.getReg();
lib/Target/X86/X86InstrInfo.cpp 112 SrcReg = MI.getOperand(1).getReg();
113 DstReg = MI.getOperand(0).getReg();
200 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
407 return MI.getOperand(0).getReg();
442 return MI.getOperand(X86::AddrNumOperands).getReg();
603 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
605 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
622 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
627 Register BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
668 NewMI.substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
676 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
715 Register SrcReg = Src.getReg();
737 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
766 *RegInfo.getRegClass(MI.getOperand(0).getReg())) == 16) &&
791 Register Dest = MI.getOperand(0).getReg();
792 Register Src = MI.getOperand(1).getReg();
834 Register Src2 = MI.getOperand(2).getReg();
928 if (Register::isVirtualRegister(Src.getReg()) &&
929 !MF.getRegInfo().constrainRegClass(Src.getReg(),
965 if (ImplicitOp.getReg() != 0)
997 if (ImplicitOp.getReg() != 0)
1019 if (ImplicitOp.getReg() != 0)
1060 if (ImplicitOp.getReg() != 0)
1062 if (ImplicitOp2.getReg() != 0)
1103 if (ImplicitOp.getReg() != 0)
1144 if (ImplicitOp.getReg() != 0)
1320 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
1322 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
1947 Register Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
1959 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
3212 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
3287 SrcReg = MI.getOperand(0).getReg();
3301 SrcReg = MI.getOperand(1).getReg();
3310 SrcReg = MI.getOperand(1).getReg();
3311 SrcReg2 = MI.getOperand(2).getReg();
3322 SrcReg = MI.getOperand(1).getReg();
3335 SrcReg = MI.getOperand(0).getReg();
3336 SrcReg2 = MI.getOperand(1).getReg();
3344 SrcReg = MI.getOperand(0).getReg();
3345 if (MI.getOperand(1).getReg() != SrcReg)
3370 ((OI.getOperand(1).getReg() == SrcReg &&
3371 OI.getOperand(2).getReg() == SrcReg2) ||
3372 (OI.getOperand(1).getReg() == SrcReg2 &&
3373 OI.getOperand(2).getReg() == SrcReg)))
3388 OI.getOperand(1).getReg() == SrcReg &&
3574 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
3631 J->getOperand(1).getReg() == SrcReg) {
3694 (SrcReg2 != 0 && Sub && Sub->getOperand(1).getReg() == SrcReg2 &&
3695 Sub->getOperand(2).getReg() == SrcReg);
3850 Register Reg = MO.getReg();
3880 Register Reg = MIB->getOperand(0).getReg();
3887 assert(MIB->getOperand(1).getReg() == Reg &&
3888 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
3910 Register Reg = MIB->getOperand(0).getReg();
3954 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
3986 Register Reg = MIB->getOperand(0).getReg();
4024 Register DestReg = MIB->getOperand(0).getReg();
4047 Register SrcReg = MIB->getOperand(X86::AddrNumOperands).getReg();
4070 MIB.addReg(MIB->getOperand(1).getReg(),
4108 Register SrcReg = MIB->getOperand(0).getReg();
4120 Register SrcReg = MIB->getOperand(0).getReg();
4134 Register SrcReg = MIB->getOperand(0).getReg();
4157 Register Reg = MIB->getOperand(0).getReg();
4164 Register Reg = MIB->getOperand(0).getReg();
4174 Register Reg = MIB->getOperand(0).getReg();
4175 Register MaskReg = MIB->getOperand(1).getReg();
4212 Register Reg = MIB->getOperand(0).getReg();
4348 Register Reg = MO.getReg();
4561 if (MO.isUndef() && Register::isPhysicalRegister(MO.getReg())) {
4569 Register Reg = MI.getOperand(OpNum).getReg();
4643 Register Reg = MO.getReg();
4817 MachineInstr *VRegDef = RegInfo.getUniqueVRegDef(MI.getOperand(1).getReg());
4876 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
4876 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
4928 Register DstReg = NewMI->getOperand(0).getReg();
4943 Register Reg0 = HasDef ? MI.getOperand(0).getReg() : Register();
4944 Register Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
4945 Register Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
5077 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg());
5539 MIB.addReg(ImpOp.getReg(),
5571 MO1.ChangeToRegister(MO0.getReg(), false);
6657 if (RI.getEncodingValue(MI.getOperand(0).getReg()) >= 16)
6659 if (RI.getEncodingValue(MI.getOperand(1).getReg()) >= 16)
6663 RI.getEncodingValue(MI.getOperand(2).getReg()) >= 16)
6675 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6675 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6793 MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
6793 MI.getOperand(1).getReg() == MI.getOperand(2).getReg() &&
7247 Inst.getOperand(3).getReg() == X86::EFLAGS &&
7578 assert(Op2.isReg() && (Op2.getReg() == X86::NoRegister ||
7579 Register::isPhysicalRegister(Op2.getReg())));
7583 if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
7583 if ((Op1.isReg() && Op1.getReg() == MI.getOperand(0).getReg()) ||
7584 Op2.getReg() == MI.getOperand(0).getReg())
7584 Op2.getReg() == MI.getOperand(0).getReg())
7586 else if ((Op1.isReg() && Op1.getReg() != X86::NoRegister &&
7587 TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) ||
7587 TRI->regsOverlap(Op1.getReg(), MI.getOperand(0).getReg())) ||
7588 (Op2.getReg() != X86::NoRegister &&
7589 TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg())))
7589 TRI->regsOverlap(Op2.getReg(), MI.getOperand(0).getReg())))
7596 if ((Op1.isReg() && Op1.getReg() != X86::NoRegister)) {
7601 if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
7601 if (Op && Op->isReg() && Op->getReg() == Op2.getReg() && Coef > 0) {
7606 if (Op && Op2.getReg() != X86::NoRegister) {
7607 int dwarfReg = TRI->getDwarfRegNum(Op2.getReg(), false);
7619 assert(Op2.getReg() != X86::NoRegister);
7624 assert(Op2.getReg() != X86::NoRegister);
7630 if (((Op1.isReg() && Op1.getReg() != X86::NoRegister) || Op1.isFI()) &&
7631 Op2.getReg() != X86::NoRegister) {
7646 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
7646 if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg())
7675 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7677 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7683 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7685 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
lib/Target/X86/X86InstructionSelector.cpp 232 Register DstReg = I.getOperand(0).getReg();
236 Register SrcReg = I.getOperand(1).getReg();
476 assert(MRI.getType(I.getOperand(0).getReg()).isPointer() &&
480 if (auto COff = getConstantVRegVal(I.getOperand(2).getReg(), MRI)) {
484 AM.Base.Reg = I.getOperand(1).getReg();
495 AM.Base.Reg = I.getOperand(0).getReg();
506 const Register DefReg = I.getOperand(0).getReg();
533 X86SelectAddress(*MRI.getVRegDef(I.getOperand(1).getReg()), MRI, AM);
566 const Register DefReg = I.getOperand(0).getReg();
619 const Register DefReg = I.getOperand(0).getReg();
638 const Register DefReg = I.getOperand(0).getReg();
711 const Register DstReg = I.getOperand(0).getReg();
712 const Register SrcReg = I.getOperand(1).getReg();
775 const Register DstReg = I.getOperand(0).getReg();
776 const Register SrcReg = I.getOperand(1).getReg();
886 const Register DstReg = I.getOperand(0).getReg();
887 const Register SrcReg = I.getOperand(1).getReg();
946 Register LHS = I.getOperand(2).getReg();
947 Register RHS = I.getOperand(3).getReg();
978 TII.get(X86::SETCCr), I.getOperand(0).getReg()).addImm(CC);
992 Register LhsReg = I.getOperand(2).getReg();
993 Register RhsReg = I.getOperand(3).getReg();
1027 Register ResultReg = I.getOperand(0).getReg();
1083 const Register DstReg = I.getOperand(0).getReg();
1084 const Register CarryOutReg = I.getOperand(1).getReg();
1085 const Register Op0Reg = I.getOperand(2).getReg();
1086 const Register Op1Reg = I.getOperand(3).getReg();
1087 Register CarryInReg = I.getOperand(4).getReg();
1097 CarryInReg = Def->getOperand(1).getReg();
1143 const Register DstReg = I.getOperand(0).getReg();
1144 const Register SrcReg = I.getOperand(1).getReg();
1275 const Register DstReg = I.getOperand(0).getReg();
1276 const Register SrcReg = I.getOperand(1).getReg();
1277 const Register InsertReg = I.getOperand(2).getReg();
1335 Register SrcReg = I.getOperand(NumDefs).getReg();
1336 unsigned DefSize = MRI.getType(I.getOperand(0).getReg()).getSizeInBits();
1341 TII.get(TargetOpcode::G_EXTRACT), I.getOperand(Idx).getReg())
1360 Register DstReg = I.getOperand(0).getReg();
1361 Register SrcReg0 = I.getOperand(1).getReg();
1372 if (!emitInsertSubreg(DefReg, I.getOperand(1).getReg(), I, MRI, MF))
1382 .addReg(I.getOperand(Idx).getReg())
1407 const Register CondReg = I.getOperand(0).getReg();
1434 const Register DstReg = I.getOperand(0).getReg();
1495 Register DstReg = I.getOperand(0).getReg();
1526 const Register DstReg = I.getOperand(0).getReg();
1527 const Register Op1Reg = I.getOperand(1).getReg();
1528 const Register Op2Reg = I.getOperand(2).getReg();
lib/Target/X86/X86MCInstLower.cpp 408 return MCOperand::createReg(MO.getReg());
1134 CallTargetMCOp = MCOperand::createReg(CallTarget.getReg());
1159 Register DefRegister = FaultingMI.getOperand(0).getReg();
1280 Register ScratchReg = MI.getOperand(ScratchIdx).getReg();
1641 StringRef DstName = DstOp.isReg() ? GetRegisterName(DstOp.getReg()) : "mem";
1643 SrcOp1.isReg() ? GetRegisterName(SrcOp1.getReg()) : "mem";
1645 SrcOp2.isReg() ? GetRegisterName(SrcOp2.getReg()) : "mem";
1665 CS << " {%" << GetRegisterName(WriteMaskOp.getReg()) << "}";
1854 Register Reg = MI->getOperand(0).getReg();
1901 Register Reg = MI->getOperand(0).getReg();
1932 Register Reg = MI->getOperand(X86::AddrNumOperands).getReg();
1992 MCInstBuilder(X86::POP32r).addReg(MI->getOperand(0).getReg()));
2027 .addReg(MI->getOperand(0).getReg())
2028 .addReg(MI->getOperand(1).getReg())
2285 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2366 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
2476 CS << X86ATTInstPrinter::getRegisterName(DstOp.getReg()) << " = ";
lib/Target/X86/X86OptimizeLEAs.cpp 201 (!MO1.isReg() || !Register::isPhysicalRegister(MO1.getReg()));
357 MRI->getRegClass(DefMI->getOperand(0).getReg()))
425 if (MRI->getRegClass(First.getOperand(0).getReg()) !=
426 MRI->getRegClass(Last.getOperand(0).getReg()))
435 for (auto &MO : MRI->use_nodbg_operands(Last.getOperand(0).getReg())) {
546 MRI->clearKillFlags(DefMI->getOperand(0).getReg());
553 .ChangeToRegister(DefMI->getOperand(0).getReg(), false);
618 Register FirstVReg = First.getOperand(0).getReg();
619 Register LastVReg = Last.getOperand(0).getReg();
lib/Target/X86/X86RegisterBankInfo.cpp 120 OpRegBankIdx[Idx] = getPartialMappingIdx(MRI.getType(MO.getReg()), isFP);
150 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
152 if (NumOperands != 3 || (Ty != MRI.getType(MI.getOperand(1).getReg())) ||
153 (Ty != MRI.getType(MI.getOperand(2).getReg())))
188 LLT Ty = MRI.getType(MI.getOperand(0).getReg());
214 const LLT Ty0 = MRI.getType(Op0.getReg());
215 const LLT Ty1 = MRI.getType(Op1.getReg());
224 LLT Ty1 = MRI.getType(MI.getOperand(2).getReg());
225 LLT Ty2 = MRI.getType(MI.getOperand(3).getReg());
243 const LLT Ty0 = MRI.getType(Op0.getReg());
244 const LLT Ty1 = MRI.getType(Op1.getReg());
289 unsigned Size = getSizeInBits(MI.getOperand(0).getReg(), MRI, TRI);
lib/Target/X86/X86RegisterInfo.cpp 684 MI.getOperand(3).getReg() != X86::NoRegister ||
686 MI.getOperand(5).getReg() != X86::NoRegister)
688 Register BasePtr = MI.getOperand(1).getReg();
694 Register NewDestReg = MI.getOperand(0).getReg();
lib/Target/X86/X86SpeculativeLoadHardening.cpp 548 if (!Op.isReg() || Op.getReg() != PS->InitialReg)
1018 TargetReg = TI.getOperand(0).getReg();
1676 return Op.isReg() && LoadDepRegs.test(Op.getReg());
1680 LoadDepRegs.set(Def.getReg());
1720 if (!BaseMO.isFI() && BaseMO.getReg() != X86::RIP &&
1721 BaseMO.getReg() != X86::NoRegister)
1722 BaseReg = BaseMO.getReg();
1723 if (IndexMO.getReg() != X86::NoRegister)
1724 IndexReg = IndexMO.getReg();
1745 canHardenRegister(MI.getOperand(0).getReg()) &&
1749 HardenedAddrRegs.insert(MI.getOperand(0).getReg());
1763 LoadDepRegs.set(Def.getReg());
1964 } else if (BaseMO.getReg() == X86::RSP) {
1968 assert(IndexMO.getReg() == X86::NoRegister &&
1972 } else if (BaseMO.getReg() == X86::RIP ||
1973 BaseMO.getReg() == X86::NoRegister) {
1984 << (BaseMO.getReg() == X86::RIP ? "RIP-relative" : "no-base")
1992 if (IndexMO.getReg() != X86::NoRegister &&
1994 HardenOpRegs.front()->getReg() != IndexMO.getReg()))
1994 HardenOpRegs.front()->getReg() != IndexMO.getReg()))
2000 HardenOpRegs[0]->getReg() != HardenOpRegs[1]->getReg()) &&
2000 HardenOpRegs[0]->getReg() != HardenOpRegs[1]->getReg()) &&
2006 auto It = AddrRegToHardenedReg.find(Op->getReg());
2034 Register OpReg = Op->getReg();
2136 assert(!AddrRegToHardenedReg.count(Op->getReg()) &&
2138 AddrRegToHardenedReg[Op->getReg()] = TmpReg;
2156 Register DefReg = MI.getOperand(0).getReg();
2187 if ((BaseMO.isReg() && BaseMO.getReg() == DefReg) ||
2188 (IndexMO.isReg() && IndexMO.getReg() == DefReg))
2213 Register UseDefReg = UseMI.getOperand(0).getReg();
2335 Register OldDefReg = DefOp.getReg();
2617 Register OldTargetReg = TargetOp.getReg();
lib/Target/X86/X86VZeroUpper.cpp 161 if (isYmmOrZmmReg(MO.getReg()))
lib/Target/X86/X86WinAllocaExpander.cpp 84 Register AmountReg = MI->getOperand(0).getReg();
249 .addReg(MI->getOperand(0).getReg());
259 .addReg(MI->getOperand(0).getReg());
264 Register AmountReg = MI->getOperand(0).getReg();
lib/Target/XCore/XCoreAsmPrinter.cpp 208 O << XCoreInstPrinter::getRegisterName(MO.getReg());
269 << XCoreInstPrinter::getRegisterName(MI->getOperand(0).getReg()) << ", "
270 << XCoreInstPrinter::getRegisterName(MI->getOperand(1).getReg());
278 << XCoreInstPrinter::getRegisterName(MI->getOperand(1).getReg()) << '\n';
lib/Target/XCore/XCoreFrameLowering.cpp 370 Register EhStackReg = MBBI->getOperand(0).getReg();
371 Register EhHandlerReg = MBBI->getOperand(1).getReg();
lib/Target/XCore/XCoreFrameToArgsOffsetElim.cpp 58 Register Reg = OldInst.getOperand(0).getReg();
lib/Target/XCore/XCoreISelLowering.cpp 1560 .addReg(MI.getOperand(1).getReg())
1575 BuildMI(*BB, BB->begin(), dl, TII.get(XCore::PHI), MI.getOperand(0).getReg())
1576 .addReg(MI.getOperand(3).getReg())
1578 .addReg(MI.getOperand(2).getReg())
lib/Target/XCore/XCoreInstrInfo.cpp 71 return MI.getOperand(0).getReg();
91 return MI.getOperand(0).getReg();
290 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
299 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
lib/Target/XCore/XCoreMCInstLower.cpp 86 return MCOperand::createReg(MO.getReg());
lib/Target/XCore/XCoreRegisterInfo.cpp 304 Register Reg = MI.getOperand(0).getReg();
unittests/CodeGen/GlobalISel/CSETest.cpp 63 EXPECT_EQ(Splat0->getOperand(1).getReg(), Splat0->getOperand(2).getReg());
63 EXPECT_EQ(Splat0->getOperand(1).getReg(), Splat0->getOperand(2).getReg());
64 EXPECT_EQ(&*MIBCst, MRI->getVRegDef(Splat0->getOperand(1).getReg()));
68 EXPECT_EQ(FSplat->getOperand(1).getReg(), FSplat->getOperand(2).getReg());
68 EXPECT_EQ(FSplat->getOperand(1).getReg(), FSplat->getOperand(2).getReg());
69 EXPECT_EQ(&*MIBFP0, MRI->getVRegDef(FSplat->getOperand(1).getReg()));
unittests/CodeGen/GlobalISel/ConstantFoldingTest.cpp 31 bool match = mi_match(MIBCAdd->getOperand(0).getReg(), *MRI, m_ICst(Cst));
38 match = mi_match(MIBCAdd1->getOperand(0).getReg(), *MRI, m_ICst(Cst));
50 match = mi_match(MIBCSub->getOperand(0).getReg(), *MRI, m_ICst(Cst));
58 match = mi_match(MIBCSext1->getOperand(0).getReg(), *MRI, m_ICst(Cst));
66 match = mi_match(MIBCSext2->getOperand(0).getReg(), *MRI, m_ICst(Cst));
84 ConstantFoldBinOp(TargetOpcode::G_ADD, MIBCst1->getOperand(0).getReg(),
85 MIBCst2->getOperand(0).getReg(), *MRI);
89 ConstantFoldBinOp(TargetOpcode::G_ADD, MIBCst1->getOperand(0).getReg(),
90 MIBFCst2->getOperand(0).getReg(), *MRI);
96 ConstantFoldBinOp(TargetOpcode::G_AND, MIBCst1->getOperand(0).getReg(),
97 MIBCst2->getOperand(0).getReg(), *MRI);
101 ConstantFoldBinOp(TargetOpcode::G_AND, MIBCst2->getOperand(0).getReg(),
102 MIBFCst1->getOperand(0).getReg(), *MRI);
108 ConstantFoldBinOp(TargetOpcode::G_ASHR, MIBCst1->getOperand(0).getReg(),
109 MIBCst2->getOperand(0).getReg(), *MRI);
113 ConstantFoldBinOp(TargetOpcode::G_ASHR, MIBFCst2->getOperand(0).getReg(),
114 MIBCst2->getOperand(0).getReg(), *MRI);
120 ConstantFoldBinOp(TargetOpcode::G_LSHR, MIBCst1->getOperand(0).getReg(),
121 MIBCst2->getOperand(0).getReg(), *MRI);
125 ConstantFoldBinOp(TargetOpcode::G_LSHR, MIBFCst1->getOperand(0).getReg(),
126 MIBCst2->getOperand(0).getReg(), *MRI);
132 ConstantFoldBinOp(TargetOpcode::G_MUL, MIBCst1->getOperand(0).getReg(),
133 MIBCst2->getOperand(0).getReg(), *MRI);
137 ConstantFoldBinOp(TargetOpcode::G_MUL, MIBCst1->getOperand(0).getReg(),
138 MIBFCst2->getOperand(0).getReg(), *MRI);
144 ConstantFoldBinOp(TargetOpcode::G_OR, MIBCst1->getOperand(0).getReg(),
145 MIBCst2->getOperand(0).getReg(), *MRI);
149 ConstantFoldBinOp(TargetOpcode::G_OR, MIBCst1->getOperand(0).getReg(),
150 MIBFCst2->getOperand(0).getReg(), *MRI);
156 ConstantFoldBinOp(TargetOpcode::G_SHL, MIBCst1->getOperand(0).getReg(),
157 MIBCst2->getOperand(0).getReg(), *MRI);
161 ConstantFoldBinOp(TargetOpcode::G_SHL, MIBCst1->getOperand(0).getReg(),
162 MIBFCst2->getOperand(0).getReg(), *MRI);
168 ConstantFoldBinOp(TargetOpcode::G_SUB, MIBCst1->getOperand(0).getReg(),
169 MIBCst2->getOperand(0).getReg(), *MRI);
173 ConstantFoldBinOp(TargetOpcode::G_SUB, MIBCst1->getOperand(0).getReg(),
174 MIBFCst2->getOperand(0).getReg(), *MRI);
180 ConstantFoldBinOp(TargetOpcode::G_XOR, MIBCst1->getOperand(0).getReg(),
181 MIBCst2->getOperand(0).getReg(), *MRI);
185 ConstantFoldBinOp(TargetOpcode::G_XOR, MIBCst1->getOperand(0).getReg(),
186 MIBFCst2->getOperand(0).getReg(), *MRI);
192 ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
193 MIBCst2->getOperand(0).getReg(), *MRI);
197 ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
198 MIBFCst2->getOperand(0).getReg(), *MRI);
204 ConstantFoldBinOp(TargetOpcode::G_SDIV, MIBCst1->getOperand(0).getReg(),
205 MIBCst2->getOperand(0).getReg(), *MRI);
209 ConstantFoldBinOp(TargetOpcode::G_SDIV, MIBCst1->getOperand(0).getReg(),
210 MIBFCst2->getOperand(0).getReg(), *MRI);
216 ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
217 MIBCst2->getOperand(0).getReg(), *MRI);
221 ConstantFoldBinOp(TargetOpcode::G_UDIV, MIBCst1->getOperand(0).getReg(),
222 MIBFCst2->getOperand(0).getReg(), *MRI);
228 ConstantFoldBinOp(TargetOpcode::G_SREM, MIBCst1->getOperand(0).getReg(),
229 MIBCst2->getOperand(0).getReg(), *MRI);
233 ConstantFoldBinOp(TargetOpcode::G_SREM, MIBCst1->getOperand(0).getReg(),
234 MIBFCst2->getOperand(0).getReg(), *MRI);
unittests/CodeGen/GlobalISel/GISelMITest.h 132 Copies.push_back(MI.getOperand(0).getReg());
unittests/CodeGen/GlobalISel/KnownBitsTest.cpp 21 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
22 unsigned DstReg = FinalCopy->getOperand(0).getReg();
41 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
42 unsigned DstReg = FinalCopy->getOperand(0).getReg();
69 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
85 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
112 unsigned SrcReg = FinalCopy->getOperand(1).getReg();
unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp 333 Register RegC0 = B.buildConstant(S32, 0)->getOperand(0).getReg();
334 Register RegC1 = B.buildConstant(S32, 1)->getOperand(0).getReg();
335 Register RegC2 = B.buildConstant(S32, 2)->getOperand(0).getReg();
336 Register RegC3 = B.buildConstant(S32, 3)->getOperand(0).getReg();
344 B.buildMerge(V2x32, {RegC0, RegC1})->getOperand(0).getReg();
346 B.buildMerge(V2x32, {RegC2, RegC3})->getOperand(0).getReg();
unittests/CodeGen/GlobalISel/PatternMatchTest.cpp 39 bool match = mi_match(MIBCst->getOperand(0).getReg(), *MRI, m_ICst(Cst));
52 mi_match(MIBAdd->getOperand(0).getReg(), *MRI, m_GAdd(m_Reg(), m_Reg()));
55 match = mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
65 match = mi_match(MIBMul->getOperand(0).getReg(), *MRI,
68 EXPECT_EQ(Src0, MIBAdd->getOperand(0).getReg());
72 match = mi_match(MIBMul->getOperand(0).getReg(), *MRI,
84 match = mi_match(MIBMul2->getOperand(0).getReg(), *MRI,
92 match = mi_match(MIBSub->getOperand(0).getReg(), *MRI,
99 match = mi_match(MIBFMul->getOperand(0).getReg(), *MRI,
108 match = mi_match(MIBFSub->getOperand(0).getReg(), *MRI,
116 match = mi_match(MIBAnd->getOperand(0).getReg(), *MRI,
125 match = mi_match(MIBOr->getOperand(0).getReg(), *MRI,
144 mi_match(MIBFabs->getOperand(0).getReg(), *MRI, m_GFabs(m_Reg()));
149 match = mi_match(MIBFNeg->getOperand(0).getReg(), *MRI, m_GFNeg(m_Reg(Src)));
151 EXPECT_EQ(Src, Copy0s32->getOperand(0).getReg());
153 match = mi_match(MIBFabs->getOperand(0).getReg(), *MRI, m_GFabs(m_Reg(Src)));
155 EXPECT_EQ(Src, Copy0s32->getOperand(0).getReg());
160 match = mi_match(MIBFCst->getOperand(0).getReg(), *MRI, m_GFCst(TmpFP));
171 match = mi_match(MIBFCst64->getOperand(0).getReg(), *MRI, m_GFCst(TmpFP64));
183 match = mi_match(MIBFCst16->getOperand(0).getReg(), *MRI, m_GFCst(TmpFP16));
208 mi_match(MIBTrunc->getOperand(0).getReg(), *MRI, m_GTrunc(m_Reg(Src0)));
212 mi_match(MIBAExt->getOperand(0).getReg(), *MRI, m_GAnyExt(m_Reg(Src0)));
214 EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
216 match = mi_match(MIBSExt->getOperand(0).getReg(), *MRI, m_GSExt(m_Reg(Src0)));
218 EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
220 match = mi_match(MIBZExt->getOperand(0).getReg(), *MRI, m_GZExt(m_Reg(Src0)));
222 EXPECT_EQ(Src0, MIBTrunc->getOperand(0).getReg());
225 match = mi_match(MIBAExt->getOperand(0).getReg(), *MRI,
230 match = mi_match(MIBSExt->getOperand(0).getReg(), *MRI,
235 match = mi_match(MIBZExt->getOperand(0).getReg(), *MRI,
250 EXPECT_FALSE(mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
252 EXPECT_TRUE(mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
259 mi_match(MIBCast->getOperand(0).getReg(), *MRI, m_GBitcast(m_Reg())));
261 mi_match(MIBCast->getOperand(0).getReg(), *MRI, m_SpecificType(v2s32)));
263 mi_match(MIBCast->getOperand(1).getReg(), *MRI, m_SpecificType(s64)));
272 bool match = mi_match(MIBPtrToInt->getOperand(0).getReg(), *MRI,
288 mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
295 mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
299 mi_match(MIBAdd->getOperand(0).getReg(), *MRI,
307 MIBAdd->getOperand(0).getReg(), *MRI,
unittests/CodeGen/MachineOperandTest.cpp 74 ASSERT_TRUE(MO.getReg() == 1);