reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/DetectDeadLanes.cpp

  280   const MachineInstr &MI = *Use.getParent();
  312   const MachineInstr &MI = *Def.getParent();
  359   const MachineInstr &DefMI = *Def.getParent();
  393           const MachineInstr &MODefMI = *MODef.getParent();
  423     const MachineInstr &UseMI = *MO.getParent();
  469   const MachineInstr &MI = *MO.getParent();

lib/CodeGen/GlobalISel/RegBankSelect.cpp

  325   const MachineInstr &MI = *MO.getParent();

lib/CodeGen/LiveInterval.cpp

  983       const MachineInstr &MI = *MO.getParent();

lib/CodeGen/LiveRangeCalc.cpp

   66   const MachineInstr &MI = *MO.getParent();

lib/CodeGen/LiveRangeEdit.cpp

  245   const MachineInstr &MI = *MO.getParent();

lib/CodeGen/MIRPrinter.cpp

  850       TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);

lib/CodeGen/MachineInstr.cpp

  878       CurRC = OpndIt->getParent()->getRegClassConstraintEffectForVRegImpl(

lib/CodeGen/MachineOperand.cpp

   41   if (const MachineInstr *MI = MO.getParent())
  122   const MachineInstr *MI = getParent();

lib/CodeGen/MachineRegisterInfo.cpp

  570   const MachineInstr &MI = *MO.getParent();

lib/CodeGen/MachineScheduler.cpp

 1487             *BaseOp->getParent()->getParent()->getParent();

lib/CodeGen/MachineVerifier.cpp

  441         if (Op.getParent() != &MI) {
  512   report(msg, MO->getParent());
 1594   const MachineInstr *MI = MO->getParent();
 1940   const MachineInstr *MI = MO->getParent();

lib/CodeGen/RegisterPressure.cpp

 1230     const MachineInstr *MI = MO.getParent();

lib/CodeGen/RegisterScavenging.cpp

  657       return !MO.getParent()->readsRegister(VReg, &TRI);

lib/CodeGen/RenameIndependentSubregs.cpp

  188       SlotIndex Pos = LIS->getInstructionIndex(*MO.getParent());

lib/CodeGen/VirtRegMap.cpp

  357   const MachineInstr &MI = *MO.getParent();

lib/Target/AArch64/AArch64InstrInfo.cpp

 2329   const MachineInstr &FirstLdSt = *BaseOp1.getParent();
 2330   const MachineInstr &SecondLdSt = *BaseOp2.getParent();

lib/Target/AArch64/AArch64InstructionSelector.cpp

 4015   auto &MI = *Root.getParent();

lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp

  595     if (!UseOp.isImplicit() || !TII.isFLAT(*UseOp.getParent()))

lib/Target/AMDGPU/AMDGPUMCInstLower.cpp

  140         getLongBranchBlockExpr(*MO.getParent()->getParent(), MO));

lib/Target/AMDGPU/GCNRegPressure.cpp

  225   auto SI = LIS.getInstructionIndex(*MO.getParent()).getBaseIndex();

lib/Target/AMDGPU/SIFixSGPRCopies.cpp

  213     const auto *UseMI = MO.getParent();
  769       const MachineInstr *UseMI = Use.getParent();

lib/Target/AMDGPU/SIInstrInfo.cpp

  432   const MachineInstr &FirstLdSt = *BaseOp1.getParent();
  433   const MachineInstr &SecondLdSt = *BaseOp2.getParent();
 2596   const MachineFunction *MF = MO->getParent()->getParent()->getParent();
 3926     const MachineFunction *MF = MO.getParent()->getParent()->getParent();

lib/Target/AMDGPU/SIInstrInfo.h

  707     assert(UseMO.getParent() == &MI);
  741     const MachineInstr *Parent = MO.getParent();

lib/Target/AMDGPU/SIPeepholeSDWA.cpp

  337   const auto *MI = SrcOp->getParent();
  534       const MachineInstr *DefInst = Def.getParent();

lib/Target/AMDGPU/SIShrinkInstructions.cpp

  130     !TII->isInlineConstant(*Src.getParent(),
  131                            Src.getParent()->getOperandNo(&Src));
  136     !TII->isInlineConstant(*Src.getParent(),
  137                            Src.getParent()->getOperandNo(&Src));

lib/Target/Hexagon/HexagonConstExtenders.cpp

  493     const MachineBasicBlock &MBB = *ED.getOp().getParent()->getParent();
 1135     Range.intersect(getOffsetRange(Rd, *Op.getParent()));

lib/Target/PowerPC/PPCMCInstLower.cpp

  112   const MachineFunction *MF = MO.getParent()->getParent()->getParent();
  131     const MachineFunction *MF = MO.getParent()->getParent()->getParent();

lib/Target/WebAssembly/WebAssemblyMCInstLower.cpp

   53     const MachineFunction &MF = *MO.getParent()->getParent()->getParent();

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

  408   const MachineInstr *OneUseInst = OneUse.getParent();
  415     const MachineInstr *UseInst = Use.getParent();
  445         const MachineInstr *NewUseInst = NewUse.getParent();