reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/MachineInstrBuilder.h

  500          getUndefRegState(RegOp.isUndef()) |

lib/CodeGen/MachineInstrBundle.cpp

  224     MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |

lib/CodeGen/SplitKit.cpp

  518       .addReg(ToReg, RegState::Define | getUndefRegState(FirstCopy)

lib/Target/AArch64/AArch64InstrInfo.cpp

 2929       .addReg(DestReg0, RegState::Define | getUndefRegState(IsUndef), SubIdx0)
 2930       .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1)

lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

  483     MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef()));
  520   const unsigned SrcFlags = getUndefRegState(Src.isUndef());

lib/Target/AMDGPU/SIISelLowering.cpp

 3203     .addReg(IdxReg.getReg(), getUndefRegState(IdxReg.isUndef()));

lib/Target/AMDGPU/SIInstrInfo.cpp

 4337   unsigned VRsrcUndef = getUndefRegState(Rsrc.isUndef());

lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp

  262           .addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg());

lib/Target/ARM/ARMBaseInstrInfo.cpp

 5011         .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI)))
 5047             .addReg(DDst, getUndefRegState(!MI.readsRegister(DDst, TRI)))
 5081       NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
 5085       NewMIB.addReg(CurReg, getUndefRegState(CurUndef))
 5099       MIB.addReg(CurReg, getUndefRegState(CurUndef));
 5103       MIB.addReg(CurReg, getUndefRegState(CurUndef))

lib/Target/ARM/ARMExpandPseudoInsts.cpp

  630   MIB.addReg(D0, getUndefRegState(SrcIsUndef));
  632     MIB.addReg(D1, getUndefRegState(SrcIsUndef));
  634     MIB.addReg(D2, getUndefRegState(SrcIsUndef));
  636     MIB.addReg(D3, getUndefRegState(SrcIsUndef));
  714   unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

 1631       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
 1639       .addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef))
 1640       .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
 1710                 getKillRegState(EvenDeadKill) | getUndefRegState(EvenUndef))
 1712                 getKillRegState(OddDeadKill)  | getUndefRegState(OddUndef))

lib/Target/Hexagon/HexagonInstrInfo.cpp

  630       unsigned Flags1 = getUndefRegState(Cond[1].isUndef());
  634         unsigned Flags2 = getUndefRegState(Cond[2].isUndef());
  645       unsigned Flags = getUndefRegState(RO.isUndef());
  669     unsigned Flags = getUndefRegState(RO.isUndef());

lib/Target/SystemZ/SystemZInstrInfo.cpp

   80   unsigned Reg128Undef  = getUndefRegState(LowRegOp.isUndef());
  263       .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
  268     .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

  616                           .addReg(DefReg, getUndefRegState(DefMO.isDead()));

lib/Target/X86/X86FrameLowering.cpp

  332             .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub))

lib/Target/X86/X86InstrInfo.cpp

 4071              getUndefRegState(MIB->getOperand(1).isUndef()));
 5544                getUndefRegState(ImpOp.isUndef()));