reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h

  957       constrainOperandRegToRegClass(*OutMIs[InsnID].getInstr(), OpIdx,
  969       constrainSelectedInstRegOperands(*OutMIs[InsnID].getInstr(), TII, TRI,

lib/CodeGen/GlobalISel/IRTranslator.cpp

 1933     Insts.push_back(MIB.getInstr());

lib/CodeGen/SelectionDAG/FastISel.cpp

  840   const MCInstrDesc &MCID = Builder.getInstr()->getDesc();

lib/CodeGen/SelectionDAG/InstrEmitter.cpp

  853     MachineInstr *MI = MIB.getInstr();

lib/Target/AArch64/AArch64InstructionSelector.cpp

 1422       return constrainSelectedInstRegOperands(*MIB.getInstr(), TII, TRI, RBI);
 1428       constrainSelectedInstRegOperands(*CMP.getInstr(), TII, TRI, RBI);
 1435       return constrainSelectedInstRegOperands(*Bcc.getInstr(), TII, TRI, RBI);

lib/Target/AMDGPU/GCNDPPCombine.cpp

  206     if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src0)) {
  228       if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) {
  238       if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) ||
  239           !TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src2)) {
  254     DPPInst.getInstr()->eraseFromParent();
  257   LLVM_DEBUG(dbgs() << "  combined:  " << *DPPInst.getInstr());
  258   return DPPInst.getInstr();
  439     DPPMIs.push_back(UndefInst.getInstr());

lib/Target/AMDGPU/SIRegisterInfo.cpp

  591   if (spillVGPRtoAGPR(ST, MI, Index, 0, Reg->getReg(), false).getInstr())
  701     if (!MIB.getInstr()) {

lib/Target/AMDGPU/SIShrinkInstructions.cpp

  533         .addReg(X1.Reg, 0, X1.SubReg).getInstr();

lib/Target/ARC/ARCInstrInfo.cpp

  365         .getInstr();

lib/Target/ARM/ARMCallLowering.cpp

  536           *MIB.getInstr(), MIB->getDesc(), Info.Callee, CalleeIdx));

lib/Target/ARM/ARMExpandPseudoInsts.cpp

  575   LLVM_DEBUG(dbgs() << "To:        "; MIB.getInstr()->dump(););
  651   LLVM_DEBUG(dbgs() << "To:        "; MIB.getInstr()->dump(););
  780   LLVM_DEBUG(dbgs() << "To:        "; MIB.getInstr()->dump(););
  920   LLVM_DEBUG(dbgs() << "To:        "; LO16.getInstr()->dump(););
  921   LLVM_DEBUG(dbgs() << "And:       "; HI16.getInstr()->dump(););

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

  822   return MIB.getInstr();
  847   return MIB.getInstr();

lib/Target/ARM/MVEVPTBlockPass.cpp

  248         Block, MachineBasicBlock::instr_iterator(MIBuilder.getInstr()), MBIter);

lib/Target/ARM/Thumb1FrameLowering.cpp

  765       MBB.erase(MIB.getInstr());

lib/Target/ARM/Thumb2ITBlockPass.cpp

  222     MachineBasicBlock::iterator InsertPos = MIB.getInstr();

lib/Target/AVR/AVRExpandPseudoInsts.cpp

  830           *buildMI(MBB, MBBI, Opcode).add(Op1).add(Op2).getInstr();

lib/Target/Sparc/SparcInstrInfo.cpp

  386     MovMI = MIB.getInstr();

lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp

  372     unsigned Index = MIB.getInstr()->getNumExplicitOperands() - 1;
  467   MIB.addMBB(MIB.getInstr()
  468                  ->getOperand(MIB.getInstr()->getNumExplicitOperands() - 1)

lib/Target/X86/X86CallFrameOptimization.cpp

  571                    .getInstr();

lib/Target/X86/X86CondBrFolding.cpp

  230     MBBInfo->BrInstr = MIB.getInstr();
  257   MBBInfo->BrInstr = MIB.getInstr();

lib/Target/X86/X86FloatingPoint.cpp

  880       .getInstr();

lib/Target/X86/X86ISelLowering.cpp

29858   BuildMI(*SinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())), DL,

lib/Target/X86/X86InstrInfo.cpp

 3913   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
 3931   MachineBasicBlock::iterator I = MIB.getInstr();
 3994   MachineBasicBlock::iterator I = MIB.getInstr();

lib/Target/XCore/XCoreInstrInfo.cpp

  437         .getInstr();
  441     return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr();
  449       .getInstr();