reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/MachineInstrBuilder.h

  499          getKillRegState(RegOp.isKill()) | getDeadRegState(RegOp.isDead()) |

lib/CodeGen/MachineInstrBundle.cpp

  215       MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |

lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp

  147                 getDeadRegState(DstIsDead && LastItem))
  158                 getDeadRegState(DstIsDead && LastItem))

lib/Target/ARM/ARMExpandPseudoInsts.cpp

  498     MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));
  502     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
  504       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
  506       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
  508       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
  569   MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
  689     MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
  691       MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
  693       MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
  695       MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
  737     MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
  848       .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
  880     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
 1459               .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
 1514             .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
 1555         .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
 1606       MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
 1607         .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
 1610       MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

 1630       .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
 1701         .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
 1702         .addReg(OddReg,  getDefRegState(isLd) | getDeadRegState(OddDeadKill))

lib/Target/ARM/MLxExpansionPass.cpp

  298     .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));

lib/Target/AVR/AVRExpandPseudoInsts.cpp

  153     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
  158     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
  186     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
  194     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
  234       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
  244       .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
  282     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
  286     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
  339     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
  347     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
  399     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
  406     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
  495     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
  498     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
  544     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
  547     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
  641     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
  646     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
  647     .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
  672     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
  677     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
  678     .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
 1062     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
 1096     .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
 1158     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
 1162     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
 1259     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
 1264     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
 1292     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
 1296     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
 1335     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
 1339     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
 1377       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
 1397     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
 1431       .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
 1436     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
 1460     .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
 1466     .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))

lib/Target/PowerPC/PPCInstrInfo.cpp

  428         .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))

lib/Target/X86/X86InstrInfo.cpp

  865           .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
 5543                getDeadRegState(ImpOp.isDead()) |