|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/X86/X86GenFastISel.inc 6952 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::AL).addReg(Op0);
7435 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
7537 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
7699 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
8025 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
8041 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h 795 OutMIs[NewInsnID].addReg(ZeroReg);
811 OutMIs[NewInsnID].addReg(State.MIs[OldInsnID]->getOperand(OpIdx).getReg(),
847 OutMIs[InsnID].addReg(RegNum, RegFlags);
860 OutMIs[InsnID].addReg(State.TempRegisters[TempRegID], TempRegFlags);
include/llvm/CodeGen/MachineInstrBuilder.h 109 return addReg(RegNo, Flags | RegState::Define, SubReg);
118 return addReg(RegNo, Flags, SubReg);
326 .addReg(DestReg, RegState::Define);
339 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
355 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define);
include/llvm/CodeGen/TargetInstrInfo.h 1707 .addReg(Src);
1719 .addReg(Src, 0, SrcSubReg);
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 133 .addReg(0)
156 MIB.addReg(0U);
159 return MIB.addReg(0).addMetadata(Variable).addMetadata(Expr);
lib/CodeGen/GlobalISel/Utils.cpp 59 .addReg(Reg);
64 .addReg(ConstrainedReg);
lib/CodeGen/IfConversion.cpp 1500 MIB.addReg(Reg, RegState::Implicit);
1507 MIB.addReg(Reg, RegState::Implicit | RegState::Define);
1511 MIB.addReg(Reg, RegState::Implicit);
1521 MIB.addReg(Reg, RegState::Implicit);
lib/CodeGen/InlineSpiller.cpp 946 .addReg(NewVReg, getKillRegState(isKill));
lib/CodeGen/MachineBasicBlock.cpp 518 .addReg(PhysReg, RegState::Kill);
lib/CodeGen/MachineInstr.cpp 2021 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
2025 MIB.addReg(0U, RegState::Debug);
2044 MIB.addReg(0U, RegState::Debug);
lib/CodeGen/MachineInstrBundle.cpp 215 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
224 MIB.addReg(Reg, getKillRegState(isKill) | getUndefRegState(isUndef) |
lib/CodeGen/MachinePipeliner.cpp 369 .addReg(RegOp.getReg(), getRegState(RegOp),
lib/CodeGen/MachineRegisterInfo.cpp 488 .addReg(LiveIns[i].first);
lib/CodeGen/MachineSSAUpdater.cpp 194 InsertedPHI.addReg(PredValues[i].second).addMBB(PredValues[i].first);
316 MachineInstrBuilder(*Pred->getParent(), PHI).addReg(Val).addMBB(Pred);
lib/CodeGen/ModuloSchedule.cpp 553 NewPhi.addReg(PhiOp1).addMBB(BB1);
554 NewPhi.addReg(PhiOp2).addMBB(BB2);
669 NewPhi.addReg(PhiOp1).addMBB(BB1);
670 NewPhi.addReg(PhiOp2).addMBB(BB2);
814 .addReg(Def);
1438 .addReg(IllegalPhiDefault.getValue())
1440 .addReg(LoopReg)
1487 .addReg(InitReg.hasValue() ? *InitReg : undef(RC))
1489 .addReg(LoopReg)
1690 .addReg(OldR)
lib/CodeGen/PeepholeOptimizer.cpp 587 .addReg(DstReg, 0, SubIdx);
771 MIB.addReg(RegPair.Reg, 0, RegPair.SubReg);
1237 .addReg(NewSrc.Reg, 0, NewSrc.SubReg);
lib/CodeGen/PrologEpilogInserter.cpp 549 .addReg(Reg, getKillRegState(true));
576 .addReg(CI.getDstReg(), getKillRegState(true));
lib/CodeGen/RegisterCoalescer.cpp 1125 .addReg(IntA.reg);
lib/CodeGen/SelectionDAG/FastISel.cpp 1420 .addReg(0U)
1426 .addReg(0U)
1432 .addReg(0U)
1556 TII.get(TargetOpcode::COPY), ResultReg).addReg(Op0);
2030 TII.get(TargetOpcode::COPY), NewOp).addReg(Op);
2056 .addReg(Op0, getKillRegState(Op0IsKill));
2059 .addReg(Op0, getKillRegState(Op0IsKill));
2061 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2079 .addReg(Op0, getKillRegState(Op0IsKill))
2080 .addReg(Op1, getKillRegState(Op1IsKill));
2083 .addReg(Op0, getKillRegState(Op0IsKill))
2084 .addReg(Op1, getKillRegState(Op1IsKill));
2086 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2105 .addReg(Op0, getKillRegState(Op0IsKill))
2106 .addReg(Op1, getKillRegState(Op1IsKill))
2107 .addReg(Op2, getKillRegState(Op2IsKill));
2110 .addReg(Op0, getKillRegState(Op0IsKill))
2111 .addReg(Op1, getKillRegState(Op1IsKill))
2112 .addReg(Op2, getKillRegState(Op2IsKill));
2114 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2129 .addReg(Op0, getKillRegState(Op0IsKill))
2133 .addReg(Op0, getKillRegState(Op0IsKill))
2136 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2152 .addReg(Op0, getKillRegState(Op0IsKill))
2157 .addReg(Op0, getKillRegState(Op0IsKill))
2161 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2180 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2197 .addReg(Op0, getKillRegState(Op0IsKill))
2198 .addReg(Op1, getKillRegState(Op1IsKill))
2202 .addReg(Op0, getKillRegState(Op0IsKill))
2203 .addReg(Op1, getKillRegState(Op1IsKill))
2206 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2222 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
2235 ResultReg).addReg(Op0, getKillRegState(Op0IsKill), Idx);
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 178 VRBase).addReg(SrcReg);
223 MIB.addReg(VRBase, RegState::Define);
236 MIB.addReg(VRBase, RegState::Define);
248 MIB.addReg(VRBase, RegState::Define);
324 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
355 MIB.addReg(VReg, getDefRegState(isOptDef) | getKillRegState(isKill) |
391 TII->get(TargetOpcode::COPY), NewVReg).addReg(VReg);
398 MIB.addReg(VReg, getImplRegState(Imp));
469 .addReg(VReg);
525 TII->get(TargetOpcode::COPY), VRBase).addReg(SrcReg);
544 CopyMI.addReg(Reg, 0, SubIdx);
546 CopyMI.addReg(TRI->getSubReg(Reg, SubIdx));
618 NewVReg).addReg(VReg);
692 MIB.addReg(0U);
693 MIB.addReg(0U, RegState::Debug);
708 FrameMI.addReg(0);
724 MIB.addReg(0U); // undef
729 MIB.addReg(SD->getVReg(), RegState::Debug);
745 MIB.addReg(0U);
749 MIB.addReg(0U);
756 MIB.addReg(0U, RegState::Debug);
902 MIB.addReg(ScratchRegs[i], RegState::ImplicitDefine |
1014 DestReg).addReg(SrcReg);
1093 MIB.addReg(Reg,
1102 MIB.addReg(Reg,
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp 807 .addReg(VRI->second);
816 .addReg(I->getReg());
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 1248 .addReg(EHPhysReg, RegState::Kill);
1712 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1840 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(BTB.Parent);
1842 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1851 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1892 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second)
1896 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1943 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
lib/CodeGen/SplitKit.cpp 518 .addReg(ToReg, RegState::Define | getUndefRegState(FirstCopy)
520 .addReg(FromReg, 0, SubIdx);
545 BuildMI(MBB, InsertBefore, DebugLoc(), Desc, ToReg).addReg(FromReg);
lib/CodeGen/SwiftErrorValueTracking.cpp 234 .addReg(VRegs[0].second);
248 PHI.addReg(BBRegPair.second).addMBB(BBRegPair.first);
lib/CodeGen/TailDuplicator.cpp 439 .addReg(VI->second.Reg, 0, VI->second.SubReg);
517 MIB.addReg(SrcReg).addMBB(SrcBB);
529 MIB.addReg(Reg).addMBB(SrcBB);
985 .addReg(CI.second.Reg, 0, CI.second.SubReg);
lib/CodeGen/TargetInstrInfo.cpp 839 .addReg(RegX, getKillRegState(KillX))
840 .addReg(RegY, getKillRegState(KillY));
843 .addReg(RegA, getKillRegState(KillA))
844 .addReg(NewVR, getKillRegState(true));
lib/CodeGen/TwoAddressInstructionPass.cpp 1556 MIB.addReg(RegB, 0, SubRegB);
1839 .addReg(DstReg, RegState::Define, SubIdx)
lib/CodeGen/UnreachableBlockElim.cpp 197 .addReg(InputReg, getRegState(Input), InputSub);
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 278 .addReg(Src, getKillRegState(IsKill));
363 .addReg(Src0, getKillRegState(KillSrc0), SubReg0)
364 .addReg(Src1, getKillRegState(KillSrc1), SubReg1);
lib/Target/AArch64/AArch64CallLowering.cpp 889 MIB.addReg(ForwardedReg, RegState::Implicit);
lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp 106 .addReg(TLSBaseAddrReg);
128 .addReg(AArch64::X0);
lib/Target/AArch64/AArch64ConditionalCompares.cpp 638 .addReg(DestReg, RegState::Define | RegState::Dead)
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 137 .addReg(BitSize == 32 ? AArch64::WZR : AArch64::XZR)
146 .addReg(DstReg, RegState::Define |
156 .addReg(DstReg,
159 .addReg(DstReg)
204 .addReg(AddrReg);
206 .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
207 .addReg(DesiredReg)
212 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
220 .addReg(NewReg)
221 .addReg(AddrReg);
223 .addReg(StatusReg, getKillRegState(StatusDead))
283 .addReg(DestLo.getReg(), RegState::Define)
284 .addReg(DestHi.getReg(), RegState::Define)
285 .addReg(AddrReg);
287 .addReg(DestLo.getReg(), getKillRegState(DestLo.isDead()))
288 .addReg(DesiredLoReg)
295 .addReg(DestHi.getReg(), getKillRegState(DestHi.isDead()))
296 .addReg(DesiredHiReg)
312 .addReg(NewLoReg)
313 .addReg(NewHiReg)
314 .addReg(AddrReg);
316 .addReg(StatusReg, getKillRegState(StatusDead))
365 .addReg(AddressReg)
366 .addReg(AddressReg)
372 .addReg(SizeReg)
510 .addReg(DstReg, RegState::Kill)
511 .addReg(DstReg, DstFlags | RegState::Implicit);
568 .addReg(DstReg)
576 .addReg(DstReg)
625 .addReg(AArch64::LR, RegState::Undef);
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 771 .addReg(AArch64::XZR)
772 .addReg(LdI.BaseReg)
786 .addReg(AArch64::XZR)
787 .addReg(ScratchReg)
lib/Target/AArch64/AArch64FastISel.cpp 393 ResultReg).addReg(ZeroReg, getKillRegState(true));
430 .addReg(TmpReg, getKillRegState(true));
449 .addReg(ADRPReg)
489 .addReg(ADRPReg)
502 .addReg(ResultReg, RegState::Kill)
514 .addReg(ADRPReg)
1148 MIB.addReg(Addr.getReg());
1149 MIB.addReg(Addr.getOffsetReg());
1153 MIB.addReg(Addr.getReg()).addImm(Offset);
1347 .addReg(LHSReg, getKillRegState(LHSIsKill))
1348 .addReg(RHSReg, getKillRegState(RHSIsKill));
1391 .addReg(LHSReg, getKillRegState(LHSIsKill))
1434 .addReg(LHSReg, getKillRegState(LHSIsKill))
1435 .addReg(RHSReg, getKillRegState(RHSIsKill))
1479 .addReg(LHSReg, getKillRegState(LHSIsKill))
1480 .addReg(RHSReg, getKillRegState(RHSIsKill))
1538 .addReg(LHSReg, getKillRegState(LHSIsKill));
1549 .addReg(LHSReg, getKillRegState(LHSIsKill))
1550 .addReg(RHSReg, getKillRegState(RHSIsKill));
1915 .addReg(ResultReg, getKillRegState(true))
2105 .addReg(SrcReg)
2106 .addReg(AddrReg)
2173 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(SrcReg);
2411 .addReg(SrcReg, getKillRegState(SrcIsKill));
2542 .addReg(ConstrainedCondReg, getKillRegState(CondRegIsKill))
2559 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(AddrReg);
2585 .addReg(AArch64::WZR, getKillRegState(true));
2625 .addReg(AArch64::WZR, getKillRegState(true))
2626 .addReg(AArch64::WZR, getKillRegState(true))
2630 .addReg(TmpReg1, getKillRegState(true))
2631 .addReg(AArch64::WZR, getKillRegState(true))
2644 .addReg(AArch64::WZR, getKillRegState(true))
2645 .addReg(AArch64::WZR, getKillRegState(true))
2815 .addReg(CondReg, getKillRegState(CondIsKill))
2850 ResultReg).addReg(Op);
2866 ResultReg).addReg(Op);
2900 .addReg(SrcReg);
3056 .addReg(DstReg, getKillRegState(true));
3116 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
3181 .addReg(RVLocs[0].getLocReg());
3276 MIB.addReg(Reg);
3290 .addReg(ADRPReg)
3303 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(CallReg);
3308 MIB.addReg(Reg, RegState::Implicit);
3482 TII.get(TargetOpcode::COPY), SrcReg).addReg(FramePtr);
3641 .addReg(SrcReg, getKillRegState(SrcRegIsKill));
3815 TII.get(TargetOpcode::COPY), ResultReg1).addReg(MulReg);
3927 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
3936 MIB.addReg(RetReg, RegState::Implicit);
3999 .addReg(SrcReg, getKillRegState(SrcIsKill));
4024 .addReg(ResultReg)
4129 .addReg(Op0, getKillRegState(Op0IsKill));
4177 .addReg(Op0, getKillRegState(Op0IsKill))
4236 .addReg(Op0, getKillRegState(Op0IsKill));
4298 .addReg(Op0, getKillRegState(Op0IsKill))
4357 .addReg(Op0, getKillRegState(Op0IsKill));
4407 .addReg(Op0, getKillRegState(Op0IsKill))
4466 .addReg(SrcReg)
4563 .addReg(Reg, getKillRegState(true))
4607 .addReg(SrcReg, getKillRegState(SrcIsKill))
lib/Target/AArch64/AArch64FrameLowering.cpp 694 MIB.addReg(AArch64::SP, RegState::Define);
992 .addReg(AArch64::X1).setMIFlag(MachineInstr::FrameSetup);
1038 .addReg(AArch64::X15)
1058 .addReg(AArch64::X15, RegState::Implicit)
1059 .addReg(AArch64::X16, RegState::Implicit | RegState::Define | RegState::Dead)
1060 .addReg(AArch64::X17, RegState::Implicit | RegState::Define | RegState::Dead)
1061 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define | RegState::Dead)
1071 .addReg(AArch64::X16, RegState::Define)
1082 .addReg(AArch64::X16, RegState::Kill)
1083 .addReg(AArch64::X15, RegState::Implicit | RegState::Define)
1084 .addReg(AArch64::X16, RegState::Implicit | RegState::Define | RegState::Dead)
1085 .addReg(AArch64::X17, RegState::Implicit | RegState::Define | RegState::Dead)
1086 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define | RegState::Dead)
1097 .addReg(AArch64::SP, RegState::Kill)
1098 .addReg(AArch64::X15, RegState::Kill)
1150 .addReg(scratchSPReg, RegState::Kill)
1963 .addReg(AArch64::X18, RegState::Define)
1964 .addReg(AArch64::LR)
1965 .addReg(AArch64::X18)
2052 MIB.addReg(Reg2, getPrologueDeath(MF, Reg2));
2057 MIB.addReg(Reg1, getPrologueDeath(MF, Reg1))
2058 .addReg(AArch64::SP)
2137 MIB.addReg(Reg2, getDefRegState(true));
2142 MIB.addReg(Reg1, getDefRegState(true))
2143 .addReg(AArch64::SP)
2163 .addReg(AArch64::X18, RegState::Define)
2164 .addReg(AArch64::LR, RegState::Define)
2165 .addReg(AArch64::X18)
2380 .addReg(DstReg, getKillRegState(true))
lib/Target/AArch64/AArch64ISelLowering.cpp 1372 .addReg(IfTrueReg)
1374 .addReg(IfFalseReg)
12405 .addReg(*I);
12411 .addReg(NewVR);
lib/Target/AArch64/AArch64InstrInfo.cpp 581 .addReg(SrcReg)
587 .addReg(SrcReg)
610 .addReg(Cond[2].getReg())
615 .addReg(Cond[2].getReg())
669 .addReg(TrueReg)
670 .addReg(FalseReg)
1491 .addReg(AArch64::X0, RegState::Define)
1494 .addReg(AArch64::X0, RegState::Define)
1495 .addReg(AArch64::X0)
1521 .addReg(Reg, RegState::Kill)
1531 .addReg(Reg, RegState::Kill)
1535 .addReg(Reg, RegState::Kill)
1539 .addReg(Reg, RegState::Kill)
1543 .addReg(Reg, RegState::Kill)
1563 .addReg(Reg, RegState::Kill)
2396 return MIB.addReg(Reg, State);
2399 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
2400 return MIB.addReg(Reg, State, SubIdx);
2456 MIB.addReg(ZeroReg);
2483 .addReg(SrcRegX, RegState::Undef)
2486 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
2489 .addReg(SrcReg, getKillRegState(KillSrc))
2509 .addReg(AArch64::XZR)
2510 .addReg(SrcRegX, RegState::Undef)
2511 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
2515 .addReg(AArch64::WZR)
2516 .addReg(SrcReg, getKillRegState(KillSrc));
2527 .addReg(SrcReg) // Pg
2528 .addReg(SrcReg)
2529 .addReg(SrcReg, getKillRegState(KillSrc));
2538 .addReg(SrcReg)
2539 .addReg(SrcReg, getKillRegState(KillSrc));
2548 .addReg(SrcReg, getKillRegState(KillSrc))
2558 .addReg(AArch64::XZR)
2559 .addReg(SrcReg, getKillRegState(KillSrc));
2642 .addReg(SrcReg)
2643 .addReg(SrcReg, getKillRegState(KillSrc));
2646 .addReg(AArch64::SP, RegState::Define)
2647 .addReg(SrcReg, getKillRegState(KillSrc))
2648 .addReg(AArch64::SP)
2651 .addReg(AArch64::SP, RegState::Define)
2652 .addReg(DestReg, RegState::Define)
2653 .addReg(AArch64::SP)
2667 .addReg(SrcReg)
2668 .addReg(SrcReg, getKillRegState(KillSrc));
2671 .addReg(SrcReg, getKillRegState(KillSrc));
2684 .addReg(SrcReg)
2685 .addReg(SrcReg, getKillRegState(KillSrc));
2688 .addReg(SrcReg, getKillRegState(KillSrc));
2701 .addReg(SrcReg)
2702 .addReg(SrcReg, getKillRegState(KillSrc));
2709 .addReg(SrcReg, getKillRegState(KillSrc));
2722 .addReg(SrcReg)
2723 .addReg(SrcReg, getKillRegState(KillSrc));
2730 .addReg(SrcReg, getKillRegState(KillSrc));
2739 .addReg(SrcReg, getKillRegState(KillSrc));
2745 .addReg(SrcReg, getKillRegState(KillSrc));
2752 .addReg(SrcReg, getKillRegState(KillSrc));
2758 .addReg(SrcReg, getKillRegState(KillSrc));
2766 .addReg(SrcReg, getKillRegState(KillSrc))
2767 .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define);
2775 .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));
2798 .addReg(SrcReg0, getKillRegState(IsKill), SubIdx0)
2799 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1)
2903 .addReg(SrcReg, getKillRegState(isKill))
2929 .addReg(DestReg0, RegState::Define | getUndefRegState(IsUndef), SubIdx0)
2930 .addReg(DestReg1, RegState::Define | getUndefRegState(IsUndef), SubIdx1)
3034 .addReg(DestReg, getDefRegState(true))
3097 .addReg(SrcReg)
4022 .addReg(SrcReg0, getKillRegState(Src0IsKill))
4023 .addReg(SrcReg1, getKillRegState(Src1IsKill))
4024 .addReg(SrcReg2, getKillRegState(Src2IsKill));
4027 .addReg(SrcReg2, getKillRegState(Src2IsKill))
4028 .addReg(SrcReg0, getKillRegState(Src0IsKill))
4029 .addReg(SrcReg1, getKillRegState(Src1IsKill))
4033 .addReg(SrcReg2, getKillRegState(Src2IsKill))
4034 .addReg(SrcReg0, getKillRegState(Src0IsKill))
4035 .addReg(SrcReg1, getKillRegState(Src1IsKill));
4087 .addReg(SrcReg0, getKillRegState(Src0IsKill))
4088 .addReg(SrcReg1, getKillRegState(Src1IsKill))
4089 .addReg(VR);
4183 .addReg(ZeroReg)
4217 .addReg(ZeroReg)
4274 .addReg(ZeroReg)
4836 .addReg(NewReg)
5575 .addReg(AArch64::SP, RegState::Define)
5576 .addReg(AArch64::LR)
5577 .addReg(AArch64::SP)
5602 .addReg(AArch64::SP, RegState::Define)
5603 .addReg(AArch64::LR, RegState::Define)
5604 .addReg(AArch64::SP)
5616 .addReg(AArch64::LR, RegState::Undef);
5666 .addReg(AArch64::XZR)
5667 .addReg(AArch64::LR)
5670 .addReg(AArch64::XZR)
5671 .addReg(Reg)
5676 .addReg(AArch64::SP, RegState::Define)
5677 .addReg(AArch64::LR)
5678 .addReg(AArch64::SP)
5681 .addReg(AArch64::SP, RegState::Define)
5682 .addReg(AArch64::LR, RegState::Define)
5683 .addReg(AArch64::SP)
lib/Target/AArch64/AArch64InstructionSelector.cpp 600 .addReg(Copy.getReg(0), 0, SubReg);
1184 .addReg(ShiftReg, 0, AArch64::sub_32);
1631 .addReg(DstReg, 0, AArch64::sub_32);
2839 .addReg(VecReg, 0, ExtractSubReg);
3019 .addReg(InsertRegs[0], 0, ExtractSubReg);
3718 .addReg(TBL1.getReg(0), 0, AArch64::dsub);
3837 .addReg(DemoteVec, 0, SubReg);
3909 .addReg(DstVec, 0, SubReg);
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 765 .addReg(isNarrowStore(Opc) ? AArch64::WZR : AArch64::XZR)
917 .addReg(DstRegW)
918 .addReg(DstRegX, RegState::Define);
923 .addReg(DstRegX)
980 .addReg(IsStoreXReg ? AArch64::XZR : AArch64::WZR)
lib/Target/AArch64/AArch64RegisterInfo.cpp 507 .addReg(ScratchReg)
508 .addReg(ScratchReg)
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 447 .addReg(SrcReg2, Src2IsKill)
451 .addReg(SrcReg0, Src0IsKill)
452 .addReg(SrcReg1, Src1IsKill)
453 .addReg(DupDest, Src2IsKill);
459 .addReg(SrcReg1, Src1IsKill)
463 .addReg(SrcReg0, Src0IsKill)
464 .addReg(DupDest, Src1IsKill);
563 .addReg(StReg[0])
564 .addReg(StReg[1]);
566 .addReg(StReg[0], StRegKill[0])
567 .addReg(StReg[1], StRegKill[1]);
570 .addReg(ZipDest[0])
571 .addReg(ZipDest[1])
572 .addReg(AddrReg)
585 .addReg(StReg[0])
586 .addReg(StReg[2]);
588 .addReg(StReg[0], StRegKill[0])
589 .addReg(StReg[2], StRegKill[2]);
591 .addReg(StReg[1])
592 .addReg(StReg[3]);
594 .addReg(StReg[1], StRegKill[1])
595 .addReg(StReg[3], StRegKill[3]);
597 .addReg(ZipDest[0])
598 .addReg(ZipDest[2]);
600 .addReg(ZipDest[0])
601 .addReg(ZipDest[2]);
603 .addReg(ZipDest[1])
604 .addReg(ZipDest[3]);
606 .addReg(ZipDest[1])
607 .addReg(ZipDest[3]);
610 .addReg(ZipDest[4])
611 .addReg(ZipDest[5])
612 .addReg(AddrReg)
615 .addReg(ZipDest[6])
616 .addReg(ZipDest[7])
617 .addReg(AddrReg)
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 138 .addReg(SrcReg);
227 .addReg(Reg, 0, ComposedSubIdx);
375 .addReg(CarryReg, RegState::Kill)
383 .addReg(DstLo)
385 .addReg(DstHi)
423 .addReg(AMDGPU::SCC);
447 .addReg(I.getOperand(1).getReg(), 0, SubReg);
483 MIB.addReg(Src.getReg(), getUndefRegState(Src.isUndef()));
529 .addReg(SrcReg, SrcFlags, SubRegs[I]);
605 .addReg(Src0Reg)
606 .addReg(Src1Reg)
734 .addReg(AMDGPU::SCC);
766 .addReg(Reg0)
767 .addReg(Reg1)
768 .addReg(Reg2)
769 .addReg(Reg3)
966 .addReg(BaseReg)
967 .addReg(OverflowVal, RegState::Kill)
1105 .addReg(CCReg);
1247 .addReg(SrcReg);
1249 .addReg(TmpReg);
1286 .addReg(SrcReg);
1294 .addReg(SrcReg)
1309 .addReg(SrcReg);
1324 .addReg(SrcReg)
1326 .addReg(UndefReg)
1330 .addReg(ExtReg)
1340 .addReg(SrcReg)
1344 .addReg(SrcReg)
1383 .addReg(Src);
1454 .addReg(LoReg)
1456 .addReg(HiReg)
1592 .addReg(CondReg);
1646 .addReg(SrcReg)
1647 .addReg(ImmReg);
1657 .addReg(SrcReg, 0, AMDGPU::sub0);
1659 .addReg(SrcReg, 0, AMDGPU::sub1);
1662 .addReg(LoReg)
1663 .addReg(ImmReg);
1665 .addReg(MaskLo)
1667 .addReg(HiReg)
1816 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
1830 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
1853 [=](MachineInstrBuilder &MIB) { MIB.addReg(Src); },
1862 [=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); },
1872 [=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); },
1893 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
1913 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
1944 [=](MachineInstrBuilder &MIB) { MIB.addReg(PtrReg); },
1945 [=](MachineInstrBuilder &MIB) { MIB.addReg(OffsetReg); }
1955 [=](MachineInstrBuilder &MIB) { MIB.addReg(Root.getReg()); },
1979 [=](MachineInstrBuilder &MIB) { MIB.addReg(BasePtr); },
2018 MIB.addReg(Info->getScratchRSrcReg());
2021 MIB.addReg(HighBits);
2030 MIB.addReg(SOffsetReg);
2075 MIB.addReg(Info->getScratchRSrcReg());
2081 MIB.addReg(VAddr);
2084 MIB.addReg(SOffset);
2128 MIB.addReg(Info->getScratchRSrcReg());
2130 [=](MachineInstrBuilder &MIB) { MIB.addReg(SOffsetReg); }, // soffset
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 1488 MIB.addReg(CombinedSourceReg);
1500 MIB.addReg(SourceReg);
1532 MIB.addReg(CombinedSourceReg);
1542 MIB.addReg(SourceReg);
1581 MIB.addReg(CombinedSourceReg);
1592 MIB.addReg(SourceReg);
1772 MIB.addReg(IfSourceRegister, RegState::Undef);
1774 MIB.addReg(IfSourceRegister);
1777 MIB.addReg(CodeSourceRegister);
2181 BackedgePHI.addReg(CurrentBackedgeReg);
2183 BackedgePHI.addReg(getPHISourceReg(*PHIDefInstr, 1));
2195 MIB.addReg(SourceReg);
2204 MIB.addReg(CurrentBackedgeReg);
2458 MIB.addReg(PHISource);
2462 MIB.addReg(RegionSourceReg);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 734 .addReg(InitSaveExecReg)
736 .addReg(NewExec)
742 .addReg(std::get<0>(Result)) // Initial value / implicit_def
744 .addReg(std::get<1>(Result)) // Mid-loop value.
784 .addReg(Op.getReg());
794 .addReg(CurrentLaneOpReg)
795 .addReg(Op.getReg());
804 .addReg(NewCondReg)
805 .addReg(CondReg);
846 .addReg(UnmergePiece, 0, AMDGPU::sub0);
851 .addReg(UnmergePiece, 0, AMDGPU::sub1);
877 .addReg(UnmergePiece);
888 .addReg(CurrentLaneOpReg)
889 .addReg(UnmergePiece);
897 .addReg(NewCondReg)
898 .addReg(CondReg);
924 .addReg(CondReg, RegState::Kill);
931 .addReg(ExecReg)
932 .addReg(NewExec);
943 .addReg(ExecReg);
949 .addReg(SaveExecReg);
1010 .addReg(Reg);
lib/Target/AMDGPU/AMDILCFGStructurizer.cpp 497 MIB.addReg(OldMI->getOperand(1).getReg(), false);
509 MachineInstrBuilder(*MF, NewInstr).addReg(RegNum, false);
lib/Target/AMDGPU/GCNDPPCombine.cpp 181 DPPInst.addReg(CombOldVGPR.Reg, Def ? 0 : RegState::Undef,
lib/Target/AMDGPU/GCNHazardRecognizer.cpp 898 .addReg(Reg, RegState::Define | (IsUndef ? RegState::Dead : 0))
899 .addReg(Reg, IsUndef ? RegState::Undef : RegState::Kill);
1130 .addReg(AMDGPU::SGPR_NULL, RegState::Undef)
lib/Target/AMDGPU/R600ISelLowering.cpp 408 .addReg(R600::PREDICATE_BIT, RegState::Kill);
422 .addReg(R600::PREDICATE_BIT, RegState::Kill);
lib/Target/AMDGPU/R600InstrInfo.cpp 84 .addReg(DestReg,
777 .addReg(R600::PREDICATE_BIT, RegState::Kill);
792 .addReg(R600::PREDICATE_BIT, RegState::Kill);
990 MIB.addReg(R600::PREDICATE_BIT, RegState::Implicit);
998 MIB.addReg(R600::PREDICATE_BIT, RegState::Implicit);
1139 .addReg(R600::AR_X,
1172 .addReg(R600::AR_X,
1254 .addReg(Src0Reg) // $src0
1261 MIB.addReg(Src1Reg) // $src1
1271 .addReg(R600::PRED_SEL_OFF) // $pred_sel
lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp 217 .addReg(SrcVec)
218 .addReg(SubReg)
231 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec);
lib/Target/AMDGPU/SIAddIMGInit.cpp 159 .addReg(PrevDst)
160 .addReg(SubReg)
168 MachineInstrBuilder(MF, MI).addReg(NewDst, RegState::Implicit);
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 311 .addReg(TmpReg, RegState::Kill);
lib/Target/AMDGPU/SIFoldOperands.cpp 264 .addReg(AMDGPU::VCC, RegState::Kill);
710 B.addReg(Tmp);
720 B.addReg(Src.Reg, Def->isUndef() ? RegState::Undef : 0,
736 B.addReg(Tmp);
751 TII->get(AMDGPU::V_ACCVGPR_WRITE_B32), Tmp).addReg(Vgpr);
752 B.addReg(Tmp);
lib/Target/AMDGPU/SIFrameLowering.cpp 107 .addReg(SpillReg, RegState::Kill)
108 .addReg(ScratchRsrcReg)
109 .addReg(SPReg)
127 .addReg(SpillReg, RegState::Kill)
128 .addReg(OffsetReg, RegState::Kill)
129 .addReg(ScratchRsrcReg)
130 .addReg(SPReg)
155 .addReg(ScratchRsrcReg)
156 .addReg(SPReg)
175 .addReg(OffsetReg, RegState::Kill)
176 .addReg(ScratchRsrcReg)
177 .addReg(SPReg)
225 .addReg(FlatScrInitLo)
226 .addReg(ScratchWaveOffsetReg);
228 .addReg(FlatScrInitHi)
231 addReg(FlatScrInitLo).
235 addReg(FlatScrInitHi).
242 .addReg(FlatScrInitLo)
243 .addReg(ScratchWaveOffsetReg);
245 .addReg(FlatScrInitHi)
255 .addReg(FlatScrInitHi, RegState::Kill);
260 .addReg(FlatScrInitLo)
261 .addReg(ScratchWaveOffsetReg);
265 .addReg(FlatScrInitLo, RegState::Kill)
490 .addReg(PreloadedPrivateBufferReg, RegState::Kill);
502 .addReg(PreloadedScratchWaveOffsetReg, HasFP ? RegState::Kill : 0);
507 .addReg(PreloadedPrivateBufferReg, RegState::Kill);
523 .addReg(MFI->getScratchWaveOffsetReg());
526 .addReg(MFI->getScratchWaveOffsetReg())
555 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
576 .addReg(GitPtrLo)
577 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
595 .addReg(Rsrc01)
599 .addReg(ScratchRsrcReg, RegState::ImplicitDefine)
621 .addReg(MFI->getImplicitBufferPtrUserSGPR())
622 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
636 .addReg(MFI->getImplicitBufferPtrUserSGPR())
641 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
652 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
656 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
662 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
666 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
713 .addReg(FramePtrReg)
753 .addReg(ScratchExecCopy, RegState::Kill);
770 .addReg(FramePtrReg)
772 .addReg(Spill[0].VGPR, RegState::Undef);
794 .addReg(StackPtrReg)
798 .addReg(ScratchSPReg, RegState::Kill)
808 .addReg(StackPtrReg)
814 .addReg(StackPtrReg)
849 .addReg(StackPtrReg)
856 .addReg(FuncInfo->SGPRForFPSaveRestoreCopy)
871 .addReg(Spill[0].VGPR)
911 .addReg(ScratchExecCopy, RegState::Kill);
1122 .addReg(SPReg)
lib/Target/AMDGPU/SIISelLowering.cpp 2007 .addReg(*I);
2013 .addReg(NewVR);
3151 .addReg(Reg, RegState::Kill)
3190 .addReg(InitReg)
3192 .addReg(ResultReg)
3196 .addReg(InitSaveExecReg)
3198 .addReg(NewExec)
3203 .addReg(IdxReg.getReg(), getUndefRegState(IdxReg.isUndef()));
3207 .addReg(CurrentIdxReg)
3208 .addReg(IdxReg.getReg(), 0, IdxReg.getSubReg());
3214 .addReg(CondReg, RegState::Kill);
3225 .addReg(CurrentIdxReg, RegState::Kill)
3232 .addReg(IdxReg, RegState::Kill)
3239 .addReg(CurrentIdxReg, RegState::Kill);
3242 .addReg(CurrentIdxReg, RegState::Kill)
3252 .addReg(Exec)
3253 .addReg(NewExec);
3296 .addReg(Exec);
3310 .addReg(SaveExec);
3367 .addReg(Tmp, RegState::Kill)
3418 .addReg(SrcReg, RegState::Undef, SubReg)
3419 .addReg(SrcReg, RegState::Implicit)
3420 .addReg(AMDGPU::M0, RegState::Implicit);
3424 .addReg(SrcReg, RegState::Undef, SubReg)
3425 .addReg(SrcReg, RegState::Implicit);
3447 .addReg(SrcReg, RegState::Undef, SubReg)
3448 .addReg(SrcReg, RegState::Implicit)
3449 .addReg(AMDGPU::M0, RegState::Implicit);
3453 .addReg(SrcReg, RegState::Undef, SubReg)
3454 .addReg(SrcReg, RegState::Implicit);
3525 .addReg(SrcVec->getReg(), RegState::Undef, SubReg) // vdst
3527 .addReg(Dst, RegState::ImplicitDefine)
3528 .addReg(SrcVec->getReg(), RegState::Implicit)
3529 .addReg(AMDGPU::M0, RegState::Implicit);
3536 .addReg(Dst, RegState::Define)
3537 .addReg(SrcVec->getReg())
3559 .addReg(PhiReg, RegState::Undef, SubReg) // vdst
3561 .addReg(Dst, RegState::ImplicitDefine)
3562 .addReg(PhiReg, RegState::Implicit)
3563 .addReg(AMDGPU::M0, RegState::Implicit);
3569 .addReg(Dst, RegState::Define)
3570 .addReg(PhiReg)
3638 .addReg(DestSub0)
3640 .addReg(DestSub1)
3705 .addReg(InputReg)
3710 .addReg(CountReg)
3713 .addReg(CountReg, RegState::Kill)
3765 .addReg(SrcCond);
3768 .addReg(Src0, 0, AMDGPU::sub0)
3770 .addReg(Src1, 0, AMDGPU::sub0)
3771 .addReg(SrcCondCopy);
3774 .addReg(Src0, 0, AMDGPU::sub1)
3776 .addReg(Src1, 0, AMDGPU::sub1)
3777 .addReg(SrcCondCopy);
3780 .addReg(DstLo)
3782 .addReg(DstHi)
3804 MIB.addReg(Info->getStackPtrOffsetReg(), RegState::ImplicitDefine)
3805 .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit)
3806 .addReg(Info->getFrameOffsetReg(), RegState::Implicit);
3842 I.addReg(TRI->getVCC(), RegState::Define);
lib/Target/AMDGPU/SIInsertSkips.cpp 170 .addReg(AMDGPU::VGPR0, RegState::Undef)
171 .addReg(AMDGPU::VGPR0, RegState::Undef)
172 .addReg(AMDGPU::VGPR0, RegState::Undef)
173 .addReg(AMDGPU::VGPR0, RegState::Undef)
262 I.addReg(AMDGPU::VCC, RegState::Define);
297 .addReg(Exec)
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 1169 .addReg(AMDGPU::SGPR_NULL, RegState::Undef)
1433 .addReg(TRI->getVCC());
1598 .addReg(AMDGPU::SGPR_NULL, RegState::Undef)
lib/Target/AMDGPU/SIInstrInfo.cpp 521 .addReg(SrcReg, getKillRegState(KillSrc));
537 .addReg(SrcReg, getKillRegState(KillSrc));
553 .addReg(SrcReg, getKillRegState(KillSrc));
559 .addReg(SrcReg, getKillRegState(KillSrc));
571 .addReg(SrcReg, getKillRegState(KillSrc));
579 .addReg(SrcReg, getKillRegState(KillSrc));
585 .addReg(SrcReg, getKillRegState(KillSrc));
597 .addReg(SrcReg, getKillRegState(KillSrc));
604 .addReg(SrcReg, getKillRegState(KillSrc))
672 .addReg(Tmp, RegState::Kill);
677 .addReg(SrcReg, getKillRegState(KillSrc));
723 Builder.addReg(RI.getSubReg(SrcReg, SubIdx));
726 Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
729 Builder.addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
832 .addReg(FalseReg)
834 .addReg(TrueReg)
835 .addReg(SReg);
847 .addReg(FalseReg)
849 .addReg(TrueReg)
850 .addReg(SReg);
861 .addReg(FalseReg)
863 .addReg(TrueReg)
864 .addReg(SReg);
875 .addReg(FalseReg)
877 .addReg(TrueReg)
878 .addReg(SReg);
889 .addReg(TrueReg)
891 .addReg(FalseReg)
892 .addReg(SReg);
907 .addReg(FalseReg)
909 .addReg(TrueReg)
910 .addReg(SReg);
925 .addReg(FalseReg)
927 .addReg(TrueReg)
928 .addReg(SReg);
948 .addReg(SrcReg);
961 .addReg(SrcReg);
1078 .addReg(SrcReg, getKillRegState(isKill)) // data
1081 .addReg(MFI->getScratchRSrcReg(), RegState::Implicit)
1082 .addReg(MFI->getStackPtrOffsetReg(), RegState::Implicit);
1099 MIB.addReg(Tmp, RegState::Define);
1101 MIB.addReg(SrcReg, getKillRegState(isKill)) // data
1103 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
1104 .addReg(MFI->getStackPtrOffsetReg()) // scratch_offset
1207 .addReg(MFI->getScratchRSrcReg(), RegState::Implicit)
1208 .addReg(MFI->getStackPtrOffsetReg(), RegState::Implicit);
1218 MIB.addReg(Tmp, RegState::Define);
1221 .addReg(MFI->getScratchRSrcReg()) // scratch_rsrc
1222 .addReg(MFI->getStackPtrOffsetReg()) // scratch_offset
1269 .addReg(InputPtrReg)
1272 .addReg(InputPtrReg)
1277 .addReg(STmp1)
1278 .addReg(STmp0);
1281 .addReg(STmp1)
1282 .addReg(TIDIGXReg);
1285 .addReg(STmp0)
1286 .addReg(TIDIGYReg)
1287 .addReg(TIDReg);
1290 .addReg(TIDReg)
1291 .addReg(TIDIGZReg)
1303 .addReg(TIDReg);
1309 .addReg(TIDReg);
1317 .addReg(TIDReg)
1430 .addReg(Dst, RegState::Implicit | RegState::Define);
1433 .addReg(Dst, RegState::Implicit | RegState::Define);
1437 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub0))
1438 .addReg(Dst, RegState::Implicit | RegState::Define);
1440 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1))
1441 .addReg(Dst, RegState::Implicit | RegState::Define);
1454 .addReg(Exec);
1458 .addReg(Exec);
1466 .addReg(Exec);
1472 .addReg(Exec);
1489 .addReg(RI.getSubReg(VecReg, SubReg), RegState::Undef)
1491 .addReg(VecReg, RegState::ImplicitDefine)
1492 .addReg(VecReg,
1517 .addReg(RegLo)
1521 .addReg(RegHi);
1597 MovDPP.addReg(RI.getSubReg(Src, Sub));
1599 MovDPP.addReg(Src, SrcOp.isUndef() ? RegState::Undef : 0, Sub);
1612 .addReg(Split[0]->getOperand(0).getReg())
1614 .addReg(Split[1]->getOperand(0).getReg())
1793 .addReg(PCReg, RegState::Define, AMDGPU::sub0)
1794 .addReg(PCReg, 0, AMDGPU::sub0)
1797 .addReg(PCReg, RegState::Define, AMDGPU::sub1)
1798 .addReg(PCReg, 0, AMDGPU::sub1)
1803 .addReg(PCReg, RegState::Define, AMDGPU::sub0)
1804 .addReg(PCReg, 0, AMDGPU::sub0)
1807 .addReg(PCReg, RegState::Define, AMDGPU::sub1)
1808 .addReg(PCReg, 0, AMDGPU::sub1)
1814 .addReg(PCReg);
2178 .addReg(FalseReg)
2179 .addReg(TrueReg);
2188 .addReg(FalseReg)
2189 .addReg(TrueReg);
2242 .addReg(FalseReg, 0, SubIdx)
2243 .addReg(TrueReg, 0, SubIdx);
2247 MIB.addReg(DstElt)
3865 .addReg(SuperReg.getReg(), 0, SubIdx);
3876 .addReg(SuperReg.getReg(), 0, SuperReg.getSubReg());
3879 .addReg(NewSuperReg, 0, SubIdx);
4223 .addReg(SrcReg);
4230 .addReg(SrcReg);
4239 .addReg(SrcReg, 0, RI.getSubRegFromChannel(i));
4247 MIB.addReg(SRegs[i]);
4351 .addReg(VRsrc, VRsrcUndef, AMDGPU::sub0);
4353 .addReg(VRsrc, VRsrcUndef, AMDGPU::sub1);
4355 .addReg(VRsrc, VRsrcUndef, AMDGPU::sub2);
4357 .addReg(VRsrc, VRsrcUndef, AMDGPU::sub3);
4360 .addReg(SRsrcSub0)
4362 .addReg(SRsrcSub1)
4364 .addReg(SRsrcSub2)
4366 .addReg(SRsrcSub3)
4375 .addReg(SRsrc, 0, AMDGPU::sub0_sub1)
4376 .addReg(VRsrc, 0, AMDGPU::sub0_sub1);
4378 .addReg(SRsrc, 0, AMDGPU::sub2_sub3)
4379 .addReg(VRsrc, 0, AMDGPU::sub2_sub3);
4381 .addReg(CondReg0)
4382 .addReg(CondReg1);
4388 .addReg(AndCond, RegState::Kill);
4395 .addReg(Exec)
4396 .addReg(SaveExec);
4418 BuildMI(MBB, I, DL, TII.get(MovExecOpc), SaveExec).addReg(Exec);
4467 BuildMI(*RemainderBB, First, DL, TII.get(MovExecOpc), Exec).addReg(SaveExec);
4503 .addReg(Zero64)
4505 .addReg(SRsrcFormatLo)
4507 .addReg(SRsrcFormatHi)
4713 .addReg(RsrcPtr, 0, AMDGPU::sub0)
4714 .addReg(VAddr->getReg(), 0, AMDGPU::sub0)
4720 .addReg(RsrcPtr, 0, AMDGPU::sub1)
4721 .addReg(VAddr->getReg(), 0, AMDGPU::sub1)
4722 .addReg(CondReg0, RegState::Kill)
4727 .addReg(NewVAddrLo)
4729 .addReg(NewVAddrHi)
4760 .addReg(NewVAddr)
4761 .addReg(NewSRsrc)
4791 .addReg(NewVAddr)
4792 .addReg(NewSRsrc)
4804 .addReg(RsrcPtr, 0, AMDGPU::sub0)
4806 .addReg(RsrcPtr, 0, AMDGPU::sub1)
4952 .addReg(AMDGPU::EXEC_LO)
4953 .addReg(AMDGPU::VCC_LO);
4957 .addReg(AMDGPU::EXEC)
4958 .addReg(AMDGPU::VCC);
5153 .addReg(Src.getReg());
5156 .addReg(Src.getReg())
5157 .addReg(TmpReg);
5204 .addReg(Temp)
5210 .addReg(Temp);
5216 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest).addReg(Temp);
5248 .addReg(Interm);
5277 .addReg(Interm);
5323 .addReg(DestSub0)
5325 .addReg(DestSub1)
5381 .addReg(CarryReg, RegState::Define)
5389 .addReg(DeadCarryReg, RegState::Define | RegState::Dead)
5392 .addReg(CarryReg, RegState::Kill)
5396 .addReg(DestSub0)
5398 .addReg(DestSub1)
5462 .addReg(DestSub0)
5464 .addReg(DestSub1)
5510 .addReg(Interm)
5546 BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg);
5579 .addReg(Inst.getOperand(1).getReg(), 0, AMDGPU::sub0)
5585 .addReg(MidRegLo);
5588 .addReg(MidRegLo)
5590 .addReg(MidRegHi)
5604 .addReg(Src.getReg(), 0, AMDGPU::sub0);
5607 .addReg(Src.getReg(), 0, AMDGPU::sub0)
5609 .addReg(TmpReg)
5672 .addReg(ImmReg, RegState::Kill)
5678 .addReg(TmpReg, RegState::Kill);
5686 .addReg(ImmReg, RegState::Kill)
5701 .addReg(ImmReg, RegState::Kill)
5702 .addReg(TmpReg, RegState::Kill);
6082 .addReg(DstReg);
6110 HeaderPHIBuilder.addReg(BackEdgeReg);
6116 HeaderPHIBuilder.addReg(ZeroReg);
6123 .addReg(DstReg)
6127 .addReg(BackEdgeReg)
6201 .addReg(UnusedCarry, RegState::Define | RegState::Dead);
6218 .addReg(UnusedCarry, RegState::Define | RegState::Dead);
6532 return BuildMI(MBB, Cur, DL, get(TargetOpcode::COPY), Dst).addReg(Src);
6553 .addReg(Src, 0, SrcSubReg)
6554 .addReg(AMDGPU::EXEC, RegState::Implicit);
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 919 .addReg(ImmReg)
920 .addReg(AddrReg->getReg(), 0, BaseSubReg)
927 .addReg(BaseReg, BaseRegFlags, BaseSubReg) // addr
940 .addReg(DestReg, 0, SubRegIdx0);
943 .addReg(DestReg, RegState::Kill, SubRegIdx1);
1012 .addReg(ImmReg)
1013 .addReg(AddrReg->getReg(), 0, BaseSubReg)
1020 .addReg(BaseReg, BaseRegFlags, BaseSubReg) // addr
1079 .addReg(DestReg, 0, SubRegIdx0);
1082 .addReg(DestReg, RegState::Kill, SubRegIdx1);
1129 .addReg(DestReg, 0, SubRegIdx0);
1132 .addReg(DestReg, RegState::Kill, SubRegIdx1);
1191 .addReg(DestReg, 0, SubRegIdx0);
1194 .addReg(DestReg, RegState::Kill, SubRegIdx1);
1320 .addReg(SrcReg, RegState::Kill);
1398 .addReg(CarryReg, RegState::Define)
1399 .addReg(Addr.Base.LoReg, 0, Addr.Base.LoSubReg)
1407 .addReg(DeadCarryReg, RegState::Define | RegState::Dead)
1408 .addReg(Addr.Base.HiReg, 0, Addr.Base.HiSubReg)
1410 .addReg(CarryReg, RegState::Kill)
1418 .addReg(DestSub0)
1420 .addReg(DestSub1)
lib/Target/AMDGPU/SILowerControlFlow.cpp 220 .addReg(Exec)
221 .addReg(Exec, RegState::ImplicitDefine);
227 .addReg(CopyReg)
236 .addReg(Tmp)
237 .addReg(CopyReg);
245 .addReg(Tmp, RegState::Kill);
304 .addReg(CopyReg);
313 .addReg(Exec)
314 .addReg(SaveReg);
322 .addReg(Exec)
323 .addReg(DstReg);
376 .addReg(Exec)
379 .addReg(Dst)
401 .addReg(Exec)
427 .addReg(Exec)
lib/Target/AMDGPU/SILowerI1Copies.cpp 530 .addReg(SrcReg);
705 .addReg(SrcReg)
824 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(CurReg);
826 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg);
829 .addReg(ExecReg)
843 .addReg(PrevReg)
844 .addReg(ExecReg);
854 .addReg(CurReg)
855 .addReg(ExecReg);
861 .addReg(CurMaskedReg);
864 .addReg(PrevMaskedReg);
867 .addReg(CurMaskedReg)
868 .addReg(ExecReg);
871 .addReg(PrevMaskedReg)
872 .addReg(CurMaskedReg ? CurMaskedReg : ExecReg);
lib/Target/AMDGPU/SIMemoryLegalizer.cpp 1113 .addReg(AMDGPU::SGPR_NULL, RegState::Undef)
lib/Target/AMDGPU/SIOptimizeExecMasking.cpp 410 .addReg(OtherOp->getReg());
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 261 .addReg(ExecReg)
262 .addReg(CCReg, getUndefRegState(CC->isUndef()), CC->getSubReg());
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 510 MIB.addReg(getPreservedOperand()->getReg(),
1023 SDWAInst.addReg(TRI->getVCC(), RegState::Define);
1198 Copy.addReg(Op.getReg(), Op.isKill() ? RegState::Kill : 0,
lib/Target/AMDGPU/SIRegisterInfo.cpp 372 .addReg(OffsetReg, RegState::Kill)
373 .addReg(FIReg)
569 .addReg(Src, getKillRegState(IsKill));
680 .addReg(ScratchOffsetReg)
706 .addReg(SubReg, getKillRegState(IsKill));
716 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill))
717 .addReg(ScratchRsrcReg)
718 .addReg(SOffset, SOffsetRegState)
730 .addReg(TmpReg, RegState::Kill);
734 MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState);
740 .addReg(ScratchOffsetReg)
807 .addReg(SubReg, getKillRegState(IsKill))
809 .addReg(Spill.VGPR, VGPRDefined ? 0 : RegState::Undef);
825 .addReg(SubReg, SubKillState);
834 Mov.addReg(SuperReg, RegState::Implicit | SuperKillState);
844 .addReg(TmpVGPR, RegState::Kill) // src
846 .addReg(MFI->getScratchRSrcReg()) // srrsrc
847 .addReg(MFI->getStackPtrOffsetReg()) // soffset
855 .addReg(M0CopyReg, RegState::Kill);
905 .addReg(Spill.VGPR)
909 MIB.addReg(SuperReg, RegState::ImplicitDefine);
929 .addReg(MFI->getScratchRSrcReg()) // srsrc
930 .addReg(MFI->getStackPtrOffsetReg()) // soffset
936 .addReg(TmpVGPR, RegState::Kill);
939 MIB.addReg(MI->getOperand(0).getReg(), RegState::ImplicitDefine);
945 .addReg(M0CopyReg, RegState::Kill);
1111 .addReg(FrameReg)
1112 .addReg(MFI->getScratchWaveOffsetReg());
1119 .addReg(DiffReg);
1128 .addReg(DiffReg, RegState::Kill);
1136 MIB.addReg(ScaledReg, RegState::Kill);
1148 MIB.addReg(ConstOffsetReg, RegState::Kill);
1149 MIB.addReg(ScaledReg, RegState::Kill);
1165 .addReg(DiffReg, RegState::Kill)
1168 .addReg(ScaledReg, RegState::Kill)
1171 .addReg(ScaledReg, RegState::Kill);
1176 .addReg(ScaledReg, RegState::Kill)
1179 .addReg(DiffReg, RegState::Kill)
1188 .addReg(FrameReg)
1189 .addReg(MFI->getScratchWaveOffsetReg());
lib/Target/AMDGPU/SIShrinkInstructions.cpp 532 .addReg(Y1.Reg, 0, Y1.SubReg)
533 .addReg(X1.Reg, 0, X1.SubReg).getInstr();
lib/Target/AMDGPU/SIWholeQuadMode.cpp 563 .addReg(AMDGPU::SCC);
566 .addReg(SaveReg);
635 .addReg(LiveMaskReg);
641 .addReg(Exec)
642 .addReg(LiveMaskReg);
656 .addReg(SavedWQM);
661 .addReg(Exec);
686 .addReg(SavedOrig);
846 .addReg(LiveMaskReg);
906 .addReg(Exec);
917 .addReg(Exec);
lib/Target/ARC/ARCBranchFinalize.cpp 120 .addReg(MI->getOperand(1).getReg())
134 .addReg(MI->getOperand(1).getReg())
lib/Target/ARC/ARCExpandPseudos.cpp 66 .addReg(SI.getOperand(1).getReg())
70 .addReg(SI.getOperand(0).getReg())
71 .addReg(AddrReg)
lib/Target/ARC/ARCFrameLowering.cpp 73 .addReg(StackPtr)
144 .addReg(ARC::SP)
150 .addReg(ARC::SP, RegState::Define)
151 .addReg(ARC::FP)
152 .addReg(ARC::SP)
162 .addReg(ARC::SP)
163 .addReg(ARC::SP)
167 .addReg(ARC::BLINK, RegState::Implicit | RegState::Kill);
191 .addReg(ARC::SP)
259 .addReg(ARC::FP)
289 .addReg(ARC::SP)
297 .addReg(ARC::BLINK, RegState::Implicit | RegState::Kill);
304 .addReg(ARC::SP)
314 .addReg(ARC::FP, RegState::Define)
315 .addReg(ARC::SP, RegState::Define)
316 .addReg(ARC::SP)
331 .addReg(ARC::SP)
332 .addReg(ARC::SP)
465 .addReg(Reg, RegState::Kill)
lib/Target/ARC/ARCInstrInfo.cpp 290 .addReg(SrcReg, getKillRegState(KillSrc));
316 .addReg(SrcReg, getKillRegState(isKill))
343 .addReg(DestReg, RegState::Define)
lib/Target/ARC/ARCRegisterInfo.cpp 51 .addReg(BaseReg)
76 .addReg(BaseReg, RegState::Define)
77 .addReg(FrameReg)
94 .addReg(BaseReg, KillState)
107 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
108 .addReg(BaseReg, KillState)
116 .addReg(Reg, RegState::Define)
117 .addReg(FrameReg)
lib/Target/ARM/A15SDOptimizer.cpp 425 .addReg(Reg)
442 .addReg(DReg, 0, Lane);
456 .addReg(Reg1)
458 .addReg(Reg2)
471 .addReg(Ssub0)
472 .addReg(Ssub1)
486 .addReg(DReg)
487 .addReg(ToInsert)
lib/Target/ARM/ARMBaseInstrInfo.cpp 192 .addReg(BaseReg)
201 .addReg(BaseReg)
202 .addReg(OffReg)
203 .addReg(0)
210 .addReg(BaseReg)
211 .addReg(OffReg)
223 .addReg(BaseReg)
230 .addReg(BaseReg)
231 .addReg(OffReg)
243 .addReg(WBReg)
248 .addReg(MI.getOperand(1).getReg())
249 .addReg(WBReg)
250 .addReg(0)
259 .addReg(BaseReg)
264 .addReg(MI.getOperand(1).getReg())
265 .addReg(BaseReg)
266 .addReg(0)
505 .addReg(Pred[1].getReg());
785 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
803 MIB.addReg(SrcReg, getKillRegState(KillSrc))
805 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
810 MIB.addReg(0);
816 MIB.addReg(DestReg, RegState::Undef);
821 MIB.addReg(ARM::VPR, RegState::Implicit);
827 MIB.addReg(Inactive);
839 .addReg(SrcReg, getKillRegState(KillSrc))
862 MIB.addReg(SrcReg, getKillRegState(KillSrc));
864 MIB.addReg(SrcReg, getKillRegState(KillSrc));
932 .addReg(SrcReg, getKillRegState(KillSrc))
938 .addReg(SrcReg, getKillRegState(KillSrc))
944 .addReg(SrcReg, getKillRegState(KillSrc))
950 .addReg(SrcReg, getKillRegState(KillSrc))
976 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
979 Mov.addReg(Src);
1020 return MIB.addReg(Reg, State);
1023 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
1024 return MIB.addReg(Reg, State, SubIdx);
1044 .addReg(SrcReg, getKillRegState(isKill))
1055 .addReg(SrcReg, getKillRegState(isKill))
1062 .addReg(SrcReg, getKillRegState(isKill))
1069 .addReg(SrcReg, getKillRegState(isKill))
1080 .addReg(SrcReg, getKillRegState(isKill))
1090 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
1112 .addReg(SrcReg, getKillRegState(isKill))
1117 .addReg(SrcReg, getKillRegState(isKill))
1125 MIB.addReg(SrcReg, getKillRegState(isKill))
1141 .addReg(SrcReg, getKillRegState(isKill))
1166 .addReg(SrcReg, getKillRegState(isKill))
1329 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
1343 MIB.addReg(DestReg, RegState::ImplicitDefine);
1389 MIB.addReg(DestReg, RegState::ImplicitDefine);
1413 MIB.addReg(DestReg, RegState::ImplicitDefine);
1433 MIB.addReg(DestReg, RegState::ImplicitDefine);
1560 LDM.addReg(Reg, RegState::Define);
1561 STM.addReg(Reg, RegState::Kill);
1634 MIB.addReg(SrcRegS, RegState::Implicit);
2366 .addReg(BaseReg, RegState::Kill)
2389 .addReg(BaseReg, RegState::Kill)
3320 .addReg(Reg1, getKillRegState(isKill))
4785 MIB.addReg(Reg, RegState::Kill).addImm(0);
4795 MIB.addReg(Reg, RegState::Kill)
4957 MIB.addReg(DstReg, RegState::Define)
4958 .addReg(SrcReg)
4959 .addReg(SrcReg)
4980 MIB.addReg(DstReg, RegState::Define)
4981 .addReg(DReg, RegState::Undef)
4987 MIB.addReg(SrcReg, RegState::Implicit);
5010 MIB.addReg(DReg, RegState::Define)
5011 .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI)))
5012 .addReg(SrcReg)
5018 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
5020 MIB.addReg(ImplicitSReg, RegState::Implicit);
5046 MIB.addReg(DDst, RegState::Define)
5047 .addReg(DDst, getUndefRegState(!MI.readsRegister(DDst, TRI)))
5053 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
5054 MIB.addReg(SrcReg, RegState::Implicit);
5056 MIB.addReg(ImplicitSReg, RegState::Implicit);
5081 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
5085 NewMIB.addReg(CurReg, getUndefRegState(CurUndef))
5090 NewMIB.addReg(SrcReg, RegState::Implicit);
5093 MIB.addReg(DDst, RegState::Define);
5099 MIB.addReg(CurReg, getUndefRegState(CurUndef));
5103 MIB.addReg(CurReg, getUndefRegState(CurUndef))
5108 MIB.addReg(SrcReg, RegState::Implicit);
5112 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
5114 MIB.addReg(ImplicitSReg, RegState::Implicit);
lib/Target/ARM/ARMBaseRegisterInfo.cpp 470 .addReg(DestReg, getDefRegState(true), SubIdx)
lib/Target/ARM/ARMConstantIslandPass.cpp 1718 .addMBB(NextBB).addImm(CC).addReg(CCReg);
1974 .addReg(Reg, getKillRegState(RegKilled))
2297 .addReg(User.MI->getOperand(0).getReg(),
2299 .addReg(IdxReg, getKillRegState(IdxRegKill))
lib/Target/ARM/ARMExpandPseudoInsts.cpp 498 MIB.addReg(DstRegPair, RegState::Define | getDeadRegState(DstIsDead));
502 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
504 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
506 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
508 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
569 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
630 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
632 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
634 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
636 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
645 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
689 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
691 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
693 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
695 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
716 MIB.addReg(D0, SrcFlags);
718 MIB.addReg(D1, SrcFlags);
720 MIB.addReg(D2, SrcFlags);
722 MIB.addReg(D3, SrcFlags);
737 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
766 MIB.addReg(D0);
777 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
848 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
849 .addReg(DstReg);
859 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp());
860 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp());
880 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
881 .addReg(DstReg);
910 LO16.addImm(Pred).addReg(PredReg);
911 HI16.addImm(Pred).addReg(PredReg);
956 .addReg(DesiredReg, RegState::Kill);
969 MIB.addReg(AddrReg);
976 .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
977 .addReg(DesiredReg)
983 .addReg(ARM::CPSR, RegState::Kill);
992 .addReg(NewReg)
993 .addReg(AddrReg);
1000 .addReg(TempReg, RegState::Kill)
1006 .addReg(ARM::CPSR, RegState::Kill);
1041 MIB.addReg(RegLo, Flags);
1042 MIB.addReg(RegHi, Flags);
1044 MIB.addReg(Reg.getReg(), Flags);
1087 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
1091 .addReg(DestLo, getKillRegState(Dest.isDead()))
1092 .addReg(DesiredLo)
1096 .addReg(DestHi, getKillRegState(Dest.isDead()))
1097 .addReg(DesiredHi)
1098 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
1104 .addReg(ARM::CPSR, RegState::Kill);
1116 MIB.addReg(AddrReg).add(predOps(ARMCC::AL));
1120 .addReg(TempReg, RegState::Kill)
1126 .addReg(ARM::CPSR, RegState::Kill);
1201 .addReg(JumpTarget.getReg(), RegState::Kill);
1370 .addReg(ARM::R6, RegState::Kill)
1390 .addReg(ARM::CPSR, RegState::Define);
1431 MIB.addReg(Reg, RegState::Kill);
1459 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1460 .addReg(DstReg)
1514 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1515 .addReg(DstReg)
1549 .addReg(DstReg)
1555 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1556 .addReg(DstReg).addImm(LabelId);
1577 .addReg(ARM::LR)
1581 .addReg(ARM::CPSR, RegState::Undef);
1606 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1607 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1610 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1638 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0)
1639 .addReg(D1, SrcIsKill ? RegState::Kill : 0);
1934 .addReg(Reg);
1941 .addReg(ARM::SP, RegState::Define)
1942 .addReg(ARM::SP)
1944 .addReg(Reg);
lib/Target/ARM/ARMFastISel.cpp 312 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
315 .addReg(Op0, Op0IsKill * RegState::Kill));
318 .addReg(II.ImplicitDefs[0]));
338 .addReg(Op0, Op0IsKill * RegState::Kill)
339 .addReg(Op1, Op1IsKill * RegState::Kill));
342 .addReg(Op0, Op0IsKill * RegState::Kill)
343 .addReg(Op1, Op1IsKill * RegState::Kill));
346 .addReg(II.ImplicitDefs[0]));
364 .addReg(Op0, Op0IsKill * RegState::Kill)
368 .addReg(Op0, Op0IsKill * RegState::Kill)
372 .addReg(II.ImplicitDefs[0]));
391 .addReg(II.ImplicitDefs[0]));
404 .addReg(SrcReg));
414 .addReg(SrcReg));
460 .addReg(0));
614 .addReg(DestReg)
628 .addReg(DestReg)
633 .addReg(DestReg)
893 MIB.addReg(0);
901 MIB.addReg(Addr.Base.Reg);
907 MIB.addReg(0);
1013 .addReg(ResultReg));
1069 .addReg(SrcReg).addImm(1));
1117 .addReg(SrcReg));
1143 .addReg(SrcReg);
1267 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1280 .addReg(OpReg).addImm(1));
1290 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1317 .addReg(CmpReg)
1328 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1341 TII.get(Opc)).addReg(AddrReg));
1449 .addReg(SrcReg1).addReg(SrcReg2));
1449 .addReg(SrcReg1).addReg(SrcReg2));
1453 .addReg(SrcReg1);
1492 .addReg(ZeroReg).addImm(1)
1493 .addImm(ARMPred).addReg(ARM::CPSR);
1513 .addReg(Op));
1532 .addReg(Op));
1577 TII.get(Opc), ResultReg).addReg(FP));
1604 TII.get(Opc), ResultReg).addReg(Op));
1653 .addReg(CondReg)
1674 .addReg(Op2Reg)
1675 .addReg(Op1Reg)
1677 .addReg(ARM::CPSR);
1682 .addReg(Op1Reg)
1685 .addReg(ARM::CPSR);
1784 .addReg(SrcReg1).addReg(SrcReg2));
1784 .addReg(SrcReg1).addReg(SrcReg2));
1831 .addReg(Op1).addReg(Op2));
1831 .addReg(Op1).addReg(Op2));
1994 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(Arg);
2009 .addReg(NextVA.getLocReg(), RegState::Define)
2010 .addReg(Arg));
2058 .addReg(RVLocs[0].getLocReg())
2059 .addReg(RVLocs[1].getLocReg()));
2079 ResultReg).addReg(RVLocs[0].getLocReg());
2163 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
2173 MIB.addReg(R, RegState::Implicit);
2271 MIB.addReg(CalleeReg);
2277 MIB.addReg(R, RegState::Implicit);
2413 MIB.addReg(CalleeReg);
2421 MIB.addReg(R, RegState::Implicit);
2513 .addReg(SrcReg).addImm(0));
2724 MIB.addReg(ARM::CPSR, RegState::Define);
2726 MIB.addReg(SrcReg, isKill * RegState::Kill)
2804 .addReg(Reg1);
2809 MIB.addReg(Reg2);
2983 .addReg(TempReg)
2993 .addReg(DestReg)
3066 ResultReg).addReg(DstReg, getKillRegState(true));
lib/Target/ARM/ARMFrameLowering.cpp 304 .addReg(Reg, RegState::Kill)
309 .addReg(Reg, RegState::Kill)
319 .addReg(Reg, RegState::Kill)
324 .addReg(Reg, RegState::Kill)
334 .addReg(Reg, RegState::Kill)
540 .addReg(ARM::R4, RegState::Implicit)
550 .addReg(ARM::R12, RegState::Kill)
551 .addReg(ARM::R4, RegState::Implicit)
557 .addReg(ARM::SP, RegState::Kill)
558 .addReg(ARM::R4, RegState::Kill)
734 .addReg(ARM::SP, RegState::Kill)
739 .addReg(ARM::R4, RegState::Kill)
754 .addReg(ARM::SP)
759 .addReg(ARM::SP)
836 .addReg(ARM::R4)
843 .addReg(FramePtr)
848 .addReg(FramePtr)
1025 .addReg(ARM::SP)
1029 MIB.addReg(Regs[i].first, getKillRegState(Regs[i].second));
1032 .addReg(Regs[0].first, getKillRegState(Regs[0].second))
1033 .addReg(ARM::SP)
1121 .addReg(ARM::SP)
1124 MIB.addReg(Regs[i], getDefRegState(true));
1139 .addReg(ARM::SP, RegState::Define)
1140 .addReg(ARM::SP);
1144 MIB.addReg(0);
1210 .addReg(ARM::SP)
1229 .addReg(ARM::R4)
1245 .addReg(ARM::R4, RegState::Kill)
1247 .addReg(NextReg)
1248 .addReg(SupReg, RegState::ImplicitKill)
1264 .addReg(ARM::R4)
1266 .addReg(NextReg)
1267 .addReg(SupReg, RegState::ImplicitKill)
1279 .addReg(ARM::R4)
1281 .addReg(SupReg)
1292 .addReg(NextReg)
1293 .addReg(ARM::R4)
1376 .addReg(ARM::R4, RegState::Define)
1377 .addReg(ARM::R4, RegState::Kill)
1379 .addReg(SupReg, RegState::ImplicitDefine)
1394 .addReg(ARM::R4)
1396 .addReg(SupReg, RegState::ImplicitDefine)
1407 .addReg(ARM::R4)
1417 .addReg(ARM::R4)
2354 .addReg(ScratchReg0)
2355 .addReg(ScratchReg1);
2358 .addReg(ARM::SP, RegState::Define)
2359 .addReg(ARM::SP)
2361 .addReg(ScratchReg0)
2362 .addReg(ScratchReg1);
2383 .addReg(ARM::SP)
2387 .addReg(ARM::SP)
2396 .addReg(ScratchReg1)
2401 .addReg(ARM::SP)
2421 .addReg(ScratchReg0)
2442 .addReg(ScratchReg0)
2451 .addReg(ScratchReg0)
2452 .addReg(ScratchReg1)
2459 .addReg(ARM::CPSR);
2497 .addReg(ARM::LR);
2500 .addReg(ARM::SP, RegState::Define)
2501 .addReg(ARM::SP)
2503 .addReg(ARM::LR);
2532 .addReg(ScratchReg0);
2534 .addReg(ScratchReg0)
2538 .addReg(ARM::LR, RegState::Define)
2539 .addReg(ARM::SP, RegState::Define)
2540 .addReg(ARM::SP)
2546 .addReg(ARM::SP, RegState::Define)
2547 .addReg(ARM::SP)
2549 .addReg(ARM::LR);
2559 .addReg(ScratchReg0)
2560 .addReg(ScratchReg1);
2563 .addReg(ARM::SP, RegState::Define)
2564 .addReg(ARM::SP)
2566 .addReg(ScratchReg0)
2567 .addReg(ScratchReg1);
2583 .addReg(ScratchReg0)
2584 .addReg(ScratchReg1);
2587 .addReg(ARM::SP, RegState::Define)
2588 .addReg(ARM::SP)
2590 .addReg(ScratchReg0)
2591 .addReg(ScratchReg1);
lib/Target/ARM/ARMISelLowering.cpp 9386 .addReg(NewVReg1, RegState::Kill)
9392 .addReg(NewVReg2, RegState::Kill)
9395 .addReg(NewVReg3, RegState::Kill)
9415 .addReg(NewVReg1, RegState::Kill)
9420 .addReg(ARM::CPSR, RegState::Define)
9425 .addReg(ARM::CPSR, RegState::Define)
9426 .addReg(NewVReg2, RegState::Kill)
9427 .addReg(NewVReg3, RegState::Kill)
9434 .addReg(NewVReg4, RegState::Kill)
9435 .addReg(NewVReg5, RegState::Kill)
9452 .addReg(NewVReg1, RegState::Kill)
9456 .addReg(NewVReg2, RegState::Kill)
9581 .addReg(NewVReg1)
9594 .addReg(VReg1)
9600 .addReg(NewVReg1)
9601 .addReg(VReg2)
9608 .addReg(ARM::CPSR);
9617 .addReg(NewVReg3, RegState::Kill)
9618 .addReg(NewVReg1)
9624 .addReg(NewVReg4, RegState::Kill)
9625 .addReg(NewVReg1)
9637 .addReg(NewVReg1)
9653 .addReg(VReg1, RegState::Define)
9657 .addReg(NewVReg1)
9658 .addReg(VReg1)
9665 .addReg(ARM::CPSR);
9669 .addReg(ARM::CPSR, RegState::Define)
9670 .addReg(NewVReg1)
9681 .addReg(ARM::CPSR, RegState::Define)
9682 .addReg(NewVReg2, RegState::Kill)
9683 .addReg(NewVReg3)
9691 .addReg(NewVReg4, RegState::Kill)
9700 .addReg(ARM::CPSR, RegState::Define)
9701 .addReg(NewVReg5, RegState::Kill)
9702 .addReg(NewVReg3)
9707 .addReg(NewVReg6, RegState::Kill)
9719 .addReg(NewVReg1)
9732 .addReg(VReg1)
9738 .addReg(NewVReg1)
9739 .addReg(VReg2)
9754 .addReg(VReg1, RegState::Define)
9759 .addReg(NewVReg1)
9760 .addReg(VReg1, RegState::Kill)
9767 .addReg(ARM::CPSR);
9771 .addReg(NewVReg1)
9784 .addReg(NewVReg3, RegState::Kill)
9785 .addReg(NewVReg4)
9792 .addReg(NewVReg5, RegState::Kill)
9793 .addReg(NewVReg4)
9797 .addReg(NewVReg5, RegState::Kill)
9860 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
9934 .addReg(AddrOut, RegState::Define)
9935 .addReg(AddrIn)
9941 .addReg(AddrIn)
9946 .addReg(AddrIn)
9951 .addReg(AddrOut, RegState::Define)
9952 .addReg(AddrIn)
9957 .addReg(AddrOut, RegState::Define)
9958 .addReg(AddrIn)
9959 .addReg(0)
9975 .addReg(AddrIn)
9977 .addReg(Data)
9982 .addReg(Data)
9983 .addReg(AddrIn)
9988 .addReg(AddrIn)
9993 .addReg(Data)
9994 .addReg(AddrIn)
9999 .addReg(Data)
10000 .addReg(AddrIn)
10001 .addReg(0)
10140 .addReg(Vtmp)
10159 .addReg(varEnd, RegState::Define)
10165 .addReg(varEnd, RegState::Define)
10187 .addReg(varLoop).addMBB(loopMBB)
10188 .addReg(varEnd).addMBB(entryBB);
10190 .addReg(srcLoop).addMBB(loopMBB)
10191 .addReg(src).addMBB(entryBB);
10193 .addReg(destLoop).addMBB(loopMBB)
10194 .addReg(dest).addMBB(entryBB);
10208 .addReg(varPhi)
10215 MIB.addReg(varPhi)
10224 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
10292 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
10293 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
10294 .addReg(ARM::R12,
10296 .addReg(ARM::CPSR,
10307 .addReg(Reg, RegState::Kill)
10308 .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
10309 .addReg(ARM::R4, RegState::Implicit | RegState::Define)
10310 .addReg(ARM::R12,
10312 .addReg(ARM::CPSR,
10319 .addReg(ARM::SP, RegState::Kill)
10320 .addReg(ARM::R4, RegState::Kill)
10349 .addReg(MI.getOperand(0).getReg())
10355 .addReg(ARM::CPSR);
10516 .addReg(MI.getOperand(4).getReg());
10531 .addReg(MI.getOperand(1).getReg())
10533 .addReg(MI.getOperand(2).getReg())
10553 .addReg(LHS1)
10557 .addReg(LHS2).addImm(0)
10558 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
10563 .addReg(LHS1)
10564 .addReg(RHS1)
10567 .addReg(LHS2).addReg(RHS2)
10567 .addReg(LHS2).addReg(RHS2)
10568 .addImm(ARMCC::EQ).addReg(ARM::CPSR);
10577 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
10645 .addReg(ABSSrcReg)
10652 .addImm(ARMCC::getOppositeCondition(ARMCC::MI)).addReg(ARM::CPSR);
10659 .addReg(ABSSrcReg, ABSSrcKIll ? RegState::Kill : 0)
10668 .addReg(NewRsbDstReg).addMBB(RSBBB)
10669 .addReg(ABSSrcReg).addMBB(BB);
10711 MIB.addReg(TmpReg, RegState::Define|RegState::Dead);
17126 .addReg(*I);
17132 .addReg(NewVR);
lib/Target/ARM/ARMInstrInfo.cpp 132 .addReg(Reg, RegState::Kill)
lib/Target/ARM/ARMInstructionSelector.cpp 696 .addReg(AddressReg)
736 MIB.addReg(ARM::R9) // FIXME: don't hardcode R9
737 .addReg(Offset)
1119 MIB.addReg(0);
1142 .addReg(I.getOperand(0).getReg())
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 552 .addReg(Base)
555 .addReg(PredReg);
573 .addReg(Base)
576 .addReg(PredReg);
737 .addReg(Base, getKillRegState(KillOldBase));
740 .addReg(Base, getKillRegState(KillOldBase))
750 .addReg(Base, getKillRegState(KillOldBase))
756 .addReg(Base, getKillRegState(KillOldBase))
761 .addReg(Base, getKillRegState(KillOldBase))
802 MIB.addReg(Base, getDefRegState(true))
803 .addReg(Base, getKillRegState(BaseKill));
812 MIB.addReg(Base, getKillRegState(BaseKill));
815 MIB.addImm(Pred).addReg(PredReg);
818 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second));
839 MIB.addReg(Regs[0].first, RegState::Define)
840 .addReg(Regs[1].first, RegState::Define);
842 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second))
843 .addReg(Regs[1].first, getKillRegState(Regs[1].second));
845 MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
845 MIB.addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg);
951 MIB.addReg(ImpDef, RegState::ImplicitDefine);
1318 .addReg(Base, getDefRegState(true)) // WB base register
1319 .addReg(Base, getKillRegState(BaseKill))
1320 .addImm(Pred).addReg(PredReg);
1442 .addReg(Base, getDefRegState(true)) // WB base register
1443 .addReg(Base, getKillRegState(isLd ? BaseKill : false))
1444 .addImm(Pred).addReg(PredReg)
1445 .addReg(MO.getReg(), (isLd ? getDefRegState(true) :
1453 .addReg(Base, RegState::Define)
1454 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg)
1454 .addReg(Base).addImm(Offset).addImm(Pred).addReg(PredReg)
1459 .addReg(Base, RegState::Define)
1460 .addReg(Base)
1461 .addReg(0)
1469 .addReg(Base, RegState::Define)
1470 .addReg(Base)
1484 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
1485 .addReg(Base)
1486 .addReg(0)
1493 .addReg(MO.getReg(), getKillRegState(MO.isKill()))
1494 .addReg(Base)
1543 MIB.add(Reg0Op).add(Reg1Op).addReg(BaseOp.getReg(), RegState::Define);
1546 MIB.addReg(BaseOp.getReg(), RegState::Define).add(Reg0Op).add(Reg1Op);
1548 MIB.addReg(BaseOp.getReg(), RegState::Kill)
1549 .addImm(Offset).addImm(Pred).addReg(PredReg);
1630 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill))
1631 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1632 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1639 .addReg(Reg, getKillRegState(RegDeadKill) | getUndefRegState(RegUndef))
1640 .addReg(BaseReg, getKillRegState(BaseKill)|getUndefRegState(BaseUndef));
1641 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
1699 .addReg(BaseReg, getKillRegState(BaseKill))
1700 .addImm(Pred).addReg(PredReg)
1701 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill))
1702 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill))
1707 .addReg(BaseReg, getKillRegState(BaseKill))
1708 .addImm(Pred).addReg(PredReg)
1709 .addReg(EvenReg,
1711 .addReg(OddReg,
1985 .addReg(Use.getReg(), RegState::Kill)
2330 .addReg(FirstReg, RegState::Define)
2331 .addReg(SecondReg, RegState::Define)
2332 .addReg(BaseReg);
2337 MIB.addReg(0);
2338 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
2344 .addReg(FirstReg)
2345 .addReg(SecondReg)
2346 .addReg(BaseReg);
2351 MIB.addReg(0);
2352 MIB.addImm(Offset).addImm(Pred).addReg(PredReg);
lib/Target/ARM/ARMLowOverheadLoops.cpp 367 MIB.addReg(ARM::NoRegister);
376 MIB.addReg(ARM::CPSR);
401 MIB.addReg(0);
404 MIB.addReg(ARM::CPSR);
407 MIB.addReg(0);
422 MIB.addReg(ARM::LR);
425 MIB.addReg(ARM::NoRegister);
437 MIB.addReg(ARM::CPSR);
lib/Target/ARM/MLxExpansionPass.cpp 291 .addReg(Src1Reg, getKillRegState(Src1Kill))
292 .addReg(Src2Reg, getKillRegState(Src2Kill));
295 MIB.addImm(Pred).addReg(PredReg);
298 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead));
302 MIB.addReg(TmpReg, getKillRegState(true))
303 .addReg(AccReg, getKillRegState(AccKill));
305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
305 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true));
307 MIB.addImm(Pred).addReg(PredReg);
lib/Target/ARM/Thumb1FrameLowering.cpp 91 .addReg(ARM::SP).addReg(ScratchReg, RegState::Kill)
91 .addReg(ARM::SP).addReg(ScratchReg, RegState::Kill)
303 .addReg(ARM::SP)
413 .addReg(ARM::SP, RegState::Kill)
418 .addReg(ARM::R4, RegState::Kill)
424 .addReg(ARM::R4, RegState::Kill)
429 .addReg(ARM::R4, RegState::Kill)
441 .addReg(ARM::SP)
520 .addReg(ARM::R4)
524 .addReg(FramePtr)
644 MIB.addReg(ARM::PC, RegState::Define);
722 .addReg(PopReg, RegState::Define)
723 .addReg(ARM::SP)
728 .addReg(ARM::LR, RegState::Define)
729 .addReg(PopReg, RegState::Kill)
744 .addReg(TemporaryReg, RegState::Define)
745 .addReg(PopReg, RegState::Kill)
775 .addReg(PopReg, RegState::Define);
781 .addReg(ARM::LR, RegState::Define)
782 .addReg(PopReg, RegState::Kill)
787 .addReg(PopReg, RegState::Define)
788 .addReg(TemporaryReg, RegState::Kill)
859 MIB.addReg(Reg, getKillRegState(isKill));
905 .addReg(*CopyReg, RegState::Define)
906 .addReg(*HiRegToSave, getKillRegState(isKill))
921 PushMIB.addReg(Reg, RegState::Kill);
1007 PopMIB.addReg(*CopyReg, RegState::Define);
1011 .addReg(*HiRegToRestore, RegState::Define)
1012 .addReg(*CopyReg, RegState::Kill)
1059 MIB.addReg(Reg, getDefRegState(true));
lib/Target/ARM/Thumb1InstrInfo.cpp 52 .addReg(SrcReg, getKillRegState(KillSrc))
62 .addReg(SrcReg, getKillRegState(KillSrc))
70 .addReg(SrcReg, getKillRegState(KillSrc));
73 .addReg(DestReg, getDefRegState(true));
97 .addReg(SrcReg, getKillRegState(isKill))
lib/Target/ARM/Thumb2InstrInfo.cpp 130 .addReg(SrcReg, getKillRegState(KillSrc))
150 .addReg(SrcReg, getKillRegState(isKill))
214 MIB.addReg(DestReg, RegState::ImplicitDefine);
239 .addReg(BaseReg, RegState::Kill)
240 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
257 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
262 .addReg(DestReg)
264 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags);
271 .addReg(BaseReg)
272 .addReg(DestReg, RegState::Kill)
283 .addReg(BaseReg)
284 .addReg(DestReg, RegState::Kill)
299 .addReg(BaseReg)
313 .addReg(BaseReg)
354 .addReg(BaseReg, RegState::Kill)
lib/Target/ARM/Thumb2SizeReduction.cpp 481 .addReg(Rn, RegState::Define)
482 .addReg(Rn)
484 .addReg(PredReg)
485 .addReg(Rt, IsStore ? 0 : RegState::Define);
587 MIB.addReg(MI->getOperand(0).getReg(), RegState::Define | RegState::Dead);
599 MIB.addReg(OffsetReg, getKillRegState(OffsetKill) |
lib/Target/ARM/ThumbRegisterInfo.cpp 76 .addReg(DestReg, getDefRegState(true), SubIdx)
77 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg)
95 .addReg(DestReg, getDefRegState(true), SubIdx)
160 .addReg(LdReg, RegState::Kill)
176 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
176 MIB.addReg(BaseReg).addReg(LdReg, RegState::Kill);
178 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
178 MIB.addReg(LdReg).addReg(BaseReg, RegState::Kill);
315 MIB.addReg(BaseReg, RegState::Kill);
332 MIB.addReg(BaseReg)
lib/Target/AVR/AVRExpandPseudoInsts.cpp 153 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
154 .addReg(DstLoReg, getKillRegState(DstIsKill))
155 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
158 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
159 .addReg(DstHiReg, getKillRegState(DstIsKill))
160 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
186 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
187 .addReg(DstLoReg, getKillRegState(DstIsKill))
188 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
194 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
195 .addReg(DstHiReg, getKillRegState(DstIsKill))
196 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
234 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
235 .addReg(DstLoReg, getKillRegState(SrcIsKill))
244 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
245 .addReg(DstHiReg, getKillRegState(SrcIsKill))
282 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
283 .addReg(DstLoReg, getKillRegState(SrcIsKill));
286 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
287 .addReg(DstHiReg, getKillRegState(SrcIsKill));
339 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
340 .addReg(DstLoReg, getKillRegState(SrcIsKill))
347 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
348 .addReg(DstHiReg, getKillRegState(SrcIsKill))
399 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
400 .addReg(DstLoReg, getKillRegState(DstIsKill));
406 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
407 .addReg(DstHiReg, getKillRegState(DstIsKill));
432 .addReg(DstLoReg, getKillRegState(DstIsKill))
433 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
436 .addReg(DstHiReg, getKillRegState(DstIsKill))
437 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
464 .addReg(DstLoReg, getKillRegState(DstIsKill))
465 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
471 .addReg(DstHiReg, getKillRegState(DstIsKill))
472 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
495 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
498 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
544 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead));
547 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead));
598 .addReg(CurDstLoReg, RegState::Define)
599 .addReg(SrcReg, RegState::Define);
603 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
607 .addReg(CurDstHiReg, RegState::Define)
608 .addReg(SrcReg, getKillRegState(SrcIsKill))
613 buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg);
613 buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg);
616 buildMI(MBB, MBBI, AVR::POPRd).addReg(DstLoReg);
641 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
642 .addReg(SrcReg, RegState::Define)
643 .addReg(SrcReg, RegState::Kill);
646 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
647 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
648 .addReg(SrcReg, RegState::Kill);
672 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
673 .addReg(SrcReg, RegState::Define)
674 .addReg(SrcReg, RegState::Kill);
677 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
678 .addReg(SrcReg, RegState::Define | getDeadRegState(SrcIsDead))
679 .addReg(SrcReg, RegState::Kill);
714 .addReg(CurDstLoReg, RegState::Define)
715 .addReg(SrcReg)
720 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
724 .addReg(CurDstHiReg, RegState::Define)
725 .addReg(SrcReg, getKillRegState(SrcIsKill))
730 buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg);
730 buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg);
733 buildMI(MBB, MBBI, AVR::POPRd).addReg(DstLoReg);
764 .addReg(CurDstLoReg, RegState::Define)
765 .addReg(SrcReg);
769 buildMI(MBB, MBBI, AVR::PUSHRr).addReg(TmpReg);
773 .addReg(CurDstHiReg, RegState::Define)
774 .addReg(SrcReg, getKillRegState(SrcIsKill));
778 buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg);
778 buildMI(MBB, MBBI, AVR::MOVRdRr).addReg(DstHiReg).addReg(TmpReg);
781 buildMI(MBB, MBBI, AVR::POPRd).addReg(DstLoReg);
803 .addReg(SCRATCH_REGISTER, RegState::Define)
814 .addReg(SCRATCH_REGISTER);
1002 MIBLO.addReg(SrcLoReg, getKillRegState(SrcIsKill));
1003 MIBHI.addReg(SrcHiReg, getKillRegState(SrcIsKill));
1025 .addReg(DstReg)
1026 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1029 .addReg(DstReg)
1031 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1056 .addReg(DstReg, RegState::Define)
1057 .addReg(DstReg, RegState::Kill)
1058 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1062 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1063 .addReg(DstReg, RegState::Kill)
1064 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1090 .addReg(DstReg, RegState::Define)
1091 .addReg(DstReg, RegState::Kill)
1092 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1096 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1097 .addReg(DstReg, RegState::Kill)
1098 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1126 .addReg(DstReg)
1128 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1131 .addReg(DstReg, getKillRegState(DstIsKill))
1133 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1158 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1162 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1190 .addReg(SrcHiReg, getKillRegState(SrcIsKill));
1194 .addReg(SrcLoReg, getKillRegState(SrcIsKill));
1216 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
1221 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1259 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1260 .addReg(DstLoReg)
1261 .addReg(DstLoReg, getKillRegState(DstIsKill));
1264 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1265 .addReg(DstHiReg)
1266 .addReg(DstHiReg, getKillRegState(DstIsKill));
1292 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1293 .addReg(DstHiReg, getKillRegState(DstIsKill));
1296 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1297 .addReg(DstLoReg, getKillRegState(DstIsKill));
1335 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1336 .addReg(DstHiReg, getKillRegState(DstIsKill));
1339 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1340 .addReg(DstLoReg, getKillRegState(DstIsKill));
1377 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1378 .addReg(SrcReg);
1387 .addReg(DstHiReg, RegState::Define)
1388 .addReg(SrcReg, getKillRegState(SrcIsKill));
1392 .addReg(DstHiReg, RegState::Define)
1393 .addReg(DstHiReg)
1394 .addReg(DstHiReg, RegState::Kill);
1397 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1398 .addReg(DstHiReg, RegState::Kill)
1399 .addReg(DstHiReg, RegState::Kill);
1431 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1432 .addReg(SrcReg, getKillRegState(SrcIsKill));
1436 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1437 .addReg(DstHiReg, RegState::Kill)
1438 .addReg(DstHiReg, RegState::Kill);
1460 .addReg(DstLoReg, RegState::Define | getDeadRegState(DstIsDead))
1466 .addReg(DstHiReg, RegState::Define | getDeadRegState(DstIsDead))
1484 .addReg(AVR::R0, RegState::Define)
1492 .addReg(SrcHiReg, getKillRegState(SrcIsKill))
1497 .addReg(AVR::R0, RegState::Kill)
1502 .addReg(SrcLoReg, getKillRegState(SrcIsKill))
lib/Target/AVR/AVRFrameLowering.cpp 72 .addReg(AVR::R29R28, RegState::Kill)
81 .addReg(AVR::R1R0, RegState::Kill)
88 .addReg(AVR::R0, RegState::Kill)
91 .addReg(AVR::R0, RegState::Define)
92 .addReg(AVR::R0, RegState::Kill)
93 .addReg(AVR::R0, RegState::Kill)
115 .addReg(AVR::SP)
132 .addReg(AVR::R29R28, RegState::Kill)
140 .addReg(AVR::R29R28)
173 .addReg(AVR::R0, RegState::Kill);
209 .addReg(AVR::R29R28, RegState::Kill)
216 .addReg(AVR::R29R28, RegState::Kill);
266 .addReg(Reg, getKillRegState(IsNotLiveIn))
334 .addReg(TRI.getSubReg(SrcReg, AVR::sub_hi),
337 .addReg(TRI.getSubReg(SrcReg, AVR::sub_lo),
341 .addReg(SrcReg, getKillRegState(SrcIsKill));
401 BuildMI(MBB, MI, DL, TII.get(AVR::SPREAD), AVR::R31R30).addReg(AVR::SP);
404 .addReg(AVR::R31R30, RegState::Kill)
409 .addReg(AVR::R31R30, RegState::Kill);
518 BuildMI(EntryMBB, MBBI, DL, TII.get(AVR::COPY), SPCopy).addReg(AVR::SP);
527 .addReg(SPCopy, RegState::Kill);
lib/Target/AVR/AVRISelLowering.cpp 1529 BuildMI(BB, dl, TII.get(AVR::CPIRdK)).addReg(ShiftAmtSrcReg).addImm(0);
1538 .addReg(SrcReg)
1540 .addReg(ShiftReg2)
1543 .addReg(ShiftAmtSrcReg)
1545 .addReg(ShiftAmtReg2)
1548 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
1550 ShiftMI.addReg(ShiftReg);
1553 .addReg(ShiftAmtReg)
1560 .addReg(SrcReg)
1562 .addReg(ShiftReg2)
1591 .addReg(AVR::R1)
1592 .addReg(AVR::R1);
1674 .addReg(MI.getOperand(1).getReg())
1676 .addReg(MI.getOperand(2).getReg())
lib/Target/AVR/AVRInstrInfo.cpp 53 .addReg(SrcReg, getKillRegState(KillSrc));
62 .addReg(SrcLo, getKillRegState(KillSrc));
64 .addReg(SrcHi, getKillRegState(KillSrc));
78 .addReg(SrcReg, getKillRegState(KillSrc));
155 .addReg(SrcReg, getKillRegState(isKill))
lib/Target/AVR/AVRRegisterInfo.cpp 197 .addReg(DstReg, RegState::Kill)
225 .addReg(AVR::R29R28, RegState::Kill)
232 .addReg(AVR::R0, RegState::Kill);
237 .addReg(AVR::R29R28, RegState::Kill)
lib/Target/AVR/AVRRelaxMemOperations.cpp 100 .addReg(Ptr.getReg());
104 .addReg(Ptr.getReg(), RegState::Define)
105 .addReg(Ptr.getReg())
111 .addReg(Ptr.getReg())
112 .addReg(Src.getReg(), getKillRegState(Src.isKill()));
116 .addReg(Ptr.getReg(), getKillRegState(Ptr.isKill()));
lib/Target/BPF/BPFISelLowering.cpp 576 BuildMI(BB, DL, TII.get(BPF::MOV_32_64), PromotedReg0).addReg(Reg);
578 .addReg(PromotedReg0).addImm(32);
580 .addReg(PromotedReg1).addImm(32);
610 MIB.addReg(ScratchReg,
723 BuildMI(BB, DL, TII.get(NewCC)).addReg(LHS).addReg(RHS).addMBB(Copy1MBB);
723 BuildMI(BB, DL, TII.get(NewCC)).addReg(LHS).addReg(RHS).addMBB(Copy1MBB);
729 .addReg(LHS).addImm(imm32).addMBB(Copy1MBB);
745 .addReg(MI.getOperand(5).getReg())
747 .addReg(MI.getOperand(4).getReg())
lib/Target/BPF/BPFInstrInfo.cpp 37 .addReg(SrcReg, getKillRegState(KillSrc));
40 .addReg(SrcReg, getKillRegState(KillSrc));
79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg)
79 .addReg(ScratchReg, RegState::Define).addReg(SrcReg)
82 .addReg(ScratchReg, RegState::Kill).addReg(DstReg)
82 .addReg(ScratchReg, RegState::Kill).addReg(DstReg)
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
93 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
95 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
95 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
100 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
102 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
102 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
107 .addReg(ScratchReg, RegState::Define).addReg(SrcReg).addImm(Offset);
109 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
109 .addReg(ScratchReg, RegState::Kill).addReg(DstReg).addImm(Offset);
135 .addReg(SrcReg, getKillRegState(IsKill))
140 .addReg(SrcReg, getKillRegState(IsKill))
lib/Target/BPF/BPFMIPeephole.cpp 171 .addImm(0).addReg(SubReg).addImm(BPF::sub_32);
438 .addReg(SrcReg);
lib/Target/BPF/BPFMISimplifyPatchable.cpp 129 .addReg(SrcReg, 0, BPF::sub_32);
lib/Target/BPF/BPFRegisterInfo.cpp 91 .addReg(reg)
111 .addReg(FrameReg);
113 .addReg(reg)
lib/Target/Hexagon/HexagonBitSimplify.cpp 1348 .addReg(RS.Reg, 0, RS.Sub);
1611 .addReg(MR.Reg, 0, MR.Sub);
1630 .addReg(ML.Reg, 0, ML.Sub)
1632 .addReg(MH.Reg, 0, MH.Sub)
2030 .addReg(Rs.Reg, 0, Rs.Sub)
2031 .addReg(Rt.Reg, 0, Rt.Sub);
2059 .addReg(L.Reg, 0, L.Sub);
2065 .addReg(L.Reg, 0, L.Sub)
2101 .addReg(H.Reg, 0, H.Sub)
2102 .addReg(L.Reg, 0, L.Sub);
2158 .addReg(RS.Reg, 0, RS.Sub);
2300 .addReg(SrcR, 0, SrcSR)
2361 .addReg(RR.Reg, 0, RR.Sub)
2545 .addReg(R, 0, SR);
2680 .addReg(InpDef->getOperand(1).getReg())
3073 .addReg(NewPredR)
3075 .addReg(G.Inp.Reg)
3096 MIB.addReg(UseR, 0, Op.getSubReg());
lib/Target/Hexagon/HexagonConstPropagation.cpp 2985 .addReg(R1.Reg, getRegState(Acc), R1.SubReg);
3015 .addReg(Src1.getReg(), getRegState(Src1), Src1.getSubReg())
3016 .addReg(OpR2.getReg(), getRegState(OpR2), OpR2.getSubReg())
3051 .addReg(SR.Reg, getRegState(SO), SR.SubReg);
3083 .addReg(SR.Reg, getRegState(SO), SR.SubReg);
lib/Target/Hexagon/HexagonCopyToCombine.cpp 772 .addReg(LoReg, LoRegKillFlag);
780 .addReg(LoReg, LoRegKillFlag);
787 .addReg(LoReg, LoRegKillFlag);
795 .addReg(LoReg, LoRegKillFlag);
802 .addReg(LoReg, LoRegKillFlag);
818 .addReg(HiReg, HiRegKillFlag)
826 .addReg(HiReg, HiRegKillFlag)
834 .addReg(HiOperand.getReg(), HiRegKillFlag)
841 .addReg(HiOperand.getReg(), HiRegKillFlag)
850 .addReg(HiReg, HiRegKillFlag)
878 .addReg(HiReg, HiRegKillFlag)
879 .addReg(LoReg, LoRegKillFlag);
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 728 MIB.addReg(PredR);
744 .addReg(PredR)
803 .addReg(PredR)
804 .addReg(TR, 0, TSR)
805 .addReg(FR, 0, FSR);
915 .addReg(FP.PredR)
925 MIB.addReg(FP.PredR);
1002 .addReg(UseR, 0, UseSR);
lib/Target/Hexagon/HexagonExpandCondsets.cpp 520 MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub);
646 .addReg(DstR, DstState, DstSR)
647 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
648 .addReg(SrcOp.getReg(), SrcState, SrcOp.getSubReg());
651 .addReg(DstR, DstState, DstSR)
652 .addReg(PredOp.getReg(), PredState, PredOp.getSubReg())
699 MachineInstrBuilder(MF, MI).addReg(RT.Reg, S, RT.Sub);
884 MB.addReg(DefOp.getReg(), getRegState(DefOp), DefOp.getSubReg());
885 MB.addReg(PredOp.getReg(), PredOp.isUndef() ? RegState::Undef : 0,
lib/Target/Hexagon/HexagonFrameLowering.cpp 629 .addReg(SP)
641 .addReg(SP)
660 .addReg(SP)
673 .addReg(Hexagon::R30);
675 .addReg(SP)
676 .addReg(Hexagon::R28);
721 .addReg(Hexagon::R30);
727 .addReg(Hexagon::R30);
756 .addReg(SP)
763 .addReg(SP)
768 .addReg(SP)
1582 .addReg(TmpR, RegState::Kill);
1608 .addReg(SrcR, getKillRegState(IsKill));
1614 .addReg(TmpR, RegState::Kill)
1646 .addReg(TmpR, RegState::Kill);
1677 .addReg(SrcR, getKillRegState(IsKill))
1678 .addReg(TmpR0, RegState::Kill);
1716 .addReg(TmpR1, RegState::Kill)
1717 .addReg(TmpR0, RegState::Kill);
1766 .addReg(SrcLo, getKillRegState(IsKill))
1777 .addReg(SrcHi, getKillRegState(IsKill))
1848 .addReg(SrcR, getKillRegState(IsKill))
2315 .addReg(FoundR, getKillRegState(&MI == &EI));
2357 .addReg(SP)
2358 .addReg(Rs);
2362 .addReg(SP)
2363 .addReg(Rs);
2368 .addReg(Rd)
2372 .addReg(SP)
2378 .addReg(Rd);
2383 .addReg(Rd)
lib/Target/Hexagon/HexagonGenInsert.cpp 1434 .addReg(IF.SrcR)
1435 .addReg(IF.InsR, 0, InsS)
lib/Target/Hexagon/HexagonGenMux.cpp 338 .addReg(MX.PredR)
lib/Target/Hexagon/HexagonGenPredicate.cpp 275 .addReg(Reg.R, 0, Reg.S);
428 MIB.addReg(Pred.R, 0, Pred.S);
437 .addReg(NewPR.R, 0, NewPR.S);
lib/Target/Hexagon/HexagonHardwareLoops.cpp 918 SubIB.addReg(End->getReg(), 0, End->getSubReg())
919 .addReg(Start->getReg(), 0, Start->getSubReg());
922 .addReg(Start->getReg(), 0, Start->getSubReg());
937 SubIB.addReg(End->getReg(), 0, End->getSubReg())
956 .addReg(DistR, 0, DistSR)
977 .addReg(AdjR, 0, AdjSR)
1249 .addReg(TripCount->getReg(), 0, TripCount->getSubReg());
1252 .addReg(CountReg);
1264 .addMBB(LoopStart).addReg(CountReg);
lib/Target/Hexagon/HexagonInstrInfo.cpp 635 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
636 addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
638 BuildMI(&MBB, DL, get(BccOpc)).addReg(Cond[1].getReg(), Flags1).
646 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
670 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
713 .addReg(LoopCount)
745 .addReg(LoopCount)
796 .addReg(SrcReg, KillFlag);
801 .addReg(SrcReg, KillFlag);
807 .addReg(SrcReg).addReg(SrcReg, KillFlag);
807 .addReg(SrcReg).addReg(SrcReg, KillFlag);
813 .addReg(SrcReg, KillFlag);
819 .addReg(SrcReg, KillFlag);
825 .addReg(SrcReg, KillFlag);
831 .addReg(SrcReg, KillFlag);
837 .addReg(SrcReg, KillFlag);
843 .addReg(SrcReg, KillFlag);
848 addReg(SrcReg, KillFlag);
855 .addReg(HiSrc, KillFlag)
856 .addReg(LoSrc, KillFlag);
861 .addReg(SrcReg)
862 .addReg(SrcReg, KillFlag);
903 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
907 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
911 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
915 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
919 .addReg(SrcReg, KillFlag).addMemOperand(MMO);
931 .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
943 .addReg(SrcReg, KillFlag).addMemOperand(MMOA);
1038 MIB.addReg(CSx, RegState::Implicit);
1057 .addReg(HRI.getFrameRegister())
1066 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_hi), Kill)
1067 .addReg(HRI.getSubReg(SrcReg, Hexagon::vsub_lo), Kill);
1101 .addReg(SrcSubLo)
1108 .addReg(SrcSubHi)
1137 .addReg(Reg, RegState::Undef)
1138 .addReg(Reg, RegState::Undef);
1145 .addReg(Reg, RegState::Undef)
1146 .addReg(Reg, RegState::Undef);
1152 .addReg(Hexagon::V0, RegState::Undef)
1153 .addReg(Hexagon::V0, RegState::Undef);
1159 .addReg(Hexagon::V0, RegState::Undef)
1160 .addReg(Hexagon::V0, RegState::Undef);
1167 .addReg(Vd, RegState::Undef)
1168 .addReg(Vd, RegState::Undef);
1183 .addReg(Src1SubHi)
1184 .addReg(Src2SubHi);
1187 .addReg(Src1SubLo)
1188 .addReg(Src2SubLo);
1210 .addReg(Src1SubHi)
1211 .addReg(Src2SubHi)
1212 .addReg(Src3SubHi);
1215 .addReg(Src1SubLo)
1216 .addReg(Src2SubLo)
1217 .addReg(Src3SubLo);
1242 .addReg(Pu, (Rd == Rt) ? K1 : 0)
1243 .addReg(Rs, K2);
1246 .addReg(Pu, K1)
1247 .addReg(Rt, K3);
1268 .addReg(PReg, S)
1271 T.addReg(Op0.getReg(), RegState::Implicit);
1277 .addReg(PReg, PState)
1280 T.addReg(Op0.getReg(), RegState::Implicit);
1304 .addReg(PReg, S)
1305 .addReg(SrcHi)
1306 .addReg(SrcLo);
1308 T.addReg(Op0.getReg(), RegState::Implicit);
1316 .addReg(PReg, PState)
1317 .addReg(SrcHi)
1318 .addReg(SrcLo);
1320 T.addReg(Op0.getReg(), RegState::Implicit);
1449 .addReg(Hexagon::VTMP);
1461 .addReg(Hexagon::VTMP);
1473 .addReg(Hexagon::VTMP);
1486 .addReg(Hexagon::VTMP);
1499 .addReg(Hexagon::VTMP);
1512 .addReg(Hexagon::VTMP);
1593 T.addReg(PredReg, PredRegFlags);
lib/Target/Hexagon/HexagonNewValueJump.cpp 693 .addReg(cmpReg1, getKillRegState(MO1IsKill))
694 .addReg(cmpOp2, getKillRegState(MO2IsKill))
699 .addReg(cmpReg1, getKillRegState(MO1IsKill))
lib/Target/Hexagon/HexagonPeephole.cpp 282 .addReg(POrig)
lib/Target/Hexagon/HexagonRegisterInfo.cpp 223 .addReg(BP)
lib/Target/Hexagon/HexagonSplitDouble.cpp 653 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
656 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
662 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
664 .addReg(P.first);
666 .addReg(AdrOp.getReg(), RSA & ~RegState::Kill, AdrOp.getSubReg())
668 .addReg(P.second);
680 .addReg(AdrOp.getReg(), RSA)
745 .addReg(Op1.getReg(), getRegState(Op1), Op1.getSubReg());
753 .addReg(Op2.getReg(), getRegState(Op2), Op2.getSubReg());
771 .addReg(Op1.getReg(), RS & ~RegState::Kill, Op1.getSubReg());
773 .addReg(Op1.getReg(), RS, Op1.getSubReg())
811 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
813 .addReg(Op1.getReg(), RS, HiSR);
836 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
839 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
842 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
848 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR)
853 .addReg(TmpR)
854 .addReg(Op1.getReg(), RS, HiSR)
859 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR)
863 .addReg(TmpR)
864 .addReg(Op1.getReg(), RS, HiSR)
870 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR));
876 .addReg(Op1.getReg(), RS, HiSR)
882 .addReg(Op1.getReg(), RS & ~RegState::Kill, LoSR);
885 .addReg(Op1.getReg(), RS & ~RegState::Kill, HiSR);
888 .addReg(Op1.getReg(), RS & ~RegState::Kill, (Left ? LoSR : HiSR))
893 .addReg(Op1.getReg(), RS, HiSR)
946 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
947 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR);
949 .addReg(Op1.getReg(), RS1, HiSR)
950 .addReg(Op2.getReg(), RS2, HiSR);
953 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR)
954 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
958 .addReg(Op2.getReg(), RS2 & ~RegState::Kill, LoSR)
963 .addReg(Op1.getReg(), RS1, HiSR)
964 .addReg(TmpR1);
966 .addReg(TmpR2)
967 .addReg(Op2.getReg(), RS2, HiSR)
975 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
977 .addReg(Op1.getReg(), RS1, HiSR)
978 .addReg(Op2.getReg(), RS2, LoSR);
986 .addReg(Op1.getReg(), RS1 & ~RegState::Kill, LoSR);
988 .addReg(Op1.getReg(), RS1, HiSR)
989 .addReg(Op2.getReg(), RS2, LoSR)
1118 .addReg(Pr.first)
1120 .addReg(Pr.second)
lib/Target/Hexagon/HexagonStoreWidening.cpp 435 .addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg())
458 .addReg(MR.getReg(), getKillRegState(MR.isKill()), MR.getSubReg())
460 .addReg(VReg, RegState::Kill);
lib/Target/Hexagon/HexagonVExtract.cpp 83 .addReg(BaseR)
94 .addReg(BaseR)
95 .addReg(IdxR)
136 .addReg(VecR);
lib/Target/Lanai/LanaiFrameLowering.cpp 79 .addReg(Src)
114 .addReg(Lanai::FP)
115 .addReg(Lanai::SP)
123 .addReg(Lanai::SP)
131 .addReg(Lanai::SP)
187 .addReg(Lanai::FP)
192 .addReg(Lanai::FP)
lib/Target/Lanai/LanaiInstrInfo.cpp 45 .addReg(SourceRegister, getKillRegState(KillSource))
63 .addReg(SourceRegister, getKillRegState(IsKill))
lib/Target/Lanai/LanaiMemAluCombiner.cpp 260 InstrBuilder.addReg(Dest.getReg(), getDefRegState(true));
261 InstrBuilder.addReg(Base.getReg(), getKillRegState(true));
265 InstrBuilder.addReg(AluOffset.getReg());
lib/Target/Lanai/LanaiRegisterInfo.cpp 191 .addReg(Reg)
204 .addReg(FrameReg)
205 .addReg(Reg)
240 .addReg(FrameReg)
lib/Target/MSP430/MSP430FrameLowering.cpp 67 .addReg(MSP430::FP, RegState::Kill);
71 .addReg(MSP430::SP);
99 .addReg(MSP430::SP).addImm(NumBytes);
157 TII.get(MSP430::MOV16rr), MSP430::SP).addReg(MSP430::FP);
162 .addReg(MSP430::SP).addImm(CSSize);
171 .addReg(MSP430::SP).addImm(NumBytes);
200 .addReg(Reg, RegState::Kill);
249 .addReg(MSP430::SP)
258 .addReg(MSP430::SP)
277 .addReg(MSP430::SP)
lib/Target/MSP430/MSP430ISelLowering.cpp 1451 .addReg(MSP430::SR).addImm(1);
1457 .addReg(SrcReg);
1497 .addReg(ShiftAmtSrcReg).addImm(0);
1508 .addReg(SrcReg).addMBB(BB)
1509 .addReg(ShiftReg2).addMBB(LoopBB);
1511 .addReg(ShiftAmtSrcReg).addMBB(BB)
1512 .addReg(ShiftAmtReg2).addMBB(LoopBB);
1515 .addReg(MSP430::SR).addImm(1);
1518 .addReg(ShiftReg)
1519 .addReg(ShiftReg);
1522 .addReg(ShiftReg);
1524 .addReg(ShiftAmtReg).addImm(1);
1532 .addReg(SrcReg).addMBB(BB)
1533 .addReg(ShiftReg2).addMBB(LoopBB);
1601 .addReg(MI.getOperand(2).getReg())
1603 .addReg(MI.getOperand(1).getReg())
lib/Target/MSP430/MSP430InstrInfo.cpp 54 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
58 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
80 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx)
84 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx)
103 .addReg(SrcReg, getKillRegState(KillSrc));
lib/Target/MSP430/MSP430RegisterInfo.cpp 145 .addReg(DstReg).addImm(-Offset);
148 .addReg(DstReg).addImm(Offset);
lib/Target/Mips/Mips16FrameLowering.cpp 88 .addReg(Mips::SP).setMIFlag(MachineInstr::FrameSetup);
105 .addReg(Mips::S0);
lib/Target/Mips/Mips16ISelDAGToDAG.cpp 88 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
90 .addReg(V1)
91 .addReg(V2);
lib/Target/Mips/Mips16ISelLowering.cpp 547 .addReg(MI.getOperand(3).getReg())
564 .addReg(MI.getOperand(1).getReg())
566 .addReg(MI.getOperand(2).getReg())
610 .addReg(MI.getOperand(3).getReg())
611 .addReg(MI.getOperand(4).getReg());
628 .addReg(MI.getOperand(1).getReg())
630 .addReg(MI.getOperand(2).getReg())
676 .addReg(MI.getOperand(3).getReg())
694 .addReg(MI.getOperand(1).getReg())
696 .addReg(MI.getOperand(2).getReg())
715 .addReg(regX)
716 .addReg(regY);
739 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(CmpOpc)).addReg(regX).addImm(imm);
765 .addReg(regX)
766 .addReg(regY);
768 .addReg(Mips::T8);
784 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(SltOpc)).addReg(regX).addImm(Imm);
786 .addReg(Mips::T8);
lib/Target/Mips/Mips16InstrInfo.cpp 93 MIB.addReg(DestReg, RegState::Define);
96 MIB.addReg(SrcReg, getKillRegState(KillSrc));
123 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)).
202 MIB.addReg(Reg, Flags);
228 MIB.addReg(Mips::S2);
271 MIB.addReg(Mips::S2, RegState::Define);
294 MIB2.addReg(Mips::SP, RegState::Kill);
296 MIB3.addReg(Reg1);
297 MIB3.addReg(Reg2, RegState::Kill);
300 MIB4.addReg(Reg1, RegState::Kill);
421 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
422 .addReg(Reg);
425 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
426 .addReg(Reg, RegState::Kill);
lib/Target/Mips/MipsBranchExpansion.cpp 350 MIB.addReg(MO.getReg());
387 BuildMI(*MBB, Pos, DL, TII->get(JumpOp)).addReg(ATReg);
457 .addReg(Mips::SP)
460 .addReg(Mips::RA)
461 .addReg(Mips::SP)
488 .addReg(Mips::AT)
503 .addReg(Mips::RA)
504 .addReg(Mips::AT);
506 .addReg(Mips::SP)
518 .addReg(Mips::SP)
526 .addReg(Mips::SP)
580 .addReg(Mips::SP_64)
583 .addReg(Mips::RA_64)
584 .addReg(Mips::SP_64)
588 .addReg(Mips::ZERO_64)
592 .addReg(Mips::AT_64)
599 .addReg(Mips::AT_64)
614 .addReg(Mips::RA_64)
615 .addReg(Mips::AT_64);
617 .addReg(Mips::SP_64)
625 .addReg(Mips::SP_64)
629 .addReg(Mips::SP_64)
681 .addReg(Mips::AT_64)
684 .addReg(Mips::AT_64)
688 .addReg(Mips::AT_64)
691 .addReg(Mips::AT_64)
695 .addReg(Mips::AT_64)
703 .addReg(Mips::AT)
727 .addReg(Mips::V0)
lib/Target/Mips/MipsConstantIslandPass.cpp 1619 .addReg(MI->getOperand(0).getReg())
lib/Target/Mips/MipsExpandPseudo.cpp 145 BuildMI(loop1MBB, DL, TII->get(LL), Scratch).addReg(Ptr).addImm(0);
147 .addReg(Scratch)
148 .addReg(Mask);
150 .addReg(Scratch2).addReg(ShiftCmpVal).addMBB(sinkMBB);
150 .addReg(Scratch2).addReg(ShiftCmpVal).addMBB(sinkMBB);
158 .addReg(Scratch, RegState::Kill)
159 .addReg(Mask2);
161 .addReg(Scratch, RegState::Kill)
162 .addReg(ShiftNewVal);
164 .addReg(Scratch, RegState::Kill)
165 .addReg(Ptr)
168 .addReg(Scratch, RegState::Kill)
169 .addReg(ZERO)
176 .addReg(Scratch2)
177 .addReg(ShiftAmnt);
179 BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest);
184 .addReg(Dest, RegState::Kill)
187 .addReg(Dest, RegState::Kill)
278 BuildMI(loop1MBB, DL, TII->get(LL), Dest).addReg(Ptr).addImm(0);
280 .addReg(Dest, RegState::Kill).addReg(OldVal).addMBB(exitMBB);
280 .addReg(Dest, RegState::Kill).addReg(OldVal).addMBB(exitMBB);
286 BuildMI(loop2MBB, DL, TII->get(MOVE), Scratch).addReg(NewVal).addReg(ZERO);
286 BuildMI(loop2MBB, DL, TII->get(MOVE), Scratch).addReg(NewVal).addReg(ZERO);
288 .addReg(Scratch).addReg(Ptr).addImm(0);
288 .addReg(Scratch).addReg(Ptr).addImm(0);
290 .addReg(Scratch, RegState::Kill).addReg(ZERO).addMBB(loop1MBB);
290 .addReg(Scratch, RegState::Kill).addReg(ZERO).addMBB(loop1MBB);
404 BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
410 .addReg(OldVal)
411 .addReg(Incr);
413 .addReg(Mips::ZERO)
414 .addReg(BinOpRes);
416 .addReg(BinOpRes)
417 .addReg(Mask);
422 .addReg(OldVal)
423 .addReg(Incr);
425 .addReg(BinOpRes)
426 .addReg(Mask);
430 .addReg(Incr)
431 .addReg(Mask);
439 .addReg(OldVal).addReg(Mask2);
439 .addReg(OldVal).addReg(Mask2);
441 .addReg(StoreVal).addReg(BinOpRes);
441 .addReg(StoreVal).addReg(BinOpRes);
443 .addReg(StoreVal).addReg(Ptr).addImm(0);
443 .addReg(StoreVal).addReg(Ptr).addImm(0);
445 .addReg(StoreVal).addReg(Mips::ZERO).addMBB(loopMBB);
445 .addReg(StoreVal).addReg(Mips::ZERO).addMBB(loopMBB);
455 .addReg(OldVal).addReg(Mask);
455 .addReg(OldVal).addReg(Mask);
457 .addReg(Dest).addReg(ShiftAmnt);
457 .addReg(Dest).addReg(ShiftAmnt);
460 BuildMI(sinkMBB, DL, TII->get(SEOp), Dest).addReg(Dest);
464 .addReg(Dest, RegState::Kill)
467 .addReg(Dest, RegState::Kill)
592 BuildMI(loopMBB, DL, TII->get(LL), OldVal).addReg(Ptr).addImm(0);
596 BuildMI(loopMBB, DL, TII->get(Opcode), Scratch).addReg(OldVal).addReg(Incr);
596 BuildMI(loopMBB, DL, TII->get(Opcode), Scratch).addReg(OldVal).addReg(Incr);
600 BuildMI(loopMBB, DL, TII->get(AND), Scratch).addReg(OldVal).addReg(Incr);
600 BuildMI(loopMBB, DL, TII->get(AND), Scratch).addReg(OldVal).addReg(Incr);
601 BuildMI(loopMBB, DL, TII->get(NOR), Scratch).addReg(ZERO).addReg(Scratch);
601 BuildMI(loopMBB, DL, TII->get(NOR), Scratch).addReg(ZERO).addReg(Scratch);
604 BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
604 BuildMI(loopMBB, DL, TII->get(OR), Scratch).addReg(Incr).addReg(ZERO);
607 BuildMI(loopMBB, DL, TII->get(SC), Scratch).addReg(Scratch).addReg(Ptr).addImm(0);
607 BuildMI(loopMBB, DL, TII->get(SC), Scratch).addReg(Scratch).addReg(Ptr).addImm(0);
608 BuildMI(loopMBB, DL, TII->get(BEQ)).addReg(Scratch).addReg(ZERO).addMBB(loopMBB);
608 BuildMI(loopMBB, DL, TII->get(BEQ)).addReg(Scratch).addReg(ZERO).addMBB(loopMBB);
lib/Target/Mips/MipsFastISel.cpp 221 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
221 return emitInst(Opc).addReg(SrcReg).addReg(MemReg).addImm(MemOffset);
226 return emitInst(Opc, DstReg).addReg(MemReg).addImm(MemOffset);
333 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
333 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg);
370 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm);
373 emitInst(Mips::ORi, ResultReg).addReg(Mips::ZERO).addImm(Imm);
382 emitInst(Mips::ORi, ResultReg).addReg(TmpReg).addImm(Lo);
397 emitInst(Mips::MTC1, DestReg).addReg(TempReg);
405 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
405 emitInst(Mips::BuildPairF64, DestReg).addReg(TempReg2).addReg(TempReg1);
423 .addReg(MFI->getGlobalBaseReg())
429 .addReg(DestReg)
440 .addReg(MFI->getGlobalBaseReg())
654 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
654 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
655 emitInst(Mips::SLTiu, ResultReg).addReg(TempReg).addImm(1);
660 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
660 emitInst(Mips::XOR, TempReg).addReg(LeftReg).addReg(RightReg);
661 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
661 emitInst(Mips::SLTu, ResultReg).addReg(Mips::ZERO).addReg(TempReg);
665 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
665 emitInst(Mips::SLTu, ResultReg).addReg(RightReg).addReg(LeftReg);
668 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
668 emitInst(Mips::SLTu, ResultReg).addReg(LeftReg).addReg(RightReg);
672 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
672 emitInst(Mips::SLTu, TempReg).addReg(LeftReg).addReg(RightReg);
673 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
678 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
678 emitInst(Mips::SLTu, TempReg).addReg(RightReg).addReg(LeftReg);
679 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
683 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
683 emitInst(Mips::SLT, ResultReg).addReg(RightReg).addReg(LeftReg);
686 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
686 emitInst(Mips::SLT, ResultReg).addReg(LeftReg).addReg(RightReg);
690 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
690 emitInst(Mips::SLT, TempReg).addReg(LeftReg).addReg(RightReg);
691 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
696 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
696 emitInst(Mips::SLT, TempReg).addReg(RightReg).addReg(LeftReg);
697 emitInst(Mips::XORi, ResultReg).addReg(TempReg).addImm(1);
743 emitInst(Mips::ADDiu, RegWithZero).addReg(Mips::ZERO).addImm(0);
744 emitInst(Mips::ADDiu, RegWithOne).addReg(Mips::ZERO).addImm(1);
745 emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg)
745 emitInst(Opc).addReg(Mips::FCC0, RegState::Define).addReg(LeftReg)
746 .addReg(RightReg);
748 .addReg(RegWithOne)
749 .addReg(Mips::FCC0)
750 .addReg(RegWithZero);
856 .addReg(SrcReg)
980 .addReg(ZExtCondReg)
1013 emitInst(Mips::CVT_D32_S, DestReg).addReg(SrcReg);
1067 emitInst(TargetOpcode::COPY, TempReg).addReg(Src2Reg);
1069 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1069 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1069 .addReg(Src1Reg).addReg(ZExtCondReg).addReg(TempReg);
1093 emitInst(Mips::CVT_S_D32, DestReg).addReg(SrcReg);
1132 emitInst(Opc, TempReg).addReg(SrcReg);
1133 emitInst(Mips::MFC1, DestReg).addReg(TempReg);
1234 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
1305 ResultReg).addReg(RVLocs[0].getLocReg());
1475 .addReg(DstReg, getKillRegState(true));
1560 emitInst(TargetOpcode::COPY, Mips::T9).addReg(DestAddress);
1563 Mips::RA).addReg(Mips::T9);
1567 MIB.addReg(Reg, RegState::Implicit);
1608 emitInst(Mips::WSBH, DestReg).addReg(SrcReg);
1618 emitInst(Mips::SLL, TempReg[0]).addReg(SrcReg).addImm(8);
1619 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(8);
1620 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1620 emitInst(Mips::OR, TempReg[2]).addReg(TempReg[0]).addReg(TempReg[1]);
1621 emitInst(Mips::ANDi, DestReg).addReg(TempReg[2]).addImm(0xFFFF);
1628 emitInst(Mips::WSBH, TempReg).addReg(SrcReg);
1629 emitInst(Mips::ROTR, DestReg).addReg(TempReg).addImm(16);
1640 emitInst(Mips::SRL, TempReg[0]).addReg(SrcReg).addImm(8);
1641 emitInst(Mips::SRL, TempReg[1]).addReg(SrcReg).addImm(24);
1642 emitInst(Mips::ANDi, TempReg[2]).addReg(TempReg[0]).addImm(0xFF00);
1643 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1643 emitInst(Mips::OR, TempReg[3]).addReg(TempReg[1]).addReg(TempReg[2]);
1645 emitInst(Mips::ANDi, TempReg[4]).addReg(SrcReg).addImm(0xFF00);
1646 emitInst(Mips::SLL, TempReg[5]).addReg(TempReg[4]).addImm(8);
1648 emitInst(Mips::SLL, TempReg[6]).addReg(SrcReg).addImm(24);
1649 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1649 emitInst(Mips::OR, TempReg[7]).addReg(TempReg[3]).addReg(TempReg[5]);
1650 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1650 emitInst(Mips::OR, DestReg).addReg(TempReg[6]).addReg(TempReg[7]);
1769 TII.get(TargetOpcode::COPY), DestReg).addReg(SrcReg);
1776 MIB.addReg(RetRegs[i], RegState::Implicit);
1846 emitInst(Mips::SLL, TempReg).addReg(SrcReg).addImm(ShiftAmt);
1847 emitInst(Mips::SRA, DestReg).addReg(TempReg).addImm(ShiftAmt);
1857 emitInst(Mips::SEB, DestReg).addReg(SrcReg);
1860 emitInst(Mips::SEH, DestReg).addReg(SrcReg);
1893 emitInst(Mips::ANDi, DestReg).addReg(SrcReg).addImm(Imm);
1946 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1946 emitInst(DivOpc).addReg(Src0Reg).addReg(Src1Reg);
1947 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
1947 emitInst(Mips::TEQ).addReg(Src1Reg).addReg(Mips::ZERO).addImm(7);
2009 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
2032 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
2032 emitInst(Opcode, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
2119 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2119 emitInst(Mips::ADDu, DestReg).addReg(TempReg).addReg(Addr.getReg());
2141 .addReg(Op0, getKillRegState(Op0IsKill))
2142 .addReg(Op1, getKillRegState(Op1IsKill))
2143 .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
2144 .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
lib/Target/Mips/MipsISelLowering.cpp 1276 .addReg(Divisor.getReg(), getKillRegState(Divisor.isKill()))
1277 .addReg(Mips::ZERO)
1523 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr);
1524 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1527 .addReg(OldVal, RegState::Define | RegState::EarlyClobber)
1528 .addReg(PtrCopy)
1529 .addReg(IncrCopy)
1530 .addReg(Scratch, RegState::Define | RegState::EarlyClobber |
1545 BuildMI(BB, DL, TII->get(Mips::SEB), DstReg).addReg(SrcReg);
1550 BuildMI(BB, DL, TII->get(Mips::SEH), DstReg).addReg(SrcReg);
1562 BuildMI(BB, DL, TII->get(Mips::SLL), ScrReg).addReg(SrcReg).addImm(ShiftImm);
1563 BuildMI(BB, DL, TII->get(Mips::SRA), DstReg).addReg(ScrReg).addImm(ShiftImm);
1671 .addReg(ABI.GetNullPtr()).addImm(-4);
1673 .addReg(Ptr).addReg(MaskLSB2);
1673 .addReg(Ptr).addReg(MaskLSB2);
1675 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1677 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1681 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1682 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1685 .addReg(Mips::ZERO).addImm(MaskImm);
1687 .addReg(MaskUpper).addReg(ShiftAmt);
1687 .addReg(MaskUpper).addReg(ShiftAmt);
1688 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1688 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1689 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1689 BuildMI(BB, DL, TII->get(Mips::SLLV), Incr2).addReg(Incr).addReg(ShiftAmt);
1697 .addReg(Dest, RegState::Define | RegState::EarlyClobber)
1698 .addReg(AlignedAddr)
1699 .addReg(Incr2)
1700 .addReg(Mask)
1701 .addReg(Mask2)
1702 .addReg(ShiftAmt)
1703 .addReg(Scratch, RegState::EarlyClobber | RegState::Define |
1705 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define |
1707 .addReg(Scratch3, RegState::EarlyClobber | RegState::Define |
1756 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1757 BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal);
1758 BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal);
1765 .addReg(Dest, RegState::Define | RegState::EarlyClobber)
1766 .addReg(PtrCopy, RegState::Kill)
1767 .addReg(OldValCopy, RegState::Kill)
1768 .addReg(NewValCopy, RegState::Kill)
1769 .addReg(Scratch, RegState::EarlyClobber | RegState::Define |
1852 .addReg(ABI.GetNullPtr()).addImm(-4);
1854 .addReg(Ptr).addReg(MaskLSB2);
1854 .addReg(Ptr).addReg(MaskLSB2);
1856 .addReg(Ptr, 0, ArePtrs64bit ? Mips::sub_32 : 0).addImm(3);
1858 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3);
1862 .addReg(PtrLSB2).addImm((Size == 1) ? 3 : 2);
1863 BuildMI(BB, DL, TII->get(Mips::SLL), ShiftAmt).addReg(Off).addImm(3);
1866 .addReg(Mips::ZERO).addImm(MaskImm);
1868 .addReg(MaskUpper).addReg(ShiftAmt);
1868 .addReg(MaskUpper).addReg(ShiftAmt);
1869 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1869 BuildMI(BB, DL, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask);
1871 .addReg(CmpVal).addImm(MaskImm);
1873 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1873 .addReg(MaskedCmpVal).addReg(ShiftAmt);
1875 .addReg(NewVal).addImm(MaskImm);
1877 .addReg(MaskedNewVal).addReg(ShiftAmt);
1877 .addReg(MaskedNewVal).addReg(ShiftAmt);
1884 .addReg(Dest, RegState::Define | RegState::EarlyClobber)
1885 .addReg(AlignedAddr)
1886 .addReg(Mask)
1887 .addReg(ShiftedCmpVal)
1888 .addReg(Mask2)
1889 .addReg(ShiftedNewVal)
1890 .addReg(ShiftAmt)
1891 .addReg(Scratch, RegState::EarlyClobber | RegState::Define |
1893 .addReg(Scratch2, RegState::EarlyClobber | RegState::Define |
4458 .addReg(MI.getOperand(1).getReg())
4463 .addReg(MI.getOperand(1).getReg())
4464 .addReg(Mips::ZERO)
4482 .addReg(MI.getOperand(2).getReg())
4484 .addReg(MI.getOperand(3).getReg())
4533 .addReg(MI.getOperand(2).getReg())
4534 .addReg(Mips::ZERO)
4552 .addReg(MI.getOperand(3).getReg())
4554 .addReg(MI.getOperand(5).getReg())
4557 .addReg(MI.getOperand(4).getReg())
4559 .addReg(MI.getOperand(6).getReg())
lib/Target/Mips/MipsInstructionSelector.cpp 556 .addReg(MF.getInfo<MipsFunctionInfo>()
580 .addReg(LWGOTDef)
612 .addReg(MF.getInfo<MipsFunctionInfo>()
lib/Target/Mips/MipsMachineFunction.cpp 90 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
91 .addReg(Mips::T9_64);
92 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
104 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
119 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
119 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
120 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
147 .addReg(Mips::V0).addReg(Mips::T9);
147 .addReg(Mips::V0).addReg(Mips::T9);
lib/Target/Mips/MipsOptimizePICCall.cpp 157 .addReg(SrcReg);
lib/Target/Mips/MipsSEFrameLowering.cpp 179 .addReg(VR, RegState::Kill);
193 .addReg(Src, getKillRegState(I->getOperand(0).isKill()));
216 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
218 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
238 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
240 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
272 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
274 .addReg(VR0, RegState::Kill);
275 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
277 .addReg(VR1, RegState::Kill);
529 BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO)
529 BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO)
546 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);
547 BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR);
547 BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR);
553 .addReg(SP)
554 .addReg(ZERO);
599 .addReg(Mips::COP013)
604 .addReg(Mips::K0)
613 .addReg(Mips::COP014)
624 .addReg(Mips::COP012)
658 .addReg(SrcReg)
661 .addReg(Mips::K1)
666 .addReg(Mips::ZERO)
669 .addReg(Mips::K1)
675 .addReg(Mips::ZERO)
678 .addReg(Mips::K1)
683 .addReg(Mips::K1)
715 BuildMI(MBB, I, DL, TII.get(MOVE), SP).addReg(FP).addReg(ZERO);
715 BuildMI(MBB, I, DL, TII.get(MOVE), SP).addReg(FP).addReg(ZERO);
765 .addReg(Mips::K1)
773 .addReg(Mips::K1)
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 59 MIB.addReg(Mips::DSPPos, Flag);
62 MIB.addReg(Mips::DSPSCount, Flag);
65 MIB.addReg(Mips::DSPCarry, Flag);
68 MIB.addReg(Mips::DSPOutFlag, Flag);
71 MIB.addReg(Mips::DSPCCond, Flag);
74 MIB.addReg(Mips::DSPEFI, Flag);
lib/Target/Mips/MipsSEISelLowering.cpp 3069 .addReg(Mips::ZERO).addImm(0);
3075 .addReg(Mips::ZERO).addImm(1);
3080 .addReg(VR2)
3082 .addReg(VR1)
3132 .addReg(MI.getOperand(1).getReg())
3138 .addReg(Mips::ZERO).addImm(0);
3144 .addReg(Mips::ZERO).addImm(1);
3149 .addReg(RD1)
3151 .addReg(RD2)
3185 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3188 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3194 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3195 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3225 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3229 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3230 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
3259 .addReg(Fs)
3262 .addReg(Wd_in)
3264 .addReg(Wt)
3293 .addReg(Fs)
3296 .addReg(Wd_in)
3298 .addReg(Wt)
3378 .addReg(SrcValReg)
3387 .addReg(LaneReg)
3395 .addReg(SrcVecReg)
3396 .addReg(SrcVecReg)
3397 .addReg(LaneReg, 0, SubRegIdx);
3403 .addReg(WdTmp1)
3405 .addReg(SrcValReg)
3410 .addReg(WdTmp1)
3411 .addReg(SrcValReg)
3421 .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
3422 .addReg(LaneReg);
3424 .addReg(WdTmp2)
3425 .addReg(WdTmp2)
3426 .addReg(LaneTmp2, 0, SubRegIdx);
3456 .addReg(Wt1)
3457 .addReg(Fs)
3459 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3487 .addReg(Wt1)
3488 .addReg(Fs)
3490 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
3529 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3534 .addReg(Rs)
3539 .addReg(Rs)
3540 .addReg(Rt)
3589 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32);
3593 BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
3677 BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs);
3678 BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp);
3683 BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
3687 .addReg(Wtemp)
3688 .addReg(Rtemp2)
3691 .addReg(Wtemp2)
3692 .addReg(Rtemp2)
3700 .addReg(WPHI)
3701 .addReg(WPHI);
3705 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI);
3705 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI);
3782 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
3785 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp);
3793 BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0);
3794 BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp);
3799 .addReg(WPHI)
3802 .addReg(FPRPHI)
3803 .addReg(Rtemp2);
3828 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3832 .addReg(Ws2)
3833 .addReg(MI.getOperand(1).getReg());
3857 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
3861 .addReg(Ws2)
3862 .addReg(MI.getOperand(1).getReg());
lib/Target/Mips/MipsSEInstrInfo.cpp 112 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
133 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
134 .addReg(DestReg, RegState::ImplicitDefine);
138 .addReg(DestReg)
139 .addReg(SrcReg, getKillRegState(KillSrc));
177 MIB.addReg(DestReg, RegState::Define);
180 MIB.addReg(SrcReg, getKillRegState(KillSrc));
183 MIB.addReg(ZeroReg);
319 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
404 BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
592 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
602 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
602 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
636 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
641 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
683 .addReg(Mips::RA_64, RegState::Undef);
686 .addReg(Mips::RA, RegState::Undef);
740 LoInst.addReg(DstLo, RegState::Define);
741 HiInst.addReg(DstHi, RegState::Define);
744 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
745 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
768 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
769 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
810 .addReg(SrcReg);
812 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
848 .addReg(LoReg);
866 .addReg(DstReg)
867 .addReg(HiReg);
872 .addReg(HiReg);
895 .addReg(TargetReg)
896 .addReg(ZERO);
898 .addReg(TargetReg)
899 .addReg(ZERO);
900 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
900 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
lib/Target/Mips/MipsSERegisterInfo.cpp 230 .addReg(FrameReg)
247 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg)
248 .addReg(Reg, RegState::Kill);
lib/Target/NVPTX/NVPTXFrameLowering.cpp 58 .addReg(NVPTX::VRFrameLocal);
lib/Target/NVPTX/NVPTXInstrInfo.cpp 69 .addReg(SrcReg, getKillRegState(KillSrc));
198 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
204 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
lib/Target/NVPTX/NVPTXPeephole.cpp 114 .addReg(NVPTX::VRFrameLocal)
lib/Target/PowerPC/PPCBranchSelector.cpp 343 .addImm(PPC::InvertPredicate(Pred)).addReg(CRReg).addImm(2);
346 BuildMI(MBB, I, dl, TII->get(PPC::BCn)).addReg(CRBit).addImm(2);
349 BuildMI(MBB, I, dl, TII->get(PPC::BC)).addReg(CRBit).addImm(2);
lib/Target/PowerPC/PPCEarlyReturn.cpp 94 .addReg(J->getOperand(1).getReg())
109 .addReg(J->getOperand(0).getReg())
lib/Target/PowerPC/PPCFastISel.cpp 159 TII.get(TargetOpcode::COPY), TmpReg).addReg(SrcReg, Flag, SubReg);
550 .addImm(Addr.Offset).addReg(Addr.Base.Reg);
584 MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
584 MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
586 MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
586 MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
688 .addReg(SrcReg)
700 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
700 .addReg(SrcReg).addImm(Addr.Offset).addReg(Addr.Base.Reg);
723 .addReg(SrcReg);
730 MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
730 MIB.addReg(Addr.Base.Reg).addReg(IndexReg);
732 MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
732 MIB.addReg(PPC::ZERO8).addReg(Addr.Base.Reg);
798 .addReg(CondReg).addMBB(TBB);
949 .addReg(SrcReg1).addReg(SrcReg2);
949 .addReg(SrcReg1).addReg(SrcReg2);
952 .addReg(SrcReg1).addImm(Imm);
995 .addReg(SrcReg);
1000 .addReg(SrcReg);
1005 .addReg(SrcReg);
1099 .addReg(SrcReg);
1143 .addReg(FPReg);
1254 .addReg(SrcReg);
1350 .addReg(SrcReg1)
1367 .addReg(SrcReg1).addReg(SrcReg2);
1367 .addReg(SrcReg1).addReg(SrcReg2);
1481 TII.get(TargetOpcode::COPY), ArgReg).addReg(Arg);
1528 ResultReg).addReg(SourcePhysReg);
1668 MIB.addReg(RegArgs[II], RegState::Implicit);
1673 MIB.addReg(PPC::X2, RegState::Implicit);
1729 TII.get(TargetOpcode::COPY), RetReg).addReg(SrcReg);
1787 .addReg(SrcReg);
1796 MIB.addReg(RetRegs[i], RegState::Implicit);
1823 .addReg(SrcReg);
1836 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB).addImm(/*ME=*/31);
1849 .addReg(SrcReg).addImm(/*SH=*/0).addImm(MB);
1862 .addReg(AddrReg);
2030 .addConstantPoolIndex(Idx).addReg(PPC::X2);
2032 .addImm(0).addReg(TmpReg).addMemOperand(MMO);
2036 TmpReg).addReg(PPC::X2).addConstantPoolIndex(Idx);
2042 TmpReg2).addConstantPoolIndex(Idx).addReg(TmpReg);
2045 .addReg(TmpReg2);
2049 .addReg(TmpReg)
2082 .addReg(PPC::X2);
2094 HighPartReg).addReg(PPC::X2).addGlobalAddress(GV);
2098 DestReg).addGlobalAddress(GV).addReg(HighPartReg);
2102 DestReg).addReg(HighPartReg).addGlobalAddress(GV);
2131 .addReg(TmpReg).addImm(Lo);
2175 TmpReg2).addReg(TmpReg1).addImm(Shift).addImm(63 - Shift);
2183 TmpReg3).addReg(TmpReg2).addImm(Hi);
2190 ResultReg).addReg(TmpReg3).addImm(Lo);
lib/Target/PowerPC/PPCFrameLowering.cpp 387 .addReg(SrcReg)
391 .addReg(SrcReg, RegState::Kill)
396 .addReg(SrcReg)
400 .addReg(SrcReg, RegState::Kill)
405 .addReg(SrcReg)
409 .addReg(SrcReg, RegState::Kill)
413 .addReg(DstReg, RegState::Kill)
980 MIB.addReg(MustSaveCRs[i], CrState);
982 .addReg(TempReg, getKillRegState(true))
984 .addReg(SPReg);
1005 MIB.addReg(MustSaveCRs[i], CrState);
1011 .addReg(FPReg)
1013 .addReg(SPReg);
1016 .addReg(PPC::R30)
1018 .addReg(SPReg);
1021 .addReg(BPReg)
1023 .addReg(SPReg);
1028 .addReg(ScratchReg, getKillRegState(true))
1030 .addReg(SPReg);
1036 .addReg(TempReg, getKillRegState(true))
1038 .addReg(SPReg);
1051 .addReg(SPReg)
1052 .addReg(SPReg);
1063 .addReg(SPReg)
1068 .addReg(SPReg)
1074 .addReg(ScratchReg, RegState::Kill)
1081 .addReg(TempReg, RegState::Kill)
1084 .addReg(ScratchReg, RegState::Kill)
1085 .addReg(TempReg, RegState::Kill);
1089 .addReg(SPReg, RegState::Kill)
1090 .addReg(SPReg)
1091 .addReg(ScratchReg);
1096 .addReg(SPReg)
1098 .addReg(SPReg);
1104 .addReg(ScratchReg, RegState::Kill)
1107 .addReg(SPReg, RegState::Kill)
1108 .addReg(SPReg)
1109 .addReg(ScratchReg);
1118 .addReg(TOCReg, getKillRegState(true))
1120 .addReg(SPReg);
1137 .addReg(ScratchReg, RegState::Kill)
1138 .addReg(SPReg);
1148 .addReg(ScratchReg)
1153 .addReg(FPReg, RegState::Kill) // Save FP.
1154 .addReg(PPC::ZERO)
1155 .addReg(ScratchReg); // This will be the index (R0 is ok here).
1160 .addReg(ScratchReg)
1164 .addReg(PPC::R30, RegState::Kill) // Save PIC base pointer.
1165 .addReg(PPC::ZERO)
1166 .addReg(ScratchReg); // This will be the index (R0 is ok here).
1171 .addReg(ScratchReg)
1175 .addReg(BPReg, RegState::Kill) // Save BP.
1176 .addReg(PPC::ZERO)
1177 .addReg(ScratchReg); // This will be the index (R0 is ok here).
1180 .addReg(ScratchReg, RegState::Kill)
1191 .addReg(FPReg)
1193 .addReg(ScratchReg);
1196 .addReg(PPC::R30)
1198 .addReg(ScratchReg);
1201 .addReg(BPReg)
1203 .addReg(ScratchReg);
1205 .addReg(ScratchReg, RegState::Kill)
1206 .addReg(ScratchReg);
1216 .addReg(FPReg)
1218 .addReg(SPReg);
1221 .addReg(PPC::R30)
1223 .addReg(SPReg);
1226 .addReg(BPReg)
1228 .addReg(SPReg);
1230 .addReg(SPReg)
1296 .addReg(SPReg)
1297 .addReg(SPReg);
1549 .addReg(FPReg).addImm(FrameSize);
1554 .addReg(ScratchReg, RegState::Kill)
1557 .addReg(RBReg)
1558 .addReg(FPReg)
1559 .addReg(ScratchReg);
1564 .addReg(SPReg)
1583 .addReg(FPReg)
1584 .addReg(FPReg);
1589 .addReg(SPReg);
1608 .addReg(SPReg);
1611 .addReg(TempReg, getKillRegState(i == e-1));
1622 .addReg(RBReg);
1632 .addReg(RBReg);
1641 .addReg(SPReg);
1645 .addReg(RBReg);
1651 .addReg(RBReg);
1656 .addReg(RBReg);
1665 .addReg(RBReg)
1666 .addReg(RBReg);
1669 .addReg(RBReg)
1675 .addReg(ScratchReg)
1676 .addReg(ScratchReg);
1682 .addReg(SPReg);
1689 .addReg(TempReg, getKillRegState(i == e-1));
1692 BuildMI(MBB, StackUpdateLoc, dl, MTLRInst).addReg(ScratchReg);
1706 .addReg(SPReg).addImm(CallerAllocatedAmt);
1711 .addReg(ScratchReg, RegState::Kill)
1714 .addReg(SPReg)
1715 .addReg(FPReg)
1716 .addReg(ScratchReg);
2225 CRMIB.addReg(Reg, RegState::ImplicitKill);
2246 .addReg(Reg, RegState::ImplicitKill);
2250 .addReg(PPC::R12,
2258 .addReg(Reg, getKillRegState(true));
2297 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
2301 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
2305 .addReg(MoveReg, getKillRegState(true)));
2328 .addReg(StackReg, RegState::Kill)
2335 .addReg(TmpReg, RegState::Kill)
2338 .addReg(StackReg, RegState::Kill)
2339 .addReg(TmpReg);
2415 .addReg(CSI[i].getDstReg(), getKillRegState(true));
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 407 UpdatedVRSAVE).addReg(InVRSAVE);
408 BuildMI(EntryBB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(UpdatedVRSAVE);
422 BuildMI(*BB, IP, dl, TII.get(PPC::MTVRSAVE)).addReg(InVRSAVE);
453 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
453 .addReg(TempReg, RegState::Define).addReg(GlobalBaseReg);
lib/Target/PowerPC/PPCISelLowering.cpp10382 .addReg(ptrA).addReg(ptrB);
10382 .addReg(ptrA).addReg(ptrB);
10384 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
10384 BuildMI(BB, dl, TII->get(BinOpcode), TmpReg).addReg(incr).addReg(dest);
10390 ExtReg).addReg(dest);
10392 .addReg(incr).addReg(ExtReg);
10392 .addReg(incr).addReg(ExtReg);
10395 .addReg(incr).addReg(dest);
10395 .addReg(incr).addReg(dest);
10398 .addImm(CmpPred).addReg(PPC::CR0).addMBB(exitMBB);
10404 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
10404 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
10404 .addReg(TmpReg).addReg(ptrA).addReg(ptrB);
10406 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
10505 .addReg(ptrA)
10506 .addReg(ptrB);
10513 .addReg(Ptr1Reg, 0, is64bit ? PPC::sub_32 : 0)
10519 .addReg(Shift1Reg)
10523 .addReg(Ptr1Reg)
10528 .addReg(Ptr1Reg)
10532 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg).addReg(incr).addReg(ShiftReg);
10532 BuildMI(BB, dl, TII->get(PPC::SLW), Incr2Reg).addReg(incr).addReg(ShiftReg);
10538 .addReg(Mask3Reg)
10542 .addReg(Mask2Reg)
10543 .addReg(ShiftReg);
10547 .addReg(ZeroReg)
10548 .addReg(PtrReg);
10551 .addReg(Incr2Reg)
10552 .addReg(TmpDestReg);
10554 .addReg(TmpDestReg)
10555 .addReg(MaskReg);
10556 BuildMI(BB, dl, TII->get(PPC::AND), Tmp3Reg).addReg(TmpReg).addReg(MaskReg);
10556 BuildMI(BB, dl, TII->get(PPC::AND), Tmp3Reg).addReg(TmpReg).addReg(MaskReg);
10562 .addReg(TmpDestReg)
10563 .addReg(MaskReg);
10569 .addReg(SReg)
10570 .addReg(ShiftReg);
10573 .addReg(ValueReg);
10578 .addReg(CmpReg)
10579 .addReg(ValueReg);
10582 .addReg(PPC::CR0)
10588 BuildMI(BB, dl, TII->get(PPC::OR), Tmp4Reg).addReg(Tmp3Reg).addReg(Tmp2Reg);
10588 BuildMI(BB, dl, TII->get(PPC::OR), Tmp4Reg).addReg(Tmp3Reg).addReg(Tmp2Reg);
10590 .addReg(Tmp4Reg)
10591 .addReg(ZeroReg)
10592 .addReg(PtrReg);
10595 .addReg(PPC::CR0)
10604 .addReg(TmpDestReg)
10605 .addReg(ShiftReg);
10684 .addReg(PPC::X2)
10686 .addReg(BufReg)
10700 .addReg(BaseReg)
10702 .addReg(BufReg)
10727 .addReg(LabelReg)
10729 .addReg(BufReg);
10732 .addReg(LabelReg)
10734 .addReg(BufReg);
10744 .addReg(mainDstReg).addMBB(mainMBB)
10745 .addReg(restoreDstReg).addMBB(thisMBB);
10791 .addReg(BufReg);
10795 .addReg(BufReg);
10803 .addReg(BufReg);
10807 .addReg(BufReg);
10815 .addReg(BufReg);
10819 .addReg(BufReg);
10827 .addReg(BufReg);
10831 .addReg(BufReg);
10840 .addReg(BufReg)
10846 TII->get(PVT == MVT::i64 ? PPC::MTCTR8 : PPC::MTCTR)).addReg(Tmp);
10969 .addReg(MI.getOperand(1).getReg())
10975 .addReg(MI.getOperand(1).getReg())
10992 .addReg(MI.getOperand(3).getReg())
10994 .addReg(MI.getOperand(2).getReg())
11035 .addReg(HiReg)
11036 .addReg(ReadAgainReg);
11039 .addReg(CmpReg)
11210 BuildMI(BB, dl, TII->get(LoadMnemonic), dest).addReg(ptrA).addReg(ptrB);
11210 BuildMI(BB, dl, TII->get(LoadMnemonic), dest).addReg(ptrA).addReg(ptrB);
11212 .addReg(oldval)
11213 .addReg(dest);
11216 .addReg(PPC::CR0)
11223 .addReg(newval)
11224 .addReg(ptrA)
11225 .addReg(ptrB);
11228 .addReg(PPC::CR0)
11236 .addReg(dest)
11237 .addReg(ptrA)
11238 .addReg(ptrB);
11329 .addReg(ptrA)
11330 .addReg(ptrB);
11338 .addReg(Ptr1Reg, 0, is64bit ? PPC::sub_32 : 0)
11344 .addReg(Shift1Reg)
11348 .addReg(Ptr1Reg)
11353 .addReg(Ptr1Reg)
11358 .addReg(newval)
11359 .addReg(ShiftReg);
11361 .addReg(oldval)
11362 .addReg(ShiftReg);
11368 .addReg(Mask3Reg)
11372 .addReg(Mask2Reg)
11373 .addReg(ShiftReg);
11375 .addReg(NewVal2Reg)
11376 .addReg(MaskReg);
11378 .addReg(OldVal2Reg)
11379 .addReg(MaskReg);
11383 .addReg(ZeroReg)
11384 .addReg(PtrReg);
11386 .addReg(TmpDestReg)
11387 .addReg(MaskReg);
11389 .addReg(TmpReg)
11390 .addReg(OldVal3Reg);
11393 .addReg(PPC::CR0)
11400 .addReg(TmpDestReg)
11401 .addReg(MaskReg);
11403 .addReg(Tmp2Reg)
11404 .addReg(NewVal3Reg);
11406 .addReg(Tmp4Reg)
11407 .addReg(ZeroReg)
11408 .addReg(PtrReg);
11411 .addReg(PPC::CR0)
11419 .addReg(TmpDestReg)
11420 .addReg(ZeroReg)
11421 .addReg(PtrReg);
11428 .addReg(TmpReg)
11429 .addReg(ShiftReg);
11450 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
11450 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
11453 BuildMI(*BB, MI, dl, TII->get(PPC::MTFSFb)).addImm(1).addReg(MFFSReg);
11471 .addReg(MI.getOperand(1).getReg())
11475 .addReg(isEQ ? PPC::CR0EQ : PPC::CR0GT);
11483 .addReg(CRReg);
11490 .addReg(PPC::CR0EQ);
11524 .addReg(SrcReg);
11554 .addReg(SrcReg)
11601 .addReg(ImDefReg)
11607 .addReg(OldFPSCRTmpReg)
11608 .addReg(ExtSrcReg)
11619 .addReg(NewFPSCRReg)
15058 .addReg(*I);
15064 .addReg(NewVR);
lib/Target/PowerPC/PPCInstrInfo.cpp 428 .addReg(Reg0, RegState::Define | getDeadRegState(Reg0IsDead))
429 .addReg(Reg2, getKillRegState(Reg2IsKill))
430 .addReg(Reg1, getKillRegState(Reg1IsKill))
869 .addReg(OldFirstReg);
873 .addReg(FirstReg).addReg(SecondReg)
873 .addReg(FirstReg).addReg(SecondReg)
874 .addReg(Cond[1].getReg(), 0, SubIdx);
935 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
940 .addReg(DestReg, RegState::Kill)
947 BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
952 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
959 BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
967 BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
972 BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
977 BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
1022 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1022 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc));
1024 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1210 BuildMI(MF, DL, get(Opcode)).addReg(SrcReg, getKillRegState(isKill)),
1915 .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
2145 .addReg(Reg);
2222 BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2222 BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
2225 .addReg(PPC::CR7)
2312 .addImm(LII.Imm).addReg(PPC::CR0, RegState::ImplicitDefine);
lib/Target/PowerPC/PPCMIPeephole.cpp 660 .addReg(TmpReg)
661 .addReg(NarrowReg)
707 .addReg(SrcReg);
787 .addReg(DominatorReg)
1299 .addReg(BI1->getOperand(1).getReg()).addMBB(MBB1)
1300 .addReg(BI2->getOperand(1).getReg()).addMBB(MBBtoMoveCmp);
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 99 MIB.addReg(MI.getOperand(i - 1).getReg()).addMBB(NewMBB);
221 .addReg(BSI.SplitCond->getOperand(0).getReg())
lib/Target/PowerPC/PPCRegisterInfo.cpp 534 .addReg(PPC::X31)
538 .addReg(PPC::R31)
543 .addReg(PPC::X1);
547 .addReg(PPC::R1);
568 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
569 .addReg(NegSizeReg1, RegState::Kill);
574 .addReg(Reg, RegState::Kill)
575 .addReg(PPC::X1)
576 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
578 .addReg(PPC::X1)
593 .addReg(UnalNegSizeReg, getKillRegState(KillNegSizeReg))
594 .addReg(NegSizeReg1, RegState::Kill);
599 .addReg(Reg, RegState::Kill)
600 .addReg(PPC::R1)
601 .addReg(NegSizeReg, getKillRegState(KillNegSizeReg));
603 .addReg(PPC::R1)
663 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
673 .addReg(Reg1, RegState::Kill)
680 .addReg(Reg, RegState::Kill),
719 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0)
724 .addReg(Reg, RegState::Kill);
787 .addReg(getCRFromCRBit(SrcReg), RegState::Undef)
788 .addReg(SrcReg,
798 .addReg(Reg1, RegState::Kill)
803 .addReg(Reg, RegState::Kill),
837 .addReg(getCRFromCRBit(DestReg));
842 .addReg(RegO, RegState::Kill)
843 .addReg(Reg, RegState::Kill)
850 .addReg(RegO, RegState::Kill)
854 .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
876 .addReg(SrcReg, getKillRegState(MI.getOperand(0).isKill()));
879 BuildMI(MBB, II, dl, TII.get(PPC::STW)).addReg(Reg, RegState::Kill),
907 .addReg(Reg, RegState::Kill);
1107 .addReg(SRegHi, RegState::Kill)
lib/Target/PowerPC/PPCTLSDynamicCall.cpp 117 .addReg(InReg);
126 .addReg(GPR3));
133 .addReg(GPR3);
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 804 .addReg(SrcReg)
805 .addReg(SrcReg)
918 .addReg(NewVReg);
926 .addReg(VSRCTmp2);
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 251 .addReg(AddrReg);
257 .addReg(DestReg)
258 .addReg(IncrReg);
260 .addReg(ScratchReg)
265 .addReg(AddrReg)
266 .addReg(ScratchReg);
268 .addReg(ScratchReg)
269 .addReg(RISCV::X0)
285 .addReg(OldValReg)
286 .addReg(NewValReg);
288 .addReg(ScratchReg)
289 .addReg(MaskReg);
291 .addReg(OldValReg)
292 .addReg(ScratchReg);
317 .addReg(AddrReg);
323 .addReg(RISCV::X0)
324 .addReg(IncrReg);
328 .addReg(DestReg)
329 .addReg(IncrReg);
333 .addReg(DestReg)
334 .addReg(IncrReg);
338 .addReg(DestReg)
339 .addReg(IncrReg);
341 .addReg(ScratchReg)
350 .addReg(AddrReg)
351 .addReg(ScratchReg);
353 .addReg(ScratchReg)
354 .addReg(RISCV::X0)
400 .addReg(ValReg)
401 .addReg(ShamtReg);
403 .addReg(ValReg)
404 .addReg(ShamtReg);
457 .addReg(AddrReg);
459 .addReg(DestReg)
460 .addReg(MaskReg);
462 .addReg(DestReg)
471 .addReg(Scratch2Reg)
472 .addReg(IncrReg)
479 .addReg(IncrReg)
480 .addReg(Scratch2Reg)
486 .addReg(Scratch2Reg)
487 .addReg(IncrReg)
492 .addReg(IncrReg)
493 .addReg(Scratch2Reg)
509 .addReg(AddrReg)
510 .addReg(Scratch1Reg);
512 .addReg(Scratch1Reg)
513 .addReg(RISCV::X0)
565 .addReg(AddrReg);
567 .addReg(DestReg)
568 .addReg(CmpValReg)
574 .addReg(AddrReg)
575 .addReg(NewValReg);
577 .addReg(ScratchReg)
578 .addReg(RISCV::X0)
587 .addReg(AddrReg);
589 .addReg(DestReg)
590 .addReg(MaskReg);
592 .addReg(ScratchReg)
593 .addReg(CmpValReg)
605 .addReg(AddrReg)
606 .addReg(ScratchReg);
608 .addReg(ScratchReg)
609 .addReg(RISCV::X0)
646 .addReg(DestReg)
lib/Target/RISCV/RISCVFrameLowering.cpp 75 .addReg(SrcReg)
89 .addReg(SrcReg)
90 .addReg(ScratchReg, RegState::Kill)
214 .addReg(SPReg)
221 .addReg(SPReg)
224 .addReg(VR)
lib/Target/RISCV/RISCVISelLowering.cpp 1130 .addReg(RISCV::X0);
1133 .addReg(RISCV::X0);
1136 .addReg(RISCV::X0);
1139 .addReg(HiReg)
1140 .addReg(ReadAgainReg)
1201 .addReg(LoReg, getKillRegState(MI.getOperand(1).isKill()))
1206 .addReg(HiReg, getKillRegState(MI.getOperand(2).isKill()))
1319 .addReg(LHS)
1320 .addReg(RHS)
1336 .addReg(SelectMBBI->getOperand(4).getReg())
1338 .addReg(SelectMBBI->getOperand(5).getReg())
lib/Target/RISCV/RISCVInstrInfo.cpp 91 .addReg(SrcReg, getKillRegState(KillSrc))
106 .addReg(SrcReg, getKillRegState(KillSrc))
107 .addReg(SrcReg, getKillRegState(KillSrc));
132 .addReg(SrcReg, getKillRegState(IsKill))
191 .addReg(SrcReg, RegState::Kill)
402 .addReg(ScratchReg, RegState::Kill)
lib/Target/RISCV/RISCVRegisterInfo.cpp 134 .addReg(FrameReg)
135 .addReg(ScratchReg, RegState::Kill);
lib/Target/Sparc/SparcFrameLowering.cpp 53 .addReg(SP::O6).addImm(NumBytes);
67 .addReg(SP::G1).addImm(LO10(NumBytes));
69 .addReg(SP::O6).addReg(SP::G1);
69 .addReg(SP::O6).addReg(SP::G1);
80 .addReg(SP::G1).addImm(LOX10(NumBytes));
82 .addReg(SP::O6).addReg(SP::G1);
82 .addReg(SP::O6).addReg(SP::G1);
187 .addReg(SP::O6).addImm(Bias);
194 .addReg(regUnbiased).addImm(MaxAlign - 1);
199 .addReg(regUnbiased).addImm(-Bias);
230 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
231 .addReg(SP::G0);
lib/Target/Sparc/SparcISelLowering.cpp 3163 .addReg(MI.getOperand(1).getReg())
3165 .addReg(MI.getOperand(2).getReg())
lib/Target/Sparc/SparcInstrInfo.cpp 322 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
323 .addReg(SrcReg, getKillRegState(KillSrc));
331 .addReg(SrcReg, getKillRegState(KillSrc));
335 .addReg(SrcReg, getKillRegState(KillSrc));
346 .addReg(SrcReg, getKillRegState(KillSrc));
362 .addReg(SP::G0)
363 .addReg(SrcReg, getKillRegState(KillSrc));
367 .addReg(SrcReg, getKillRegState(KillSrc));
384 MIB.addReg(SP::G0);
385 MIB.addReg(Src);
411 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
414 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
417 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
420 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
423 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
428 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO);
503 .addReg(SP::G7)
lib/Target/Sparc/SparcRegisterInfo.cpp 137 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
138 .addReg(FramePtr);
153 .addReg(SP::G1).addImm(LOX10(Offset));
155 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
156 .addReg(FramePtr);
190 .addReg(FrameReg).addImm(0).addReg(SrcEvenReg);
190 .addReg(FrameReg).addImm(0).addReg(SrcEvenReg);
202 .addReg(FrameReg).addImm(0);
lib/Target/SystemZ/SystemZElimCompare.cpp 241 MIB.addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
572 MIB.add(Target).addReg(SystemZ::CC,
lib/Target/SystemZ/SystemZFrameLowering.cpp 124 MIB.addReg(GPR64, getImplRegState(IsImplicit) | getKillRegState(!IsLive));
190 MIB.addReg(SystemZ::R15D).addImm(StartOffset);
264 MIB.addReg(LowGPR, RegState::Define);
265 MIB.addReg(HighGPR, RegState::Define);
268 MIB.addReg(HasFP ? SystemZ::R11D : SystemZ::R15D);
276 MIB.addReg(Reg, RegState::ImplicitDefine);
334 .addReg(Reg).addImm(ThisVal);
398 .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
398 .addReg(SystemZ::R1D, RegState::Define).addReg(SystemZ::R15D);
413 .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D).addImm(0).addReg(0);
413 .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D).addImm(0).addReg(0);
413 .addReg(SystemZ::R1D, RegState::Kill).addReg(SystemZ::R15D).addImm(0).addReg(0);
419 .addReg(SystemZ::R15D);
lib/Target/SystemZ/SystemZISelLowering.cpp 6515 .addReg(0);
6607 .addReg(TrueReg).addMBB(TrueMBB)
6608 .addReg(FalseReg).addMBB(FalseMBB);
6748 .addReg(SrcReg)
6788 .addReg(SrcReg)
6791 .addReg(IndexReg);
6856 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal).add(Base).addImm(Disp).addReg(0);
6869 .addReg(OrigVal).addMBB(StartMBB)
6870 .addReg(Dest).addMBB(LoopMBB);
6873 .addReg(OldVal).addReg(BitShift).addImm(0);
6873 .addReg(OldVal).addReg(BitShift).addImm(0);
6877 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp).addReg(RotatedOldVal).add(Src2);
6881 .addReg(Tmp).addImm(-1U << (32 - BitSize));
6886 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
6888 .addReg(Tmp2).addImm(-1);
6893 .addReg(RotatedOldVal)
6899 .addReg(RotatedOldVal).addReg(Src2.getReg())
6899 .addReg(RotatedOldVal).addReg(Src2.getReg())
6903 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
6903 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
6905 .addReg(OldVal)
6906 .addReg(NewVal)
6976 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal).add(Base).addImm(Disp).addReg(0);
6986 .addReg(OrigVal).addMBB(StartMBB)
6987 .addReg(Dest).addMBB(UpdateMBB);
6990 .addReg(OldVal).addReg(BitShift).addImm(0);
6990 .addReg(OldVal).addReg(BitShift).addImm(0);
6992 .addReg(RotatedOldVal).addReg(Src2);
6992 .addReg(RotatedOldVal).addReg(Src2);
7004 .addReg(RotatedOldVal).addReg(Src2)
7004 .addReg(RotatedOldVal).addReg(Src2)
7017 .addReg(RotatedOldVal).addMBB(LoopMBB)
7018 .addReg(RotatedAltVal).addMBB(UseAltMBB);
7021 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
7021 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
7023 .addReg(OldVal)
7024 .addReg(NewVal)
7089 .addReg(0);
7108 .addReg(OrigOldVal).addMBB(StartMBB)
7109 .addReg(RetryOldVal).addMBB(SetMBB);
7111 .addReg(OrigCmpVal).addMBB(StartMBB)
7112 .addReg(RetryCmpVal).addMBB(SetMBB);
7114 .addReg(OrigSwapVal).addMBB(StartMBB)
7115 .addReg(RetrySwapVal).addMBB(SetMBB);
7117 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
7117 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
7119 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
7119 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
7121 .addReg(Dest).addReg(RetryCmpVal);
7121 .addReg(Dest).addReg(RetryCmpVal);
7139 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
7139 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
7141 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
7141 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
7143 .addReg(OldVal)
7144 .addReg(StoreVal)
7180 .addReg(Tmp1).addReg(Hi).addImm(SystemZ::subreg_h64);
7180 .addReg(Tmp1).addReg(Hi).addImm(SystemZ::subreg_h64);
7182 .addReg(Tmp2).addReg(Lo).addImm(SystemZ::subreg_l64);
7182 .addReg(Tmp2).addReg(Lo).addImm(SystemZ::subreg_l64);
7212 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
7212 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
7216 .addReg(In128).addReg(Src).addImm(SystemZ::subreg_l64);
7216 .addReg(In128).addReg(Src).addImm(SystemZ::subreg_l64);
7286 .addReg(StartDestReg).addMBB(StartMBB)
7287 .addReg(NextDestReg).addMBB(NextMBB);
7290 .addReg(StartSrcReg).addMBB(StartMBB)
7291 .addReg(NextSrcReg).addMBB(NextMBB);
7293 .addReg(StartCountReg).addMBB(StartMBB)
7294 .addReg(NextCountReg).addMBB(NextMBB);
7298 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
7298 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
7300 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
7301 .addReg(ThisSrcReg).addImm(SrcDisp);
7322 .addReg(ThisDestReg).addImm(256).addReg(0);
7322 .addReg(ThisDestReg).addImm(256).addReg(0);
7325 .addReg(ThisSrcReg).addImm(256).addReg(0);
7325 .addReg(ThisSrcReg).addImm(256).addReg(0);
7327 .addReg(ThisCountReg).addImm(-1);
7329 .addReg(NextCountReg).addImm(0);
7355 .addReg(0);
7364 .addReg(0);
7440 .addReg(Start1Reg).addMBB(StartMBB)
7441 .addReg(End1Reg).addMBB(LoopMBB);
7443 .addReg(Start2Reg).addMBB(StartMBB)
7444 .addReg(End2Reg).addMBB(LoopMBB);
7445 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
7447 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
7447 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
7448 .addReg(This1Reg).addReg(This2Reg);
7448 .addReg(This1Reg).addReg(This2Reg);
7526 .addReg(SrcReg);
lib/Target/SystemZ/SystemZInstrBuilder.h 40 return MIB.addFrameIndex(FI).addImm(Offset).addReg(0).addMemOperand(MMO);
lib/Target/SystemZ/SystemZInstrInfo.cpp 90 MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
91 MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl | Reg128Killed));
222 .addReg(SystemZ::A0)
223 .addReg(Reg64, RegState::ImplicitDefine);
227 .addReg(Reg64)
228 .addReg(0)
233 .addReg(SystemZ::A1);
237 MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0);
237 MachineInstrBuilder(MF, MI).addReg(Reg64).addImm(40).addReg(0);
263 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc));
267 .addReg(DestReg, RegState::Undef)
268 .addReg(SrcReg, getKillRegState(KillSrc) | getUndefRegState(UndefSrc))
590 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
591 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
604 .addReg(FalseReg).addReg(TrueReg)
604 .addReg(FalseReg).addReg(TrueReg)
729 .addReg(SystemZ::CC, RegState::Implicit);
736 .addReg(SystemZ::CC, RegState::Implicit);
750 .addReg(SystemZ::CC, RegState::Implicit);
760 .addReg(SystemZ::CC, RegState::Implicit);
777 .addReg(SrcReg, RegState::Implicit);
781 .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit));
802 .addReg(SrcRegHi, getKillRegState(KillSrc))
803 .addReg(SrcRegLo, getKillRegState(KillSrc));
818 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1);
834 .addReg(SrcReg, getKillRegState(KillSrc))
868 .addReg(SrcReg, getKillRegState(KillSrc));
882 .addReg(SrcReg, getKillRegState(isKill)),
976 .addReg(0)
977 .addReg(Src.getReg(), getKillRegState(Src.isKill()),
1098 .addReg(0);
1109 .addReg(0);
1201 MIB.addReg(0);
lib/Target/SystemZ/SystemZLDCleanup.cpp 121 .addReg(TLSBaseAddrReg);
141 .addReg(SystemZ::R2D);
lib/Target/SystemZ/SystemZPostRewrite.cpp 124 .addReg(MBBI->getOperand(1).getReg(), getRegState(MBBI->getOperand(1)));
131 .addReg(MBBI->getOperand(2).getReg(), getRegState(MBBI->getOperand(2)));
201 .addReg(MI.getOperand(2).getReg(), getRegState(MI.getOperand(2)));
229 .addReg(SrcMO.getReg());
lib/Target/SystemZ/SystemZRegisterInfo.cpp 318 .addReg(BasePtr).addImm(HighOffset).addReg(0);
318 .addReg(BasePtr).addImm(HighOffset).addReg(0);
324 .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
324 .addReg(ScratchReg, RegState::Kill).addReg(BasePtr);
lib/Target/SystemZ/SystemZShortenInst.cpp 147 .addReg(SystemZ::CC, RegState::ImplicitDefine | RegState::Dead);
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 970 .addReg(ExnReg);
lib/Target/WebAssembly/WebAssemblyExplicitLocals.cpp 262 .addReg(MI.getOperand(2).getReg());
287 .addReg(NewReg);
295 .addReg(NewReg);
lib/Target/WebAssembly/WebAssemblyFastISel.cpp 408 MIB.addReg(Addr.getReg());
470 .addReg(Reg)
471 .addReg(Imm);
500 .addReg(Reg)
501 .addReg(Imm);
506 .addReg(Left)
507 .addReg(Imm);
524 .addReg(Reg);
546 .addReg(Reg);
585 .addReg(Reg);
593 .addReg(Reg);
872 MIB.addReg(ResultReg, RegState::Define);
877 MIB.addReg(CalleeReg);
880 MIB.addReg(ArgReg);
938 .addReg(TrueReg)
939 .addReg(FalseReg)
940 .addReg(CondReg);
957 .addReg(Reg);
1054 .addReg(LHS)
1055 .addReg(RHS);
1115 .addReg(LHS)
1116 .addReg(RHS);
1265 MIB.addReg(ValueReg);
1291 .addReg(CondReg);
1350 .addReg(Reg);
lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp 363 MIB.addReg(Reg);
lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp 134 .addReg(SrcReg);
189 .addReg(SPReg);
198 .addReg(SPReg)
199 .addReg(OffsetReg);
210 .addReg(WebAssembly::SP32)
211 .addReg(BitmaskReg);
218 .addReg(WebAssembly::SP32);
254 .addReg(hasFP(MF) ? WebAssembly::FP32 : WebAssembly::SP32)
255 .addReg(OffsetReg);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 388 BuildMI(BB, DL, TII.get(Abs), Tmp0).addReg(InReg);
392 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1);
392 BuildMI(BB, DL, TII.get(LT), CmpReg).addReg(Tmp0).addReg(Tmp1);
402 BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1);
402 BuildMI(BB, DL, TII.get(GE), SecondCmpReg).addReg(Tmp0).addReg(Tmp1);
403 BuildMI(BB, DL, TII.get(And), AndReg).addReg(CmpReg).addReg(SecondCmpReg);
403 BuildMI(BB, DL, TII.get(And), AndReg).addReg(CmpReg).addReg(SecondCmpReg);
407 BuildMI(BB, DL, TII.get(Eqz), EqzReg).addReg(CmpReg);
411 BuildMI(BB, DL, TII.get(WebAssembly::BR_IF)).addMBB(TrueMBB).addReg(EqzReg);
412 BuildMI(FalseMBB, DL, TII.get(LoweredOpcode), FalseReg).addReg(InReg);
416 .addReg(FalseReg)
418 .addReg(TrueReg)
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp 84 .addReg(SrcReg, KillSrc ? RegState::Kill : 0);
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 174 .addReg(ExnReg);
312 .addReg(ExnReg);
348 .addReg(Reg);
352 BuildMI(ElseMBB, DL, TII.get(WebAssembly::RETHROW)).addReg(ExnReg);
lib/Target/WebAssembly/WebAssemblyLowerBrUnless.cpp 193 .addReg(Cond);
204 .addReg(Cond);
lib/Target/WebAssembly/WebAssemblyPeephole.cpp 122 .addReg(Reg);
lib/Target/WebAssembly/WebAssemblyRegStackify.cpp 615 .addReg(Reg, RegState::Define)
616 .addReg(DefReg, getUndefRegState(DefMO.isDead()));
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 127 .addReg(FrameRegister)
128 .addReg(OffsetOp);
lib/Target/X86/X86AvoidStoreForwardingBlocks.cpp 401 .addReg(X86::NoRegister)
403 .addReg(X86::NoRegister)
421 .addReg(X86::NoRegister)
423 .addReg(X86::NoRegister)
424 .addReg(Reg1)
lib/Target/X86/X86CallFrameOptimization.cpp 546 .addReg(UndefReg)
570 .addReg(Reg)
lib/Target/X86/X86CmovConversion.cpp 835 .addReg(Op1Reg)
837 .addReg(Op2Reg)
lib/Target/X86/X86DomainReassignment.cpp 194 .addReg(Reg);
lib/Target/X86/X86ExpandPseudo.cpp 93 .addReg(X86::RIP)
95 .addReg(0)
98 .addReg(0);
101 .addReg(X86::R11);
294 .addReg(DestAddr.getReg());
324 BuildMI(MBB, MBBI, DL, TII->get(X86::POP32r)).addReg(X86::ECX, RegState::Define);
326 BuildMI(MBB, MBBI, DL, TII->get(X86::PUSH32r)).addReg(X86::ECX);
lib/Target/X86/X86FastISel.cpp 503 .addReg(ValReg, getKillRegState(ValIsKill)).addImm(1);
649 addFullAddress(MIB, AM).addReg(ValReg, getKillRegState(ValIsKill));
1252 TII.get(TargetOpcode::COPY), DstReg).addReg(SrcReg);
1271 TII.get(TargetOpcode::COPY), RetReg).addReg(Reg);
1286 MIB.addReg(RetRegs[i], RegState::Implicit);
1407 .addReg(Op0Reg)
1419 .addReg(Op0Reg)
1420 .addReg(Op1Reg);
1496 ResultReg).addReg(FlagReg1).addReg(FlagReg2);
1496 ResultReg).addReg(FlagReg1).addReg(FlagReg2);
1552 .addReg(ResultReg);
1557 .addImm(0).addReg(Result32).addImm(X86::sub_32bit);
1563 Result32).addReg(ResultReg);
1599 ResultReg).addReg(ZExtReg);
1609 Result32).addReg(ResultReg);
1726 .addReg(OpReg).addImm(1);
1766 .addReg(KOpReg);
1771 .addReg(OpReg)
1832 CReg).addReg(Op1Reg);
1839 .addReg(CReg, RegState::Kill);
1843 .addReg(Op0Reg);
1944 TII.get(OpEntry.OpCopy), TypeEntry.LowInReg).addReg(Op0Reg);
1961 .addReg(Zero32, 0, X86::sub_16bit);
1965 .addReg(Zero32);
1969 .addImm(0).addReg(Zero32).addImm(X86::sub_32bit);
1975 TII.get(OpEntry.OpDivRem)).addReg(Op1Reg);
1991 TII.get(Copy), SourceSuperReg).addReg(X86::AX);
1995 ResultSuperReg).addReg(SourceSuperReg).addImm(8);
2005 .addReg(OpEntry.DivRemResultReg);
2078 .addReg(FlagReg2).addReg(FlagReg1);
2078 .addReg(FlagReg2).addReg(FlagReg1);
2081 .addReg(FlagReg2).addReg(FlagReg1);
2081 .addReg(FlagReg2).addReg(FlagReg1);
2112 .addReg(KCondReg, getKillRegState(CondIsKill));
2117 .addReg(CondReg, getKillRegState(CondIsKill))
2228 TII.get(TargetOpcode::COPY), ResultReg).addReg(MovReg);
2249 TII.get(TargetOpcode::COPY), ResultReg).addReg(VBlendReg);
2275 TII.get(TargetOpcode::COPY), ResultReg).addReg(OrReg);
2330 .addReg(KCondReg, getKillRegState(CondIsKill));
2335 .addReg(CondReg, getKillRegState(CondIsKill))
2383 .addReg(OpReg, getKillRegState(OpIsKill));
2494 MIB.addReg(ImplicitDefReg);
2496 MIB.addReg(OpReg);
2640 .addReg(InputReg, RegState::Kill);
2662 .addReg(InputReg, RegState::Kill);
2704 TII.get(TargetOpcode::COPY), SrcReg).addReg(FrameReg);
2851 MIB.addReg(ImplicitDefReg);
2853 MIB.addReg(SrcReg);
2925 .addReg(LHSReg, getKillRegState(LHSIsKill));
2952 .addReg(LHSReg, getKillRegState(LHSIsKill));
2963 .addReg(LHSReg, getKillRegState(LHSIsKill));
3049 .addReg(Reg);
3148 .addReg(DstReg, getKillRegState(true));
3405 TII.get(TargetOpcode::COPY), VA.getLocReg()).addReg(ArgReg);
3447 TII.get(TargetOpcode::COPY), X86::EBX).addReg(Base);
3492 .addReg(CalleeOp);
3510 MIB.addReg(Is64Bit ? X86::RIP : 0).addImm(1).addReg(0);
3510 MIB.addReg(Is64Bit ? X86::RIP : 0).addImm(1).addReg(0);
3516 MIB.addReg(0);
3525 MIB.addReg(X86::EBX, RegState::Implicit);
3528 MIB.addReg(X86::AL, RegState::Implicit);
3532 MIB.addReg(Reg, RegState::Implicit);
3574 TII.get(TargetOpcode::COPY), CopyReg).addReg(SrcReg);
3587 .addReg(CopyReg);
3706 .addImm(0).addReg(SrcReg).addImm(X86::sub_32bit);
3990 .addReg(Op0, getKillRegState(Op0IsKill))
3991 .addReg(Op1, getKillRegState(Op1IsKill))
3992 .addReg(Op2, getKillRegState(Op2IsKill))
3993 .addReg(Op3, getKillRegState(Op3IsKill));
3996 .addReg(Op0, getKillRegState(Op0IsKill))
3997 .addReg(Op1, getKillRegState(Op1IsKill))
3998 .addReg(Op2, getKillRegState(Op2IsKill))
3999 .addReg(Op3, getKillRegState(Op3IsKill));
4001 TII.get(TargetOpcode::COPY), ResultReg).addReg(II.ImplicitDefs[0]);
lib/Target/X86/X86FixupBWInsts.cpp 324 .addReg(NewSrcReg, RegState::Undef)
325 .addReg(OldSrc.getReg(), RegState::Implicit);
lib/Target/X86/X86FixupLEAs.cpp 141 .addReg(0)
143 .addReg(0);
396 .addReg(BaseReg).addReg(IndexReg)
396 .addReg(BaseReg).addReg(IndexReg)
397 .addReg(Base.getReg(), RegState::Implicit)
398 .addReg(Index.getReg(), RegState::Implicit);
401 .addReg(BaseReg).addReg(IndexReg);
401 .addReg(BaseReg).addReg(IndexReg);
417 .addReg(BaseReg).addReg(Base.getReg(), RegState::Implicit);
417 .addReg(BaseReg).addReg(Base.getReg(), RegState::Implicit);
420 .addReg(BaseReg);
427 .addReg(BaseReg).addImm(Disp.getImm())
428 .addReg(Base.getReg(), RegState::Implicit);
431 .addReg(BaseReg).addImm(Disp.getImm());
510 BuildMI(MBB, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src);
584 .addReg(BaseReg)
585 .addReg(IndexReg)
586 .addReg(Base.getReg(), RegState::Implicit)
587 .addReg(Index.getReg(), RegState::Implicit);
590 .addReg(BaseReg)
591 .addReg(IndexReg);
618 .addReg(DestReg);
623 .addReg(DestReg)
650 .addReg(DestReg)
660 .addReg(0)
669 .addReg(DestReg)
lib/Target/X86/X86FixupSetCC.cpp 150 .addReg(ZeroReg)
151 .addReg(MI.getOperand(0).getReg())
lib/Target/X86/X86FlagsCopyLowering.cpp 770 BuildMI(MBB, Pos, Loc, TII->get(X86::TEST8rr)).addReg(Reg).addReg(Reg);
770 BuildMI(MBB, Pos, Loc, TII->get(X86::TEST8rr)).addReg(Reg).addReg(Reg);
821 .addReg(CondReg)
936 .addReg(Reg);
948 .addReg(Reg)
958 .addReg(Reg, 0, SubRegIdx[TargetRegSize]);
961 .addReg(Reg);
1005 .addReg(ZeroReg)
1006 .addReg(ExtCondReg);
1041 MIB.addReg(CondReg);
lib/Target/X86/X86FloatingPoint.cpp 240 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg);
250 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg);
847 I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0);
879 .addReg(STReg)
1359 I = BuildMI(*MBB, I, dl, TII->get(Opcode)).addReg(getSTReg(NotTOS));
lib/Target/X86/X86FrameLowering.cpp 279 .addReg(StackPtr)
280 .addReg(Reg);
293 .addReg(Rax, RegState::Kill)
305 .addReg(Rax)
306 .addReg(StackPtr);
310 BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax),
332 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub))
387 .addReg(StackPtr)
637 .addReg(X86::RCX);
641 .addReg(X86::RDX);
644 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX);
650 .addReg(ZeroReg, RegState::Undef)
651 .addReg(ZeroReg, RegState::Undef);
652 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), CopyReg).addReg(X86::RSP);
654 .addReg(CopyReg)
655 .addReg(SizeReg);
657 .addReg(TestReg)
658 .addReg(ZeroReg)
669 .addReg(0)
671 .addReg(0)
673 .addReg(X86::GS);
674 BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
674 BuildMI(&MBB, DL, TII.get(X86::CMP64rr)).addReg(FinalReg).addReg(LimitReg);
681 .addReg(FinalReg)
690 .addReg(LimitReg)
692 .addReg(ProbeReg)
702 .addReg(ProbeReg)
704 .addReg(0)
706 .addReg(0)
711 .addReg(RoundedReg)
712 .addReg(ProbeReg);
733 .addReg(X86::RSP)
734 .addReg(SizeReg);
791 CI = BuildMI(MBB, MBBI, DL, TII.get(CallOp)).addReg(X86::R11);
799 CI.addReg(AX, RegState::Implicit)
800 .addReg(SP, RegState::Implicit)
801 .addReg(AX, RegState::Define | RegState::Implicit)
802 .addReg(SP, RegState::Define | RegState::Implicit)
803 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
813 .addReg(SP)
814 .addReg(AX);
867 .addReg(Reg)
1089 .addReg(Establisher)
1111 .addReg(MachineFramePtr, RegState::Kill)
1139 .addReg(StackPtr)
1252 .addReg(X86::RAX, RegState::Kill)
1257 .addReg(X86::EAX, RegState::Kill)
1333 .addReg(Establisher)
1354 .addReg(SPOrEstablisher);
1380 .addReg(X86::ESP);
1424 .addReg(StackPtr)
1450 .addReg(SPOrEstablisher)
1458 .addReg(SPOrEstablisher)
1473 .addReg(FramePtr)
1708 .addReg(FramePtr);
2106 BuildMI(MBB, MI, DL, TII.get(Opc)).addReg(Reg, getKillRegState(CanKill))
2150 .addReg(X86::RIP)
2152 .addReg(0)
2154 .addReg(0);
2378 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::LEA64r : X86::LEA64_32r), ScratchReg).addReg(X86::RSP)
2379 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2379 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2381 BuildMI(checkMBB, DL, TII.get(IsLP64 ? X86::CMP64rm : X86::CMP32rm)).addReg(ScratchReg)
2382 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2382 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2382 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2405 BuildMI(checkMBB, DL, TII.get(X86::LEA32r), ScratchReg).addReg(X86::ESP)
2406 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2406 .addImm(1).addReg(0).addImm(-StackSize).addReg(0);
2410 BuildMI(checkMBB, DL, TII.get(X86::CMP32rm)).addReg(ScratchReg)
2411 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2411 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2411 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg);
2436 .addReg(ScratchReg2, RegState::Kill);
2441 .addReg(ScratchReg)
2442 .addReg(ScratchReg2).addImm(1).addReg(0)
2442 .addReg(ScratchReg2).addImm(1).addReg(0)
2444 .addReg(TlsReg);
2468 BuildMI(allocMBB, DL, TII.get(MOVrr), RegAX).addReg(Reg10);
2502 .addReg(X86::RIP)
2504 .addReg(0)
2506 .addReg(0);
2694 .addReg(ScratchReg), PReg, false, SPLimitOffset);
2703 .addReg(ScratchReg), PReg, false, SPLimitOffset);
2980 .addReg(FramePtr)
lib/Target/X86/X86ISelLowering.cpp29237 .addReg(X86::EAX);
29243 .addReg(mainDstReg).addMBB(mainMBB)
29244 .addReg(fallDstReg).addMBB(fallMBB);
29391 .addReg(OffsetReg)
29418 .addReg(OffsetReg)
29423 .addReg(OffsetReg64)
29424 .addReg(RegSaveReg);
29429 .addReg(OffsetReg)
29439 .addReg(NextOffsetReg)
29470 .addReg(OverflowAddrReg)
29474 .addReg(TmpReg)
29478 .addReg(OverflowAddrReg);
29485 .addReg(OverflowDestReg)
29495 .addReg(NextAddrReg)
29502 .addReg(OffsetDestReg).addMBB(offsetMBB)
29503 .addReg(OverflowDestReg).addMBB(overflowMBB);
29553 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
29553 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg);
29575 .addReg(/*IndexReg=*/0)
29577 .addReg(/*Segment=*/0)
29578 .addReg(MI.getOperand(i).getReg())
29701 .addReg(Op1Reg)
29703 .addReg(Op2Reg)
29849 .addReg(Op1Reg)
29851 .addReg(Op2Reg)
29856 MIB.addReg(FirstCMOV.getOperand(2).getReg()).addMBB(FirstInsertedMBB);
29861 .addReg(FirstCMOV.getOperand(0).getReg());
30072 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg);
30074 .addReg(tmpSPVReg).addReg(sizeVReg);
30074 .addReg(tmpSPVReg).addReg(sizeVReg);
30076 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
30076 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
30076 .addReg(0).addImm(1).addReg(0).addImm(TlsOffset).addReg(TlsReg)
30077 .addReg(SPLimitVReg);
30083 .addReg(SPLimitVReg);
30085 .addReg(SPLimitVReg);
30093 .addReg(sizeVReg);
30097 .addReg(X86::RDI, RegState::Implicit)
30098 .addReg(X86::RAX, RegState::ImplicitDefine);
30101 .addReg(sizeVReg);
30105 .addReg(X86::EDI, RegState::Implicit)
30106 .addReg(X86::EAX, RegState::ImplicitDefine);
30108 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg)
30110 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg);
30114 .addReg(X86::EAX, RegState::ImplicitDefine);
30118 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg)
30122 .addReg(IsLP64 ? X86::RAX : X86::EAX);
30134 .addReg(mallocPtrVReg)
30136 .addReg(bumpSPPtrVReg)
30247 .addReg(X86::RIP)
30249 .addReg(0)
30252 .addReg(0);
30255 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask);
30259 .addReg(0)
30261 .addReg(0)
30264 .addReg(0);
30267 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
30271 .addReg(TII->getGlobalBaseReg(F))
30273 .addReg(0)
30276 .addReg(0);
30279 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask);
30402 .addReg(CalleeVReg);
30406 .addReg(AvailableReg, RegState::Implicit | RegState::Kill);
30441 .addReg(ZReg, RegState::Undef)
30442 .addReg(ZReg, RegState::Undef);
30447 BuildMI(*MBB, MI, DL, TII->get(RdsspOpc), SSPCopyReg).addReg(ZReg);
30460 MIB.addReg(SSPCopyReg);
30544 .addReg(X86::RIP)
30546 .addReg(0)
30548 .addReg(0);
30552 .addReg(XII->getGlobalBaseReg(MF))
30554 .addReg(0)
30556 .addReg(0);
30569 MIB.addReg(LabelReg);
30595 .addReg(mainDstReg).addMBB(mainMBB)
30596 .addReg(restoreDstReg).addMBB(restoreMBB);
30691 .addReg(ZReg, RegState::Undef)
30692 .addReg(ZReg, RegState::Undef);
30697 BuildMI(checkSspMBB, DL, TII->get(RdsspOpc), SSPCopyReg).addReg(ZReg);
30703 .addReg(SSPCopyReg)
30704 .addReg(SSPCopyReg);
30721 MIB.addReg(MO.getReg());
30731 .addReg(PrevSSPReg)
30732 .addReg(SSPCopyReg);
30744 .addReg(SspSubReg)
30749 BuildMI(fixShadowMBB, DL, TII->get(IncsspOpc)).addReg(SspFirstShrReg);
30754 .addReg(SspFirstShrReg)
30766 .addReg(SspSecondShrReg);
30780 .addReg(SspAfterShlReg)
30782 .addReg(DecReg)
30786 BuildMI(fixShadowLoopMBB, DL, TII->get(IncsspOpc)).addReg(Value128InReg);
30790 BuildMI(fixShadowLoopMBB, DL, TII->get(DecROpc), DecReg).addReg(CounterReg);
30845 MIB.addReg(MO.getReg());
30859 MIB.addReg(MO.getReg());
30877 BuildMI(*thisMBB, MI, DL, TII->get(IJmpOpc)).addReg(Tmp);
30911 .addReg(X86::RIP)
30913 .addReg(0)
30915 .addReg(0);
30918 .addReg(0) /* TII->getGlobalBaseReg(MF) */
30920 .addReg(0)
30922 .addReg(0);
30930 MIB.addReg(VR);
31036 .addReg(IReg)
31046 .addReg(X86::RIP)
31048 .addReg(0)
31050 .addReg(0);
31054 .addReg(IReg)
31061 .addReg(BReg)
31063 .addReg(IReg64)
31065 .addReg(0);
31074 .addReg(BReg)
31076 .addReg(IReg64)
31078 .addReg(0);
31080 BuildMI(DispContBB, DL, TII->get(X86::MOVSX64rr32), OReg64).addReg(OReg);
31083 .addReg(OReg64)
31084 .addReg(BReg);
31086 BuildMI(DispContBB, DL, TII->get(X86::JMP64r)).addReg(TReg);
31095 .addReg(0)
31097 .addReg(IReg)
31099 .addReg(0);
31144 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead);
31241 BuildMI(*BB, MI, DL, TII->get(Push)).addReg(MI.getOperand(0).getReg());
31271 .addReg(OldCW, RegState::Kill).addImm(0xC00);
31277 .addReg(NewCW, RegState::Kill, X86::sub_16bit);
31283 .addReg(NewCW16, RegState::Kill);
31306 .addReg(MI.getOperand(X86::AddrNumOperands).getReg());
46203 .addReg(*I);
46209 .addReg(NewVR);
lib/Target/X86/X86InsertPrefetch.cpp 225 MIB.addReg(Current->getOperand(MemOpOffset + X86::AddrBaseReg).getReg())
228 .addReg(
232 .addReg(Current->getOperand(MemOpOffset + X86::AddrSegmentReg)
lib/Target/X86/X86InstrBuilder.h 127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
127 return MIB.addReg(Reg).addImm(1).addReg(0).addImm(0).addReg(0);
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
144 return MIB.addImm(1).addReg(0).addImm(Offset).addReg(0);
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0);
149 return MIB.addImm(1).addReg(0).add(Offset).addReg(0);
159 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset);
167 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1)
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
168 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0);
177 MIB.addReg(AM.Base.Reg);
183 MIB.addImm(AM.Scale).addReg(AM.IndexReg);
189 return MIB.addReg(0);
226 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
226 return MIB.addReg(GlobalBaseReg).addImm(1).addReg(0)
227 .addConstantPoolIndex(CPI, 0, OpFlags).addReg(0);
lib/Target/X86/X86InstrInfo.cpp 746 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
800 .addReg(InRegLEA, RegState::Define, SubReg)
801 .addReg(Src, getKillRegState(IsKill));
810 MIB.addReg(0).addImm(1ULL << ShAmt)
811 .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
811 .addReg(InRegLEA, RegState::Kill).addImm(0).addReg(0);
852 .addReg(InRegLEA2, RegState::Define, SubReg)
853 .addReg(Src2, getKillRegState(IsKill2));
865 .addReg(Dest, RegState::Define | getDeadRegState(IsDead))
866 .addReg(OutRegLEA, RegState::Kill, SubReg);
935 .addReg(0)
939 .addReg(0);
960 .addReg(0)
962 .addReg(SrcReg, getKillRegState(isKill))
964 .addReg(0);
996 .addReg(SrcReg, getKillRegState(isKill));
1018 .addReg(SrcReg, getKillRegState(isKill));
1102 .addReg(SrcReg, getKillRegState(isKill));
1143 .addReg(SrcReg, getKillRegState(isKill));
2474 MIB.addReg(C.first, RegState::Implicit);
2475 MIB.addReg(C.first, RegState::Implicit | RegState::Define);
2877 .addReg(FalseReg)
2878 .addReg(TrueReg)
3032 .addReg(SrcReg, getKillRegState(KillSrc));
3258 .addReg(SrcReg, getKillRegState(isKill));
3885 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3885 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3902 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3902 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3914 .addReg(Reg, RegState::Undef)
3915 .addReg(Reg, RegState::Undef);
3919 MIB.addReg(Reg);
3996 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
3997 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
3997 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4001 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4001 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4001 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4012 MIB.addReg(TRI->getFrameRegister(MF), RegState::Undef);
4070 MIB.addReg(MIB->getOperand(1).getReg(),
4112 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4141 MIB.addReg(SrcReg, RegState::ImplicitDefine);
4160 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4160 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xf);
4168 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4168 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef)
4169 .addReg(Reg, RegState::Undef).addImm(0xff);
4183 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4183 MIB.addReg(Reg, RegState::Undef).addReg(MaskReg, MaskState)
4184 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4184 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef).addImm(0xff);
4216 MIB.addReg(Reg, RegState::ImplicitDefine);
4579 .addReg(Reg, RegState::Undef)
4580 .addReg(Reg, RegState::Undef);
4587 .addReg(XReg, RegState::Undef)
4588 .addReg(XReg, RegState::Undef)
4589 .addReg(Reg, RegState::ImplicitDefine);
4596 .addReg(XReg, RegState::Undef)
4597 .addReg(XReg, RegState::Undef)
4598 .addReg(Reg, RegState::ImplicitDefine);
4602 .addReg(Reg, RegState::Undef)
4603 .addReg(Reg, RegState::Undef);
5531 MIB.addReg(Reg, RegState::Define);
5535 MIB.addReg(Reg);
5539 MIB.addReg(ImpOp.getReg(),
5588 MIB.addReg(Reg, RegState::Kill);
7777 .addReg(X86::RIP)
7779 .addReg(0)
7781 .addReg(0);
7792 .addReg(X86::RIP)
7794 .addReg(0)
7796 .addReg(0);
7802 .addReg(PBReg, RegState::Kill)
7803 .addReg(GOTReg, RegState::Kill);
7818 .addReg(PC)
7909 .addReg(TLSBaseAddrReg);
7936 .addReg(is64Bit ? X86::RAX : X86::EAX);
lib/Target/X86/X86InstructionSelector.cpp 257 .addReg(SrcReg)
580 MIB.addImm(0).addReg(0);
831 .addReg(SrcReg);
838 .addReg(TransitRegFrom)
866 .addReg(SrcReg)
872 .addReg(DefReg)
929 .addReg(SrcReg)
974 .addReg(LHS)
975 .addReg(RHS);
1034 .addReg(LhsReg)
1035 .addReg(RhsReg);
1045 .addReg(FlagReg1)
1046 .addReg(FlagReg2);
1067 .addReg(LhsReg)
1068 .addReg(RhsReg);
1106 .addReg(CarryInReg);
1123 .addReg(Op0Reg)
1124 .addReg(Op1Reg);
1127 .addReg(X86::EFLAGS);
1227 .addReg(SrcReg, 0, SubIdx);
1264 .addReg(DstReg, RegState::DefineNoRead, SubIdx)
1265 .addReg(SrcReg);
1342 .addReg(SrcReg)
1381 .addReg(DefReg)
1382 .addReg(I.getOperand(Idx).getReg())
1393 .addReg(DefReg);
1412 .addReg(CondReg)
1645 .addReg(Op1Reg);
1662 .addReg(Zero32, 0, X86::sub_16bit);
1666 .addReg(Zero32);
1671 .addReg(Zero32)
1678 .addReg(Op2Reg);
1693 .addReg(X86::AX);
1698 .addReg(SourceSuperReg)
1706 .addReg(ResultSuperReg)
1711 .addReg(OpEntry.DivRemResultReg);
lib/Target/X86/X86RetpolineThunks.cpp 234 .addReg(Reg);
lib/Target/X86/X86SpeculativeLoadHardening.cpp 492 .addReg(PredStateSubReg)
758 .addReg(CurStateReg)
759 .addReg(PS->PoisonReg)
1119 .addReg(/*Base*/ X86::RIP)
1121 .addReg(/*Index*/ 0)
1123 .addReg(/*Segment*/ 0);
1149 .addReg(TargetReg, RegState::Kill)
1159 .addReg(/*Base*/ X86::RIP)
1161 .addReg(/*Index*/ 0)
1163 .addReg(/*Segment*/ 0);
1168 .addReg(TargetReg, RegState::Kill)
1169 .addReg(AddrReg, RegState::Kill);
1181 .addReg(PS->InitialReg)
1182 .addReg(PS->PoisonReg)
1884 BuildMI(MBB, InsertPt, Loc, TII->get(X86::COPY), Reg).addReg(X86::EFLAGS);
1897 BuildMI(MBB, InsertPt, Loc, TII->get(X86::COPY), X86::EFLAGS).addReg(Reg);
1913 .addReg(PredStateReg, RegState::Kill)
1918 .addReg(X86::RSP)
1919 .addReg(TmpReg, RegState::Kill);
1935 .addReg(X86::RSP);
1938 .addReg(TmpReg, RegState::Kill)
2051 .addReg(StateReg);
2062 .addReg(VStateReg);
2072 .addReg(VBStateReg)
2073 .addReg(OpReg);
2093 .addReg(StateReg);
2103 .addReg(VStateReg)
2104 .addReg(OpReg);
2116 .addReg(StateReg)
2117 .addReg(OpReg);
2126 .addReg(OpReg)
2127 .addReg(StateReg);
2297 .addReg(StateReg, 0, SubRegImm);
2309 .addReg(StateReg)
2310 .addReg(Reg);
2503 .addReg(/*Base*/ X86::RIP)
2505 .addReg(/*Index*/ 0)
2507 .addReg(/*Segment*/ 0);
2521 .addReg(/*Base*/ X86::RSP)
2523 .addReg(/*Index*/ 0)
2526 .addReg(/*Segment*/ 0);
2540 .addReg(ExpectedRetAddrReg, RegState::Kill)
2545 .addReg(/*Base*/ X86::RIP)
2547 .addReg(/*Index*/ 0)
2549 .addReg(/*Segment*/ 0);
2551 .addReg(ExpectedRetAddrReg, RegState::Kill)
2552 .addReg(ActualRetAddrReg, RegState::Kill);
2562 .addReg(NewStateReg, RegState::Kill)
2563 .addReg(PS->PoisonReg)
lib/Target/X86/X86WinAllocaExpander.cpp 221 .addReg(RegA, RegState::Undef);
235 .addReg(RegA, RegState::Undef);
240 .addReg(StackPtr)
249 .addReg(MI->getOperand(0).getReg());
258 .addReg(StackPtr)
259 .addReg(MI->getOperand(0).getReg());
lib/Target/XCore/XCoreFrameLowering.cpp 290 .addReg(SpillList[i].Reg, RegState::Kill)
372 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(EhStackReg);
373 BuildMI(MBB, MBBI, dl, TII.get(XCore::BAU_1r)).addReg(EhHandlerReg);
386 BuildMI(MBB, MBBI, dl, TII.get(XCore::SETSP_1r)).addReg(FramePtr);
lib/Target/XCore/XCoreISelLowering.cpp 1560 .addReg(MI.getOperand(1).getReg())
1576 .addReg(MI.getOperand(3).getReg())
1578 .addReg(MI.getOperand(2).getReg())
lib/Target/XCore/XCoreInstrInfo.cpp 290 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
299 BuildMI(&MBB, DL, get(Opc)).addReg(Cond[1].getReg())
340 .addReg(SrcReg, getKillRegState(KillSrc))
352 .addReg(SrcReg, getKillRegState(KillSrc));
375 .addReg(SrcReg, getKillRegState(isKill))
lib/Target/XCore/XCoreRegisterInfo.cpp 71 .addReg(FrameReg)
77 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
78 .addReg(FrameReg)
84 .addReg(FrameReg)
107 .addReg(FrameReg)
108 .addReg(ScratchOffset, RegState::Kill)
113 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
114 .addReg(FrameReg)
115 .addReg(ScratchOffset, RegState::Kill)
120 .addReg(FrameReg)
121 .addReg(ScratchOffset, RegState::Kill);
147 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
184 .addReg(ScratchBase, RegState::Kill)
185 .addReg(ScratchOffset, RegState::Kill)
190 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill()))
191 .addReg(ScratchBase, RegState::Kill)
192 .addReg(ScratchOffset, RegState::Kill)
197 .addReg(ScratchBase, RegState::Kill)
198 .addReg(ScratchOffset, RegState::Kill);
tools/llvm-exegesis/lib/Assembler.cpp 106 Builder.addReg(Op.getReg(), Flags);