|
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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
lib/CodeGen/GlobalISel/IRTranslator.cpp 2073 MIB.addMBB(Pred);
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 2749 MIB.addMBB(&OpMBB);
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 262 return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
365 return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
lib/CodeGen/ImplicitNullChecks.cpp 639 .addMBB(HandlerMBB)
lib/CodeGen/MachineSSAUpdater.cpp 194 InsertedPHI.addReg(PredValues[i].second).addMBB(PredValues[i].first);
316 MachineInstrBuilder(*Pred->getParent(), PHI).addReg(Val).addMBB(Pred);
lib/CodeGen/ModuloSchedule.cpp 553 NewPhi.addReg(PhiOp1).addMBB(BB1);
554 NewPhi.addReg(PhiOp2).addMBB(BB2);
669 NewPhi.addReg(PhiOp1).addMBB(BB1);
670 NewPhi.addReg(PhiOp2).addMBB(BB2);
1439 .addMBB(PreheaderBB) // Block choice is arbitrary and has no effect.
1441 .addMBB(BB); // Block choice is arbitrary and has no effect.
1488 .addMBB(PreheaderBB)
1490 .addMBB(BB);
1691 .addMBB(BB);
lib/CodeGen/PeepholeOptimizer.cpp 772 MIB.addMBB(OrigPHI.getOperand(MBBOpIdx).getMBB());
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 405 MIB.addMBB(BBNode->getBasicBlock());
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 1712 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB);
1840 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(BTB.Parent);
1843 .addMBB(BTB.Cases.back().ThisBB);
1851 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB);
1893 .addMBB(SDB->SL->JTCases[i].first.HeaderBB);
1896 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB);
1943 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB);
lib/CodeGen/SwiftErrorValueTracking.cpp 248 PHI.addReg(BBRegPair.second).addMBB(BBRegPair.first);
lib/CodeGen/TailDuplicator.cpp 517 MIB.addReg(SrcReg).addMBB(SrcBB);
529 MIB.addReg(Reg).addMBB(SrcBB);
lib/Target/AArch64/AArch64CondBrTuning.cpp 139 .addMBB(TargetMBB);
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 211 .addMBB(DoneBB)
224 .addMBB(LoadCmpBB);
304 .addMBB(DoneBB);
317 .addMBB(LoadCmpBB);
375 BuildMI(LoopBB, DL, TII->get(AArch64::CBNZX)).addUse(SizeReg).addMBB(LoopBB);
lib/Target/AArch64/AArch64FastISel.cpp 2414 MIB.addMBB(TBB);
2482 .addMBB(TBB);
2488 .addMBB(TBB);
2497 .addMBB(Target);
2519 .addMBB(TBB);
2544 .addMBB(TBB);
lib/Target/AArch64/AArch64ISelLowering.cpp 1358 BuildMI(MBB, DL, TII->get(AArch64::Bcc)).addImm(CondCode).addMBB(TrueBB);
1359 BuildMI(MBB, DL, TII->get(AArch64::B)).addMBB(EndBB);
1373 .addMBB(TrueBB)
1375 .addMBB(MBB);
lib/Target/AArch64/AArch64InstrInfo.cpp 376 BuildMI(&MBB, DL, get(AArch64::Bcc)).addImm(Cond[0].getImm()).addMBB(TBB);
384 MIB.addMBB(TBB);
396 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(TBB);
408 BuildMI(&MBB, DL, get(AArch64::B)).addMBB(FBB);
1492 .addMBB(TargetMBB);
1496 .addMBB(TargetMBB)
4838 .addMBB(TBB);
4875 BuildMI(RefToMBB, MI, DL, get(AArch64::Bcc)).addImm(CC).addMBB(TBB);
lib/Target/AArch64/AArch64InstructionSelector.cpp 978 MIB.buildInstr(AArch64::Bcc, {}, {}).addImm(CC).addMBB(DestMBB);
1002 .addMBB(DestMBB)
1419 .addMBB(DestMBB);
1432 .addMBB(DestMBB);
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 1594 .addMBB(I.getOperand(1).getMBB());
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 2123 .addMBB(BrCond->getOperand(1).getMBB());
2143 .addMBB(BrCond->getOperand(1).getMBB());
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 1489 MIB.addMBB(SourceMBB);
1501 MIB.addMBB(SourcePred);
1533 MIB.addMBB(LastMerge);
1543 MIB.addMBB(SourcePred);
1582 MIB.addMBB(IfMBB);
1593 MIB.addMBB(SourcePred);
1776 MIB.addMBB(IfBB);
1778 MIB.addMBB(CodeBB);
2182 BackedgePHI.addMBB(getPHIPred(*PHIDefInstr, 0));
2184 BackedgePHI.addMBB((*SRI).second);
2196 MIB.addMBB((*SRI).second);
2205 MIB.addMBB(Exit);
2459 MIB.addMBB(Entry);
2463 MIB.addMBB(RegionSourceMBB);
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 735 .addMBB(&MBB)
737 .addMBB(LoopBB);
743 .addMBB(&MBB)
745 .addMBB(LoopBB);
939 .addMBB(LoopBB);
lib/Target/AMDGPU/R600InstrInfo.cpp 767 BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(TBB);
776 .addMBB(TBB)
791 .addMBB(TBB)
793 BuildMI(&MBB, DL, get(R600::JUMP)).addMBB(FBB);
lib/Target/AMDGPU/SIISelLowering.cpp 3154 .addMBB(LoopBB);
3191 .addMBB(&OrigBB)
3193 .addMBB(&LoopBB);
3197 .addMBB(&OrigBB)
3199 .addMBB(&LoopBB);
3260 .addMBB(&LoopBB);
lib/Target/AMDGPU/SIInsertSkips.cpp 163 .addMBB(&NextBB);
332 .addMBB(DestBB);
521 .addMBB(EmptyMBBAtEnd);
lib/Target/AMDGPU/SIInstrInfo.cpp 1795 .addMBB(&DestBB, MO_LONG_BRANCH_FORWARD);
1805 .addMBB(&DestBB, MO_LONG_BRANCH_BACKWARD);
2053 .addMBB(TBB);
2062 .addMBB(TBB);
2075 .addMBB(TBB);
2089 .addMBB(TBB);
2091 .addMBB(FBB);
4397 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::S_CBRANCH_EXECNZ)).addMBB(&LoopBB);
6118 HeaderPHIBuilder.addMBB(*PI);
6128 .addMBB(LoopEntry);
lib/Target/AMDGPU/SILowerControlFlow.cpp 327 .addMBB(DestBB);
lib/Target/ARC/ARCBranchFinalize.cpp 119 .addMBB(MI->getOperand(0).getMBB())
137 .addMBB(MI->getOperand(0).getMBB())
lib/Target/ARC/ARCInstrInfo.cpp 383 BuildMI(&MBB, dl, get(ARC::BR)).addMBB(TBB);
388 MIB.addMBB(TBB);
399 BuildMI(&MBB, dl, get(ARC::BR)).addMBB(FBB);
lib/Target/ARM/ARMBaseInstrInfo.cpp 452 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).add(predOps(ARMCC::AL));
454 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
457 .addMBB(TBB)
465 .addMBB(TBB)
469 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).add(predOps(ARMCC::AL));
471 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
lib/Target/ARM/ARMConstantIslandPass.cpp 911 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
914 .addMBB(NewBB)
1297 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
1300 .addMBB(NewMBB)
1718 .addMBB(NextBB).addImm(CC).addReg(CCReg);
1723 .addMBB(DestBB)
1726 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
1975 .addMBB(DestBB, Br.MI->getOperand(0).getTargetFlags());
2438 .addMBB(BB)
2442 .addMBB(BB)
lib/Target/ARM/ARMExpandPseudoInsts.cpp 981 .addMBB(DoneBB)
1004 .addMBB(LoadCmpBB)
1102 .addMBB(DoneBB)
1124 .addMBB(LoadCmpBB)
lib/Target/ARM/ARMFastISel.cpp 1267 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR);
1290 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
1328 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR);
lib/Target/ARM/ARMFrameLowering.cpp 2457 BuildMI(GetMBB, DL, TII.get(Opcode)).addMBB(PostStackMBB)
lib/Target/ARM/ARMISelLowering.cpp 9606 .addMBB(TrapBB)
9663 .addMBB(TrapBB)
9765 .addMBB(TrapBB)
10187 .addReg(varLoop).addMBB(loopMBB)
10188 .addReg(varEnd).addMBB(entryBB);
10190 .addReg(srcLoop).addMBB(loopMBB)
10191 .addReg(src).addMBB(entryBB);
10193 .addReg(destLoop).addMBB(loopMBB)
10194 .addReg(dest).addMBB(entryBB);
10224 .addMBB(loopMBB).addImm(ARMCC::NE).addReg(ARM::CPSR);
10353 .addMBB(TrapBB)
10514 .addMBB(sinkMBB)
10532 .addMBB(copy0MBB)
10534 .addMBB(thisMBB);
10577 .addMBB(destMBB).addImm(ARMCC::EQ).addReg(ARM::CPSR);
10580 .addMBB(exitMBB)
10583 BuildMI(BB, dl, TII->get(ARM::B)) .addMBB(exitMBB);
10651 TII->get(isThumb2 ? ARM::t2Bcc : ARM::Bcc)).addMBB(SinkBB)
10668 .addReg(NewRsbDstReg).addMBB(RSBBB)
10669 .addReg(ABSSrcReg).addMBB(BB);
lib/Target/AVR/AVRISelLowering.cpp 1530 BuildMI(BB, dl, TII.get(AVR::BREQk)).addMBB(RemBB);
1539 .addMBB(BB)
1541 .addMBB(LoopBB);
1544 .addMBB(BB)
1546 .addMBB(LoopBB);
1555 BuildMI(LoopBB, dl, TII.get(AVR::BRNEk)).addMBB(LoopBB);
1561 .addMBB(BB)
1563 .addMBB(LoopBB);
1643 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(FallThrough);
1663 BuildMI(MBB, dl, TII.getBrCond(CC)).addMBB(trueMBB);
1664 BuildMI(MBB, dl, TII.get(AVR::RJMPk)).addMBB(falseMBB);
1669 BuildMI(falseMBB, dl, TII.get(AVR::RJMPk)).addMBB(trueMBB);
1675 .addMBB(MBB)
1677 .addMBB(falseMBB) ;
lib/Target/AVR/AVRInstrInfo.cpp 356 .addMBB(UnCondBrIter->getOperand(0).getMBB());
358 .addMBB(TargetBB);
413 auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(TBB);
422 auto &CondMI = *BuildMI(&MBB, DL, getBrCond(CC)).addMBB(TBB);
429 auto &MI = *BuildMI(&MBB, DL, get(AVR::RJMPk)).addMBB(FBB);
568 auto &MI = *BuildMI(&MBB, DL, get(AVR::JMPk)).addMBB(&NewDestBB);
lib/Target/BPF/BPFISelLowering.cpp 723 BuildMI(BB, DL, TII.get(NewCC)).addReg(LHS).addReg(RHS).addMBB(Copy1MBB);
729 .addReg(LHS).addImm(imm32).addMBB(Copy1MBB);
746 .addMBB(Copy0MBB)
748 .addMBB(ThisMBB);
lib/Target/BPF/BPFInstrInfo.cpp 233 BuildMI(&MBB, DL, get(BPF::JMP)).addMBB(TBB);
lib/Target/Hexagon/HexagonBitSimplify.cpp 3074 .addMBB(&PB)
3076 .addMBB(&LB);
lib/Target/Hexagon/HexagonConstPropagation.cpp 3153 .addMBB(TargetB);
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 745 .addMBB(TB);
909 .addMBB(FP.JoinB);
916 .addMBB(TSB);
926 MIB.addMBB(FSB);
935 .addMBB(SSB);
lib/Target/Hexagon/HexagonHardwareLoops.cpp 1251 BuildMI(*Preheader, InsertPos, DL, TII->get(LOOP_r)).addMBB(LoopStart)
1264 .addMBB(LoopStart).addReg(CountReg);
1267 .addMBB(LoopStart).addImm(CountImm);
1280 BuildMI(*LastMBB, LastI, LastIDL, TII->get(ENDLOOP)).addMBB(LoopStart);
lib/Target/Hexagon/HexagonInstrInfo.cpp 612 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
624 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
636 addReg(Cond[2].getReg(), Flags2).addMBB(TBB);
639 addImm(Cond[2].getImm()).addMBB(TBB);
646 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
666 BuildMI(&MBB, DL, get(EndLoopOp)).addMBB(TBB);
670 BuildMI(&MBB, DL, get(BccOpc)).addReg(RO.getReg(), Flags).addMBB(TBB);
672 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
lib/Target/Hexagon/HexagonNewValueJump.cpp 695 .addMBB(jmpTarget);
701 .addMBB(jmpTarget);
lib/Target/Lanai/LanaiInstrInfo.cpp 673 BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(TrueBlock);
681 BuildMI(&MBB, DL, get(Lanai::BRCC)).addMBB(TrueBlock).addImm(ConditionalCode);
688 BuildMI(&MBB, DL, get(Lanai::BT)).addMBB(FalseBlock);
lib/Target/MSP430/MSP430BranchSelector.cpp 197 .addMBB(NextMBB)
204 MI = BuildMI(*MBB, MI, dl, TII->get(MSP430::Bi)).addMBB(DestBB);
lib/Target/MSP430/MSP430ISelLowering.cpp 1499 .addMBB(RemBB)
1508 .addReg(SrcReg).addMBB(BB)
1509 .addReg(ShiftReg2).addMBB(LoopBB);
1511 .addReg(ShiftAmtSrcReg).addMBB(BB)
1512 .addReg(ShiftAmtReg2).addMBB(LoopBB);
1526 .addMBB(LoopBB)
1532 .addReg(SrcReg).addMBB(BB)
1533 .addReg(ShiftReg2).addMBB(LoopBB);
1585 .addMBB(copy1MBB)
1602 .addMBB(copy0MBB)
1604 .addMBB(thisMBB);
lib/Target/MSP430/MSP430InstrInfo.cpp 280 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(TBB);
286 BuildMI(&MBB, DL, get(MSP430::JCC)).addMBB(TBB).addImm(Cond[0].getImm());
291 BuildMI(&MBB, DL, get(MSP430::JMP)).addMBB(FBB);
lib/Target/Mips/Mips16ISelLowering.cpp 548 .addMBB(sinkMBB);
565 .addMBB(thisMBB)
567 .addMBB(copy0MBB);
612 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
629 .addMBB(thisMBB)
631 .addMBB(copy0MBB);
678 BuildMI(BB, DL, TII->get(Opc1)).addMBB(sinkMBB);
695 .addMBB(thisMBB)
697 .addMBB(copy0MBB);
717 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
740 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(BtOpc)).addMBB(target);
lib/Target/Mips/MipsBranchExpansion.cpp 353 MIB.addMBB(MBBOpnd);
481 .addMBB(TgtMBB, MipsII::MO_ABS_HI)
482 .addMBB(BalTgtMBB);
485 BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
489 .addMBB(TgtMBB, MipsII::MO_ABS_LO)
490 .addMBB(BalTgtMBB);
589 .addMBB(TgtMBB, MipsII::MO_ABS_HI)
590 .addMBB(BalTgtMBB);
596 BuildMI(*MFp, DL, TII->get(BalOp)).addMBB(BalTgtMBB);
600 .addMBB(TgtMBB, MipsII::MO_ABS_LO)
601 .addMBB(BalTgtMBB);
658 .addMBB(TgtMBB);
667 .append(BuildMI(*MFp, DL, TII->get(Mips::J)).addMBB(TgtMBB))
678 .addMBB(TgtMBB, MipsII::MO_HIGHEST);
682 .addMBB(TgtMBB, MipsII::MO_HIGHER);
689 .addMBB(TgtMBB, MipsII::MO_ABS_HI);
696 .addMBB(TgtMBB, MipsII::MO_ABS_LO);
700 .addMBB(TgtMBB, MipsII::MO_ABS_HI);
704 .addMBB(TgtMBB, MipsII::MO_ABS_LO);
lib/Target/Mips/MipsConstantIslandPass.cpp 866 BuildMI(OrigBB, DebugLoc(), TII->get(Mips::Bimm16)).addMBB(NewBB);
1239 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
1620 .addMBB(NextBB);
1623 .addMBB(NextBB);
1627 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
lib/Target/Mips/MipsExpandPseudo.cpp 150 .addReg(Scratch2).addReg(ShiftCmpVal).addMBB(sinkMBB);
170 .addMBB(loop1MBB);
280 .addReg(Dest, RegState::Kill).addReg(OldVal).addMBB(exitMBB);
290 .addReg(Scratch, RegState::Kill).addReg(ZERO).addMBB(loop1MBB);
445 .addReg(StoreVal).addReg(Mips::ZERO).addMBB(loopMBB);
608 BuildMI(loopMBB, DL, TII->get(BEQ)).addReg(Scratch).addReg(ZERO).addMBB(loopMBB);
lib/Target/Mips/MipsFastISel.cpp 981 .addMBB(TBB);
lib/Target/Mips/MipsISelLowering.cpp 4459 .addMBB(sinkMBB);
4465 .addMBB(sinkMBB);
4483 .addMBB(thisMBB)
4485 .addMBB(copy0MBB);
4535 .addMBB(sinkMBB);
4553 .addMBB(thisMBB)
4555 .addMBB(copy0MBB);
4558 .addMBB(thisMBB)
4560 .addMBB(copy0MBB);
lib/Target/Mips/MipsInstrInfo.cpp 117 MIB.addMBB(TBB);
141 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(FBB);
148 BuildMI(&MBB, DL, get(UncondBrOpc)).addMBB(TBB);
lib/Target/Mips/MipsSEISelLowering.cpp 3062 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
3064 BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
3070 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3081 .addMBB(FBB)
3083 .addMBB(TBB);
3133 .addMBB(TBB);
3139 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3150 .addMBB(FBB)
3152 .addMBB(TBB);
lib/Target/NVPTX/NVPTXInstrInfo.cpp 196 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
199 .addMBB(TBB);
204 BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
205 BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
lib/Target/PowerPC/PPCBranchSelector.cpp 363 I = BuildMI(MBB, I, dl, TII->get(PPC::B)).addMBB(Dest);
lib/Target/PowerPC/PPCExpandISEL.cpp 423 .addMBB(IsTrueBlockRequired ? TrueBlock : Successor);
429 .addMBB(Successor);
lib/Target/PowerPC/PPCFastISel.cpp 798 .addReg(CondReg).addMBB(TBB);
lib/Target/PowerPC/PPCISelLowering.cpp10398 .addImm(CmpPred).addReg(PPC::CR0).addMBB(exitMBB);
10406 .addImm(PPC::PRED_NE).addReg(PPC::CR0).addMBB(loopMBB);
10583 .addMBB(exitMBB);
10596 .addMBB(loopMBB);
10706 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::BCLalways)).addMBB(mainMBB);
10712 .addMBB(mainMBB);
10713 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PPC::B)).addMBB(sinkMBB);
10744 .addReg(mainDstReg).addMBB(mainMBB)
10745 .addReg(restoreDstReg).addMBB(thisMBB);
10970 .addMBB(sinkMBB);
10976 .addMBB(sinkMBB);
10993 .addMBB(copy0MBB)
10995 .addMBB(thisMBB);
11040 .addMBB(readMBB);
11217 .addMBB(midMBB);
11229 .addMBB(loop1MBB);
11230 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
11394 .addMBB(midMBB);
11412 .addMBB(loop1MBB);
11413 BuildMI(BB, dl, TII->get(PPC::B)).addMBB(exitMBB);
lib/Target/PowerPC/PPCInstrInfo.cpp 719 BuildMI(&MBB, DL, get(PPC::B)).addMBB(TBB);
723 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
725 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
727 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
732 .addMBB(TBB);
740 (isPPC64 ? PPC::BDZ8 : PPC::BDZ))).addMBB(TBB);
742 BuildMI(&MBB, DL, get(PPC::BC)).add(Cond[1]).addMBB(TBB);
744 BuildMI(&MBB, DL, get(PPC::BCn)).add(Cond[1]).addMBB(TBB);
749 .addMBB(TBB);
750 BuildMI(&MBB, DL, get(PPC::B)).addMBB(FBB);
1471 .addMBB(MBB);
1479 .addMBB(MBB);
1488 .addMBB(MBB);
lib/Target/PowerPC/PPCMIPeephole.cpp 1299 .addReg(BI1->getOperand(1).getReg()).addMBB(MBB1)
1300 .addReg(BI2->getOperand(1).getReg()).addMBB(MBBtoMoveCmp);
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 99 MIB.addReg(MI.getOperand(i - 1).getReg()).addMBB(NewMBB);
222 .addMBB(NewBRTarget);
225 .addMBB(NewMBB);
lib/Target/RISCV/RISCVExpandPseudoInsts.cpp 270 .addMBB(LoopMBB);
355 .addMBB(LoopMBB);
473 .addMBB(LoopTailMBB);
481 .addMBB(LoopTailMBB);
488 .addMBB(LoopTailMBB);
494 .addMBB(LoopTailMBB);
514 .addMBB(LoopHeadMBB);
569 .addMBB(DoneMBB);
579 .addMBB(LoopHeadMBB);
594 .addMBB(DoneMBB);
610 .addMBB(LoopHeadMBB);
647 .addMBB(NewMBB, RISCVII::MO_PCREL_LO);
lib/Target/RISCV/RISCVISelLowering.cpp 1141 .addMBB(LoopMBB);
1321 .addMBB(TailMBB);
1337 .addMBB(HeadMBB)
1339 .addMBB(IfFalseMBB);
lib/Target/RISCV/RISCVInstrInfo.cpp 348 MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(TBB);
357 *BuildMI(&MBB, DL, get(Opc)).add(Cond[1]).add(Cond[2]).addMBB(TBB);
366 MachineInstr &MI = *BuildMI(&MBB, DL, get(RISCV::PseudoBR)).addMBB(FBB);
400 .addMBB(&DestBB, RISCVII::MO_HI);
403 .addMBB(&DestBB, RISCVII::MO_LO);
lib/Target/Sparc/SparcISelLowering.cpp 3154 .addMBB(SinkMBB)
3164 .addMBB(ThisMBB)
3166 .addMBB(IfFalseMBB);
lib/Target/Sparc/SparcInstrInfo.cpp 255 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
263 BuildMI(&MBB, DL, get(SP::BCOND)).addMBB(TBB).addImm(CC);
265 BuildMI(&MBB, DL, get(SP::FBCOND)).addMBB(TBB).addImm(CC);
269 BuildMI(&MBB, DL, get(SP::BA)).addMBB(FBB);
lib/Target/SystemZ/SystemZISelLowering.cpp 6607 .addReg(TrueReg).addMBB(TrueMBB)
6608 .addReg(FalseReg).addMBB(FalseMBB);
6685 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
6779 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
6869 .addReg(OrigVal).addMBB(StartMBB)
6870 .addReg(Dest).addMBB(LoopMBB);
6910 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
6986 .addReg(OrigVal).addMBB(StartMBB)
6987 .addReg(Dest).addMBB(UpdateMBB);
6994 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
7017 .addReg(RotatedOldVal).addMBB(LoopMBB)
7018 .addReg(RotatedAltVal).addMBB(UseAltMBB);
7028 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
7108 .addReg(OrigOldVal).addMBB(StartMBB)
7109 .addReg(RetryOldVal).addMBB(SetMBB);
7111 .addReg(OrigCmpVal).addMBB(StartMBB)
7112 .addReg(RetryCmpVal).addMBB(SetMBB);
7114 .addReg(OrigSwapVal).addMBB(StartMBB)
7115 .addReg(RetrySwapVal).addMBB(SetMBB);
7124 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
7148 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
7286 .addReg(StartDestReg).addMBB(StartMBB)
7287 .addReg(NextDestReg).addMBB(NextMBB);
7290 .addReg(StartSrcReg).addMBB(StartMBB)
7291 .addReg(NextSrcReg).addMBB(NextMBB);
7293 .addReg(StartCountReg).addMBB(StartMBB)
7294 .addReg(NextCountReg).addMBB(NextMBB);
7305 .addMBB(EndMBB);
7332 .addMBB(LoopMBB);
7384 .addMBB(EndMBB);
7440 .addReg(Start1Reg).addMBB(StartMBB)
7441 .addReg(End1Reg).addMBB(LoopMBB);
7443 .addReg(Start2Reg).addMBB(StartMBB)
7444 .addReg(End2Reg).addMBB(LoopMBB);
7450 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
lib/Target/SystemZ/SystemZInstrInfo.cpp 496 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
505 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
510 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
lib/Target/SystemZ/SystemZPostRewrite.cpp 194 .addImm(CCValid).addImm(CCMask ^ CCValid).addMBB(RestMBB);
lib/Target/WebAssembly/WebAssemblyCFGStackify.cpp 1077 BuildMI(EHPadLayoutPred, DL, TII.get(WebAssembly::BR)).addMBB(Cont);
1143 .addMBB(BrDest);
lib/Target/WebAssembly/WebAssemblyFastISel.cpp 1290 .addMBB(TBB)
lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp 375 MIB.addMBB(Entry);
444 BuildMI(Routing, DebugLoc(), TII.get(WebAssembly::BR)).addMBB(Dispatch);
467 MIB.addMBB(MIB.getInstr()
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 411 BuildMI(BB, DL, TII.get(WebAssembly::BR_IF)).addMBB(TrueMBB).addReg(EqzReg);
413 BuildMI(FalseMBB, DL, TII.get(WebAssembly::BR)).addMBB(DoneMBB);
417 .addMBB(FalseMBB)
419 .addMBB(TrueMBB);
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp 188 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(TBB);
203 .addMBB(TBB)
207 BuildMI(&MBB, DL, get(WebAssembly::BR_IF)).addMBB(TBB).add(Cond[1]);
210 BuildMI(&MBB, DL, get(WebAssembly::BR_UNLESS)).addMBB(TBB).add(Cond[1]);
215 BuildMI(&MBB, DL, get(WebAssembly::BR)).addMBB(FBB);
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 159 .addMBB(TBB);
310 .addMBB(ThenMBB)
313 BuildMI(EHPad, DL, TII.get(WebAssembly::BR)).addMBB(ElseMBB);
lib/Target/X86/X86CmovConversion.cpp 691 BuildMI(MBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(CC);
836 .addMBB(FalseMBB)
838 .addMBB(MBB);
lib/Target/X86/X86CondBrFolding.cpp 228 .addMBB(NewDest).addImm(MBBInfo->BranchCode);
234 .addMBB(NewDest);
255 .addMBB(MBBInfo->TBB).addImm(CC);
261 .addMBB(MBBInfo->FBB);
324 .addMBB(RootMBBInfo->FBB).addImm(NewCC);
329 .addMBB(TargetMBB);
lib/Target/X86/X86ExpandPseudo.cpp 113 BuildMI(*MBB, MBBI, DL, TII->get(X86::JCC_1)).addMBB(ThenMBB).addImm(CC);
lib/Target/X86/X86FastISel.cpp 1695 .addMBB(TrueMBB).addImm(CC);
1701 .addMBB(TrueMBB).addImm(X86::COND_P);
1735 .addMBB(TrueMBB).addImm(JmpCond);
1749 .addMBB(TrueMBB).addImm(CC);
1774 .addMBB(TrueMBB).addImm(X86::COND_NE);
lib/Target/X86/X86FrameLowering.cpp 676 BuildMI(&MBB, DL, TII.get(X86::JCC_1)).addMBB(ContinueMBB).addImm(X86::COND_AE);
683 BuildMI(RoundMBB, DL, TII.get(X86::JMP_1)).addMBB(LoopMBB);
691 .addMBB(RoundMBB)
693 .addMBB(LoopMBB);
713 BuildMI(LoopMBB, DL, TII.get(X86::JCC_1)).addMBB(LoopMBB).addImm(X86::COND_NE);
2153 .addMBB(CatchRetTarget)
2158 .addMBB(CatchRetTarget);
2453 BuildMI(checkMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_A);
2695 BuildMI(stackCheckMBB, DL, TII.get(X86::JCC_1)).addMBB(&PrologueMBB).addImm(X86::COND_AE);
2704 BuildMI(incStackMBB, DL, TII.get(X86::JCC_1)).addMBB(incStackMBB).addImm(X86::COND_LE);
lib/Target/X86/X86ISelLowering.cpp29221 BuildMI(thisMBB, DL, TII->get(X86::XBEGIN_4)).addMBB(fallMBB);
29228 BuildMI(mainMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
29243 .addReg(mainDstReg).addMBB(mainMBB)
29244 .addReg(fallDstReg).addMBB(fallMBB);
29397 .addMBB(overflowMBB).addImm(X86::COND_AE);
29444 .addMBB(endMBB);
29502 .addReg(OffsetDestReg).addMBB(offsetMBB)
29503 .addReg(OverflowDestReg).addMBB(overflowMBB);
29554 BuildMI(MBB, DL, TII->get(X86::JCC_1)).addMBB(EndMBB).addImm(X86::COND_E);
29702 .addMBB(FalseMBB)
29704 .addMBB(TrueMBB);
29836 BuildMI(ThisMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(FirstCC);
29840 BuildMI(FirstInsertedMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(SecondCC);
29850 .addMBB(SecondInsertedMBB)
29852 .addMBB(ThisMBB);
29856 MIB.addReg(FirstCMOV.getOperand(2).getReg()).addMBB(FirstInsertedMBB);
29996 BuildMI(ThisMBB, DL, TII->get(X86::JCC_1)).addMBB(SinkMBB).addImm(CC);
30078 BuildMI(BB, DL, TII->get(X86::JCC_1)).addMBB(mallocMBB).addImm(X86::COND_G);
30086 BuildMI(bumpMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
30123 BuildMI(mallocMBB, DL, TII->get(X86::JMP_1)).addMBB(continueMBB);
30135 .addMBB(mallocMBB)
30137 .addMBB(bumpMBB);
30174 BuildMI(*RestoreMBB, RestoreMBBI, DL, TII.get(X86::JMP_4)).addMBB(TargetMBB);
30547 .addMBB(restoreMBB)
30555 .addMBB(restoreMBB, Subtarget.classifyBlockAddressReference())
30571 MIB.addMBB(restoreMBB);
30580 .addMBB(restoreMBB);
30595 .addReg(mainDstReg).addMBB(mainMBB)
30596 .addReg(restoreDstReg).addMBB(restoreMBB);
30612 BuildMI(restoreMBB, DL, TII->get(X86::JMP_1)).addMBB(sinkMBB);
30705 BuildMI(checkSspMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_E);
30735 BuildMI(fallMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_BE);
30758 BuildMI(fixShadowMBB, DL, TII->get(X86::JCC_1)).addMBB(sinkMBB).addImm(X86::COND_E);
30781 .addMBB(fixShadowLoopPrepareMBB)
30783 .addMBB(fixShadowLoopMBB);
30793 BuildMI(fixShadowLoopMBB, DL, TII->get(X86::JCC_1)).addMBB(fixShadowLoopMBB).addImm(X86::COND_NE);
30914 .addMBB(DispatchBB)
30921 .addMBB(DispatchBB, Subtarget.classifyBlockAddressReference())
30928 MIB.addMBB(DispatchBB);
31038 BuildMI(DispatchBB, DL, TII->get(X86::JCC_1)).addMBB(TrapBB).addImm(X86::COND_AE);
lib/Target/X86/X86InstrInfo.cpp 2592 .addMBB(UnCondBrIter->getOperand(0).getMBB())
2595 .addMBB(TargetBB);
2784 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
2797 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NE);
2799 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_P);
2810 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(FBB).addImm(X86::COND_NE);
2812 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(X86::COND_NP);
2816 BuildMI(&MBB, DL, get(X86::JCC_1)).addMBB(TBB).addImm(CC);
2822 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
lib/Target/X86/X86InstructionSelector.cpp 1415 .addMBB(DestMBB).addImm(X86::COND_NE);
lib/Target/X86/X86RetpolineThunks.cpp 276 BuildMI(CaptureSpec, DebugLoc(), TII->get(X86::JMP_1)).addMBB(CaptureSpec);
lib/Target/X86/X86SpeculativeLoadHardening.cpp 254 BuildMI(&MBB, DebugLoc(), TII.get(X86::JMP_1)).addMBB(&OldLayoutSucc);
1111 .addMBB(&MBB);
1122 .addMBB(&MBB)
1150 .addMBB(&MBB);
1162 .addMBB(&MBB)
lib/Target/XCore/XCoreISelLowering.cpp 1561 .addMBB(sinkMBB);
1577 .addMBB(copy0MBB)
1579 .addMBB(thisMBB);
lib/Target/XCore/XCoreInstrInfo.cpp 286 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(TBB);
291 .addMBB(TBB);
300 .addMBB(TBB);
301 BuildMI(&MBB, DL, get(XCore::BRFU_lu6)).addMBB(FBB);
tools/llvm-exegesis/lib/X86/Target.cpp 659 .addMBB(&TargetMBB)
unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp 704 .addMBB(EntryMBB)
706 .addMBB(MidMBB);
713 .addMBB(EntryMBB)
715 .addMBB(MidMBB);