reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
  824       OutMIs[InsnID].addDef(RegNum, RegState::Implicit);
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
   77       MIB.addDef(Reg);
   80       MIB.addDef(MRI.createGenericVirtualRegister(LLTTy));
   83       MIB.addDef(MRI.createVirtualRegister(RC));
lib/CodeGen/GlobalISel/CombinerHelper.cpp
  718     MIB.addDef(Addr);
  721     MIB.addDef(MI.getOperand(0).getReg());
  722     MIB.addDef(Addr);
lib/CodeGen/GlobalISel/IRTranslator.cpp
 1170   MIB.addDef(DstReg);
 1190       .addDef(ResRegs[0])
 1191       .addDef(ResRegs[1])
 1504         .addDef(getOrCreateVReg(CI))
 1850     .addDef(getOrCreateVReg(U))
 1920       .addDef(getOrCreateVReg(U))
lib/CodeGen/GlobalISel/LegalizerHelper.cpp
  825         .addDef(TmpReg)
  929           MIRBuilder.buildInstr(TargetOpcode::G_PHI).addDef(DstRegs[i]);
 1507       .addDef(ShrReg)
 1920         .addDef(QuotReg)
 1951       .addDef(HiPart)
 1965         .addDef(Shifted)
 2019     MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS);
 2463                                .addDef(PartDstReg)
 2471                                .addDef(PartDstReg)
 2535       .addDef(DstReg)
 2716                        .addDef(PartDstReg));
 2789       MIB.addDef(MI.getOperand(I * PartsPerUnmerge + J).getReg());
 3332       MIB.addDef(MI.getOperand(I).getReg());
 3336       MIB.addDef(MRI.createGenericVirtualRegister(DstTy));
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp
  295     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
  327     .addDef(getMRI()->createGenericVirtualRegister(EltTy))
  665       .addDef(Res)
  678     MIB.addDef(ResultReg);
  762       .addDef(OldValRes)
  763       .addDef(SuccessRes)
  788       .addDef(OldValRes)
  915   return buildInstr(TargetOpcode::G_BLOCK_ADDR).addDef(Res).addBlockAddress(BA);
lib/CodeGen/GlobalISel/RegBankSelect.cpp
  164       .addDef(Dst)
  194         .addDef(MO.getReg());
  204         UnMergeBuilder.addDef(DefReg);
lib/Target/AArch64/AArch64CallLowering.cpp
  124     MIB.addDef(PhysReg, RegState::Implicit);
 1013     MIB.addDef(AArch64::X21, RegState::Implicit);
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  364       .addDef(AddressReg)
  371       .addDef(SizeReg)
  509                    .addDef(Reg32)
lib/Target/AArch64/AArch64FastISel.cpp
  500         .addDef(Result64)
 5126       .addDef(ResultReg1)
 5127       .addDef(ScratchReg)
 5133       .addDef(VT == MVT::i32 ? AArch64::WZR : AArch64::XZR)
 5139       .addDef(ResultReg2)
lib/Target/AArch64/AArch64InstrInfo.cpp
 1514           .addDef(Reg32, RegState::Dead)
 1518           .addDef(Reg, RegState::Implicit);
 1556           .addDef(Reg32, RegState::Dead)
 1560           .addDef(Reg, RegState::Implicit);
lib/Target/AArch64/AArch64InstructionSelector.cpp
 1097           .addDef(ArgsAddrReg)
 1134     auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg);
 1425                      .addDef(AArch64::WZR)
 1663         .addDef(SrcReg)
 2048           .addDef(ExtSrc)
 2174              .addDef(AArch64::WZR)
 2179                                 .addDef(I.getOperand(0).getReg())
 2245              .addDef(Def1Reg)
 2254                .addDef(Def2Reg)
 2260                .addDef(DefReg)
 2390       .addDef(AArch64::X0, RegState::Implicit)
 2753                                 .addDef(SubToRegDef)
 2761                                 .addDef(SubToRegDef2)
 2767            .addDef(I.getOperand(0).getReg())
 3257   auto CmpMI = MIRBuilder.buildInstr(CmpOpc).addDef(ZReg).addUse(LHS.getReg());
lib/Target/AArch64/AArch64SpeculationHardening.cpp
  232         .addDef(MisspeculatingTaintReg)
  370       .addDef(AArch64::XZR)
  376       .addDef(MisspeculatingTaintReg)
  393       .addDef(TmpReg)
  399       .addDef(TmpReg, RegState::Renamable)
  405       .addDef(AArch64::SP)
  453       .addDef(Reg)
  577           .addDef(DstReg)
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
  333       .addDef(UnusedCarry, RegState::Dead)
  367       .addDef(CarryReg)
  372       .addDef(MRI->createVirtualRegister(CarryRC), RegState::Dead)
  956         .addDef(BaseReg)
  961         .addDef(OverflowVal)
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
 1164       .addDef(GetReg)
 1170       .addDef(ApertureReg)
 1304     .addDef(SrcAsInt)
 1619     .addDef(PCReg);
 1755     .addDef(DstReg)
 2121         .addDef(Def)
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp
  619     .addDef(LoLHS)
  620     .addDef(HiLHS)
  704     .addDef(InitSaveExecReg);
  733     .addDef(PhiExec)
  741       .addDef(std::get<2>(Result))
  793             .addDef(NewCondReg)
  803               .addDef(AndReg)
  887               .addDef(NewCondReg)
  896                 .addDef(AndReg)
  923     .addDef(NewExec)
  930     .addDef(ExecReg)
  948     .addDef(ExecReg)
 1009     .addDef(SGPR)
 1421       .addDef(DefRegs[0])
 1426       .addDef(DefRegs[1])
lib/Target/AMDGPU/SIFormMemoryClauses.cpp
  379           B.addDef(R.first, S, SubReg);
lib/Target/AMDGPU/SIInstrInfo.cpp
 1579       MovDPP.addDef(RI.getSubReg(Dst, Sub));
 1583       MovDPP.addDef(Tmp);
 4712         .addDef(CondReg0)
 4719         .addDef(CondReg1, RegState::Dead)
lib/Target/AMDGPU/SIShrinkInstructions.cpp
  530         .addDef(X1.Reg, 0, X1.SubReg)
  531         .addDef(Y1.Reg, 0, Y1.SubReg)
lib/Target/ARM/ARMCallLowering.cpp
  479     MIB.addDef(PhysReg, RegState::Implicit);
lib/Target/ARM/ARMInstructionSelector.cpp
  494       .addDef(DestReg)
  598                    .addDef(ResReg)
  695                            .addDef(ResultReg)
  792                    .addDef(ResReg)
  885                 .addDef(SExtResult)
  934               .addDef(DstReg)
  935               .addDef(IgnoredBits)
 1106         .addDef(ValueToStore)
lib/Target/ARM/ARMLowOverheadLoops.cpp
  397   MIB.addDef(ARM::LR);
  454     MIB.addDef(ARM::LR);
  472     MIB.addDef(ARM::LR);
lib/Target/ARM/Thumb1FrameLowering.cpp
  417       .addDef(ARM::CPSR)
  423       .addDef(ARM::CPSR)
lib/Target/Hexagon/HexagonFrameLowering.cpp
  672         .addDef(Hexagon::D15)
  720       .addDef(Hexagon::D15)
  726       .addDef(Hexagon::D15)
  755       .addDef(SP)
  767       .addDef(SP)
lib/Target/Mips/MipsCallLowering.cpp
  128     MIB.addDef(PhysReg, RegState::Implicit);
  149         .addDef(ValVReg)
  158         .addDef(ValVReg)
  261         .addDef(PhysReg + (STI.isLittle() ? 1 : 0))
  269         .addDef(PhysReg + (STI.isLittle() ? 0 : 1))
  276         .addDef(PhysReg)
  571   MIB.addDef(Mips::SP, RegState::Implicit);
  635     MIB.addDef(Mips::GP, RegState::Implicit);
lib/Target/Mips/MipsInstructionSelector.cpp
  270                       .addDef(PseudoMULTuReg)
  277                      .addDef(I.getOperand(0).getReg())
  319                             .addDef(JTIndex)
  327                              .addDef(DestAddress)
  336             .addDef(Dest)
  348                                .addDef(Dest)
  431                     .addDef(HILOReg)
  439                      .addDef(I.getOperand(0).getReg())
  537                 .addDef(ResultInFPR)
  543                              .addDef(I.getOperand(0).getReg())
  555                                 .addDef(I.getOperand(0).getReg())
  579                 .addDef(I.getOperand(0).getReg())
  590                               .addDef(LUiReg)
  598               .addDef(I.getOperand(0).getReg())
  611                .addDef(I.getOperand(0).getReg())
  621               .addDef(I.getOperand(0).getReg())
  758         .addDef(TrueInReg)
  774                              .addDef(I.getOperand(0).getReg())
  795             .addDef(LeaReg)
lib/Target/Mips/MipsSEISelDAGToDAG.cpp
  133         .addDef(Mips::AT_64)
  141         .addDef(Mips::AT)
  146         .addDef(Mips::SP)
lib/Target/X86/X86CallLowering.cpp
  318     MIB.addDef(PhysReg, RegState::Implicit);
  439         .addDef(X86::AL)
lib/Target/X86/X86FlagsCopyLowering.cpp
  820           .addDef(TmpReg, RegState::Dead)
lib/Target/X86/X86ISelLowering.cpp
30440       .addDef(ZReg)
30690       .addDef(ZReg)
lib/Target/X86/X86InstructionSelector.cpp
  255             .addDef(ExtSrc)
  830           .addDef(TransitRegTo)
  836           .addDef(DstReg)
  927       .addDef(DstReg)
 1704         .addDef(DstReg)
tools/llvm-exegesis/lib/X86/Target.cpp
  655       .addDef(kLoopCounterReg)
unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp
  702     .addDef(MRI->createGenericVirtualRegister(PhiTy))
  711     .addDef(MRI->createGenericVirtualRegister(s64))