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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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Declarations
include/llvm/CodeGen/GlobalISel/InstructionSelector.h 36 class MachineInstrBuilder;
lib/CodeGen/SelectionDAG/InstrEmitter.h 24 class MachineInstrBuilder;
lib/Target/AMDGPU/AMDGPUCallLowering.h 23 class MachineInstrBuilder;
lib/Target/AMDGPU/AMDGPUInstrInfo.h 27 class MachineInstrBuilder;
lib/Target/AMDGPU/R600InstrInfo.h 36 class MachineInstrBuilder;
lib/Target/ARM/ARMCallLowering.h 27 class MachineInstrBuilder;
lib/Target/X86/X86FrameLowering.h 20 class MachineInstrBuilder;
lib/Target/X86/X86InstrInfo.h 27 class MachineInstrBuilder;
References
include/llvm/ADT/Optional.h 144 T value;
160 explicit OptionalStorage(in_place_t, Args &&... args)
161 : value(std::forward<Args>(args)...), hasVal(true) {}
172 T &getValue() LLVM_LVALUE_FUNCTION noexcept {
176 T const &getValue() const LLVM_LVALUE_FUNCTION noexcept {
181 T &&getValue() && noexcept {
216 optional_detail::OptionalStorage<T> Storage;
219 using value_type = T;
224 Optional(const T &y) : Storage(optional_detail::in_place_t{}, y) {}
227 Optional(T &&y) : Storage(optional_detail::in_place_t{}, std::move(y)) {}
230 Optional &operator=(T &&y) {
241 static inline Optional create(const T *y) {
245 Optional &operator=(const T &y) {
253 const T *getPointer() const { return &Storage.getValue(); }
254 T *getPointer() { return &Storage.getValue(); }
255 const T &getValue() const LLVM_LVALUE_FUNCTION { return Storage.getValue(); }
256 T &getValue() LLVM_LVALUE_FUNCTION { return Storage.getValue(); }
260 const T *operator->() const { return getPointer(); }
261 T *operator->() { return getPointer(); }
262 const T &operator*() const LLVM_LVALUE_FUNCTION { return getValue(); }
263 T &operator*() LLVM_LVALUE_FUNCTION { return getValue(); }
266 constexpr T getValueOr(U &&value) const LLVM_LVALUE_FUNCTION {
271 T &&getValue() && { return std::move(Storage.getValue()); }
272 T &&operator*() && { return std::move(Storage.getValue()); }
275 T getValueOr(U &&value) && {
include/llvm/ADT/SmallVector.h 75 AlignedCharArrayUnion<T> FirstEl;
114 using value_type = T;
115 using iterator = T *;
116 using const_iterator = const T *;
121 using reference = T &;
122 using const_reference = const T &;
123 using pointer = T *;
124 using const_pointer = const T *;
259 class SmallVectorTemplateBase<T, true> : public SmallVectorTemplateCommon<T> {
264 static void destroy_range(T *, T *) {}
264 static void destroy_range(T *, T *) {}
299 void grow(size_t MinSize = 0) { this->grow_pod(MinSize, sizeof(T)); }
302 void push_back(const T &Elt) {
305 memcpy(reinterpret_cast<void *>(this->end()), &Elt, sizeof(T));
315 class SmallVectorImpl : public SmallVectorTemplateBase<T> {
316 using SuperClass = SmallVectorTemplateBase<T>;
352 new (&*I) T();
357 void resize(size_type N, const T &NV) {
374 LLVM_NODISCARD T pop_back_val() {
397 void append(size_type NumInputs, const T &Elt) {
405 void append(std::initializer_list<T> IL) {
412 void assign(size_type NumElts, const T &Elt) {
429 void assign(std::initializer_list<T> IL) {
467 iterator insert(iterator I, T &&Elt) {
497 iterator insert(iterator I, const T &Elt) {
526 iterator insert(iterator I, size_type NumToInsert, const T &Elt) {
637 void insert(iterator I, std::initializer_list<T> IL) {
820 AlignedCharArrayUnion<T> InlineElts[N];
837 class SmallVector : public SmallVectorImpl<T>, SmallVectorStorage<T, N> {
837 class SmallVector : public SmallVectorImpl<T>, SmallVectorStorage<T, N> {
846 explicit SmallVector(size_t Size, const T &Value = T())
865 SmallVector(std::initializer_list<T> IL) : SmallVectorImpl<T>(N) {
884 SmallVector(SmallVectorImpl<T> &&RHS) : SmallVectorImpl<T>(N) {
include/llvm/CodeGen/GlobalISel/CSEMIRBuilder.h 50 MachineInstrBuilder getDominatingInstrForID(FoldingSetNodeID &ID,
78 MachineInstrBuilder memoizeMI(MachineInstrBuilder MIB, void *NodeInsertPos);
78 MachineInstrBuilder memoizeMI(MachineInstrBuilder MIB, void *NodeInsertPos);
82 MachineInstrBuilder generateCopiesIfRequired(ArrayRef<DstOp> DstOps,
83 MachineInstrBuilder &MIB);
94 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
100 MachineInstrBuilder buildConstant(const DstOp &Res,
105 MachineInstrBuilder buildFConstant(const DstOp &Res,
include/llvm/CodeGen/GlobalISel/ConstantFoldingMIRBuilder.h 28 MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
include/llvm/CodeGen/GlobalISel/InstructionSelector.h 404 Optional<SmallVector<std::function<void(MachineInstrBuilder &)>, 4>>;
406 using NewMIVector = SmallVector<MachineInstrBuilder, 4>;
include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h 111 auto MIBMask = Builder.buildConstant(DstTy, Mask.getZExtValue());
include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h 74 void addDefToMIB(MachineRegisterInfo &MRI, MachineInstrBuilder &MIB) const {
122 MachineInstrBuilder SrcMIB;
132 SrcOp(const MachineInstrBuilder &MIB) : SrcMIB(MIB), Ty(SrcType::Ty_MIB) {}
142 void addSrcToMIB(MachineInstrBuilder &MIB) const {
333 MachineInstrBuilder buildInstr(unsigned Opcode);
340 MachineInstrBuilder buildInstrNoInsert(unsigned Opcode);
343 MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
343 MachineInstrBuilder insertInstr(MachineInstrBuilder MIB);
347 MachineInstrBuilder buildDirectDbgValue(Register Reg, const MDNode *Variable,
353 MachineInstrBuilder buildIndirectDbgValue(Register Reg,
360 MachineInstrBuilder buildFIDbgValue(int FI, const MDNode *Variable,
365 MachineInstrBuilder buildConstDbgValue(const Constant &C,
371 MachineInstrBuilder buildDbgLabel(const MDNode *Label);
381 MachineInstrBuilder buildDynStackAlloc(const DstOp &Res, const SrcOp &Size,
393 MachineInstrBuilder buildFrameIndex(const DstOp &Res, int Idx);
405 MachineInstrBuilder buildGlobalValue(const DstOp &Res, const GlobalValue *GV);
418 MachineInstrBuilder buildGEP(const DstOp &Res, const SrcOp &Op0,
437 Optional<MachineInstrBuilder> materializeGEP(Register &Res, Register Op0,
454 MachineInstrBuilder buildPtrMask(const DstOp &Res, const SrcOp &Op0,
469 MachineInstrBuilder buildUAddo(const DstOp &Res, const DstOp &CarryOut,
486 MachineInstrBuilder buildUAdde(const DstOp &Res, const DstOp &CarryOut,
504 MachineInstrBuilder buildAnyExt(const DstOp &Res, const SrcOp &Op);
518 MachineInstrBuilder buildSExt(const DstOp &Res, const SrcOp &Op);
521 MachineInstrBuilder buildFPExt(const DstOp &Res, const SrcOp &Op,
528 MachineInstrBuilder buildPtrToInt(const DstOp &Dst, const SrcOp &Src) {
533 MachineInstrBuilder buildIntToPtr(const DstOp &Dst, const SrcOp &Src) {
538 MachineInstrBuilder buildBitcast(const DstOp &Dst, const SrcOp &Src) {
543 MachineInstrBuilder buildAddrSpaceCast(const DstOp &Dst, const SrcOp &Src) {
553 MachineInstrBuilder buildBoolExt(const DstOp &Res, const SrcOp &Op,
568 MachineInstrBuilder buildZExt(const DstOp &Res, const SrcOp &Op);
578 MachineInstrBuilder buildSExtOrTrunc(const DstOp &Res, const SrcOp &Op);
588 MachineInstrBuilder buildZExtOrTrunc(const DstOp &Res, const SrcOp &Op);
598 MachineInstrBuilder buildAnyExtOrTrunc(const DstOp &Res, const SrcOp &Op);
609 MachineInstrBuilder buildExtOrTrunc(unsigned ExtOpc, const DstOp &Res,
613 MachineInstrBuilder buildCast(const DstOp &Dst, const SrcOp &Src);
622 MachineInstrBuilder buildBr(MachineBasicBlock &Dest);
636 MachineInstrBuilder buildBrCond(Register Tst, MachineBasicBlock &Dest);
646 MachineInstrBuilder buildBrIndirect(Register Tgt);
659 MachineInstrBuilder buildBrJT(Register TablePtr, unsigned JTI,
672 virtual MachineInstrBuilder buildConstant(const DstOp &Res,
683 MachineInstrBuilder buildConstant(const DstOp &Res, int64_t Val);
684 MachineInstrBuilder buildConstant(const DstOp &Res, const APInt &Val);
695 virtual MachineInstrBuilder buildFConstant(const DstOp &Res,
698 MachineInstrBuilder buildFConstant(const DstOp &Res, double Val);
699 MachineInstrBuilder buildFConstant(const DstOp &Res, const APFloat &Val);
708 MachineInstrBuilder buildCopy(const DstOp &Res, const SrcOp &Op);
719 MachineInstrBuilder buildLoad(const DstOp &Res, const SrcOp &Addr,
731 MachineInstrBuilder buildLoadInstr(unsigned Opcode, const DstOp &Res,
743 MachineInstrBuilder buildStore(const SrcOp &Val, const SrcOp &Addr,
752 MachineInstrBuilder buildExtract(const DstOp &Res, const SrcOp &Src, uint64_t Index);
755 MachineInstrBuilder buildUndef(const DstOp &Res);
784 MachineInstrBuilder buildMerge(const DstOp &Res, ArrayRef<Register> Ops);
796 MachineInstrBuilder buildUnmerge(ArrayRef<LLT> Res, const SrcOp &Op);
797 MachineInstrBuilder buildUnmerge(ArrayRef<Register> Res, const SrcOp &Op);
800 MachineInstrBuilder buildUnmerge(LLT Res, const SrcOp &Op);
811 MachineInstrBuilder buildBuildVector(const DstOp &Res,
816 MachineInstrBuilder buildSplatVector(const DstOp &Res,
832 MachineInstrBuilder buildBuildVectorTrunc(const DstOp &Res,
846 MachineInstrBuilder buildConcatVectors(const DstOp &Res,
849 MachineInstrBuilder buildInsert(Register Res, Register Src,
862 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<Register> Res,
864 MachineInstrBuilder buildIntrinsic(Intrinsic::ID ID, ArrayRef<DstOp> Res,
877 MachineInstrBuilder buildFPTrunc(const DstOp &Res, const SrcOp &Op,
891 MachineInstrBuilder buildTrunc(const DstOp &Res, const SrcOp &Op);
905 MachineInstrBuilder buildICmp(CmpInst::Predicate Pred, const DstOp &Res,
920 MachineInstrBuilder buildFCmp(CmpInst::Predicate Pred, const DstOp &Res,
934 MachineInstrBuilder buildSelect(const DstOp &Res, const SrcOp &Tst,
948 MachineInstrBuilder buildInsertVectorElement(const DstOp &Res,
961 MachineInstrBuilder buildExtractVectorElement(const DstOp &Res,
981 MachineInstrBuilder
1000 MachineInstrBuilder buildAtomicCmpXchg(Register OldValRes, Register Addr,
1017 MachineInstrBuilder buildAtomicRMW(unsigned Opcode, const DstOp &OldValRes,
1033 MachineInstrBuilder buildAtomicRMWXchg(Register OldValRes, Register Addr,
1048 MachineInstrBuilder buildAtomicRMWAdd(Register OldValRes, Register Addr,
1063 MachineInstrBuilder buildAtomicRMWSub(Register OldValRes, Register Addr,
1078 MachineInstrBuilder buildAtomicRMWAnd(Register OldValRes, Register Addr,
1094 MachineInstrBuilder buildAtomicRMWNand(Register OldValRes, Register Addr,
1109 MachineInstrBuilder buildAtomicRMWOr(Register OldValRes, Register Addr,
1124 MachineInstrBuilder buildAtomicRMWXor(Register OldValRes, Register Addr,
1140 MachineInstrBuilder buildAtomicRMWMax(Register OldValRes, Register Addr,
1156 MachineInstrBuilder buildAtomicRMWMin(Register OldValRes, Register Addr,
1172 MachineInstrBuilder buildAtomicRMWUmax(Register OldValRes, Register Addr,
1188 MachineInstrBuilder buildAtomicRMWUmin(Register OldValRes, Register Addr,
1192 MachineInstrBuilder buildAtomicRMWFAdd(
1197 MachineInstrBuilder buildAtomicRMWFSub(
1202 MachineInstrBuilder buildFence(unsigned Ordering, unsigned Scope);
1212 MachineInstrBuilder buildBlockAddress(Register Res, const BlockAddress *BA);
1225 MachineInstrBuilder buildAdd(const DstOp &Dst, const SrcOp &Src0,
1242 MachineInstrBuilder buildSub(const DstOp &Dst, const SrcOp &Src0,
1258 MachineInstrBuilder buildMul(const DstOp &Dst, const SrcOp &Src0,
1264 MachineInstrBuilder buildUMulH(const DstOp &Dst, const SrcOp &Src0,
1270 MachineInstrBuilder buildSMulH(const DstOp &Dst, const SrcOp &Src0,
1276 MachineInstrBuilder buildFMul(const DstOp &Dst, const SrcOp &Src0,
1282 MachineInstrBuilder buildShl(const DstOp &Dst, const SrcOp &Src0,
1288 MachineInstrBuilder buildLShr(const DstOp &Dst, const SrcOp &Src0,
1294 MachineInstrBuilder buildAShr(const DstOp &Dst, const SrcOp &Src0,
1311 MachineInstrBuilder buildAnd(const DstOp &Dst, const SrcOp &Src0,
1326 MachineInstrBuilder buildOr(const DstOp &Dst, const SrcOp &Src0,
1332 MachineInstrBuilder buildXor(const DstOp &Dst, const SrcOp &Src0,
1340 MachineInstrBuilder buildNot(const DstOp &Dst, const SrcOp &Src0) {
1341 auto NegOne = buildConstant(Dst.getLLTTy(*getMRI()), -1);
1346 MachineInstrBuilder buildCTPOP(const DstOp &Dst, const SrcOp &Src0) {
1351 MachineInstrBuilder buildCTLZ(const DstOp &Dst, const SrcOp &Src0) {
1356 MachineInstrBuilder buildCTLZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) {
1361 MachineInstrBuilder buildCTTZ(const DstOp &Dst, const SrcOp &Src0) {
1366 MachineInstrBuilder buildCTTZ_ZERO_UNDEF(const DstOp &Dst, const SrcOp &Src0) {
1371 MachineInstrBuilder buildFAdd(const DstOp &Dst, const SrcOp &Src0,
1378 MachineInstrBuilder buildFSub(const DstOp &Dst, const SrcOp &Src0,
1384 MachineInstrBuilder buildFMA(const DstOp &Dst, const SrcOp &Src0,
1390 MachineInstrBuilder buildFMAD(const DstOp &Dst, const SrcOp &Src0,
1397 MachineInstrBuilder buildFNeg(const DstOp &Dst, const SrcOp &Src0,
1403 MachineInstrBuilder buildFAbs(const DstOp &Dst, const SrcOp &Src0,
1409 MachineInstrBuilder buildFCanonicalize(const DstOp &Dst, const SrcOp &Src0,
1415 MachineInstrBuilder buildFCopysign(const DstOp &Dst, const SrcOp &Src0,
1421 MachineInstrBuilder buildUITOFP(const DstOp &Dst, const SrcOp &Src0) {
1426 MachineInstrBuilder buildSITOFP(const DstOp &Dst, const SrcOp &Src0) {
1431 MachineInstrBuilder buildFPTOUI(const DstOp &Dst, const SrcOp &Src0) {
1436 MachineInstrBuilder buildFPTOSI(const DstOp &Dst, const SrcOp &Src0) {
1441 MachineInstrBuilder buildSMin(const DstOp &Dst, const SrcOp &Src0,
1447 MachineInstrBuilder buildSMax(const DstOp &Dst, const SrcOp &Src0,
1453 MachineInstrBuilder buildUMin(const DstOp &Dst, const SrcOp &Src0,
1459 MachineInstrBuilder buildUMax(const DstOp &Dst, const SrcOp &Src0,
1470 MachineInstrBuilder buildJumpTable(const LLT PtrTy, unsigned JTI);
1472 virtual MachineInstrBuilder buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps,
include/llvm/CodeGen/MachineInstrBuilder.h 88 const MachineInstrBuilder &addReg(Register RegNo, unsigned flags = 0,
107 const MachineInstrBuilder &addDef(Register RegNo, unsigned Flags = 0,
114 const MachineInstrBuilder &addUse(Register RegNo, unsigned Flags = 0,
122 const MachineInstrBuilder &addImm(int64_t Val) const {
127 const MachineInstrBuilder &addCImm(const ConstantInt *Val) const {
132 const MachineInstrBuilder &addFPImm(const ConstantFP *Val) const {
137 const MachineInstrBuilder &addMBB(MachineBasicBlock *MBB,
143 const MachineInstrBuilder &addFrameIndex(int Idx) const {
148 const MachineInstrBuilder &
155 const MachineInstrBuilder &addTargetIndex(unsigned Idx, int64_t Offset = 0,
162 const MachineInstrBuilder &addJumpTableIndex(unsigned Idx,
168 const MachineInstrBuilder &addGlobalAddress(const GlobalValue *GV,
175 const MachineInstrBuilder &addExternalSymbol(const char *FnName,
181 const MachineInstrBuilder &addBlockAddress(const BlockAddress *BA,
188 const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const {
193 const MachineInstrBuilder &addMemOperand(MachineMemOperand *MMO) const {
198 const MachineInstrBuilder &
204 const MachineInstrBuilder &cloneMemRefs(const MachineInstr &OtherMI) const {
209 const MachineInstrBuilder &
215 const MachineInstrBuilder &add(const MachineOperand &MO) const {
220 const MachineInstrBuilder &add(ArrayRef<MachineOperand> MOs) const {
227 const MachineInstrBuilder &addMetadata(const MDNode *MD) const {
238 const MachineInstrBuilder &addCFIIndex(unsigned CFIIndex) const {
243 const MachineInstrBuilder &addIntrinsicID(Intrinsic::ID ID) const {
248 const MachineInstrBuilder &addPredicate(CmpInst::Predicate Pred) const {
253 const MachineInstrBuilder &addShuffleMask(const Constant *Val) const {
258 const MachineInstrBuilder &addSym(MCSymbol *Sym,
264 const MachineInstrBuilder &setMIFlags(unsigned Flags) const {
269 const MachineInstrBuilder &setMIFlag(MachineInstr::MIFlag Flag) const {
275 const MachineInstrBuilder &addDisp(const MachineOperand &Disp, int64_t off,
302 const MachineInstrBuilder &
316 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
323 inline MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
332 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
348 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
358 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
368 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
377 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
387 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
397 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I,
407 inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *I,
415 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,
423 inline MachineInstrBuilder BuildMI(MachineBasicBlock *BB, const DebugLoc &DL,
432 MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
439 MachineInstrBuilder BuildMI(MachineFunction &MF, const DebugLoc &DL,
447 MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
455 MachineInstrBuilder BuildMI(MachineBasicBlock &BB,
include/llvm/Support/AlignOf.h 30 T t;
39 template <typename T> union SizerImpl<T> { char arr[sizeof(T)]; };
50 llvm::detail::SizerImpl<T, Ts...>)];
include/llvm/Support/type_traits.h 91 T t;
122 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<const F &>(), std::true_type{});
122 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<const F &>(), std::true_type{});
122 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<const F &>(), std::true_type{});
130 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<F &&>(), std::true_type{});
130 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<F &&>(), std::true_type{});
130 static auto get(F*) -> decltype(std::declval<F &>() = std::declval<F &&>(), std::true_type{});
145 std::is_copy_constructible<detail::trivial_helper<T>>::value;
147 !std::is_copy_constructible<T>::value;
151 std::is_move_constructible<detail::trivial_helper<T>>::value;
153 !std::is_move_constructible<T>::value;
157 is_copy_assignable<detail::trivial_helper<T>>::value;
159 !is_copy_assignable<T>::value;
163 is_move_assignable<detail::trivial_helper<T>>::value;
165 !is_move_assignable<T>::value;
169 std::is_destructible<detail::trivial_helper<T>>::value;
lib/CodeGen/GlobalISel/CSEMIRBuilder.cpp 33 MachineInstrBuilder
105 MachineInstrBuilder CSEMIRBuilder::memoizeMI(MachineInstrBuilder MIB,
105 MachineInstrBuilder CSEMIRBuilder::memoizeMI(MachineInstrBuilder MIB,
124 MachineInstrBuilder
126 MachineInstrBuilder &MIB) {
137 MachineInstrBuilder CSEMIRBuilder::buildInstr(unsigned Opc,
183 auto MIB = MachineIRBuilder::buildInstr(Opc, DstOps, SrcOps, Flag);
193 MachineInstrBuilder MIB = getDominatingInstrForID(ID, InsertPos);
199 MachineInstrBuilder NewMIB =
204 MachineInstrBuilder CSEMIRBuilder::buildConstant(const DstOp &Res,
221 MachineInstrBuilder MIB = getDominatingInstrForID(ID, InsertPos);
227 MachineInstrBuilder NewMIB = MachineIRBuilder::buildConstant(Res, Val);
231 MachineInstrBuilder CSEMIRBuilder::buildFConstant(const DstOp &Res,
248 MachineInstrBuilder MIB = getDominatingInstrForID(ID, InsertPos);
253 MachineInstrBuilder NewMIB = MachineIRBuilder::buildFConstant(Res, Val);
lib/CodeGen/GlobalISel/CallLowering.cpp 260 auto Unmerge = MIRBuilder.buildUnmerge(SmallTy, LargeReg);
337 auto Unmerge = MIRBuilder.buildUnmerge({OrigTy, OrigTy}, {NewReg});
467 auto MIB = MIRBuilder.buildAnyExt(LocTy, ValReg);
lib/CodeGen/GlobalISel/CombinerHelper.cpp 716 auto MIB = MIRBuilder.buildInstr(NewOpcode);
908 auto ZExt = MIB.buildZExtOrTrunc(ExtType, Val);
911 auto MagicMI = MIB.buildConstant(ExtType, Magic);
1017 auto Offset =
1126 auto LdVal = MIB.buildLoad(CopyTy, LoadPtr, *LoadMMO);
1219 auto Offset =
1236 auto Offset =
lib/CodeGen/GlobalISel/IRTranslator.cpp 518 auto Table = MIB.buildJumpTable(PtrTy, JT.JTI);
533 auto FirstCst = MIB.buildConstant(SwitchTy, JTH.First);
534 auto Sub = MIB.buildSub({SwitchTy}, SwitchOpReg, FirstCst);
556 auto Cmp = MIB.buildICmp(CmpInst::ICMP_UGT, LLT::scalar(1), Sub, Cst);
558 auto BrCond = MIB.buildBrCond(Cmp.getReg(0), *JT.Default);
606 auto Sub = MIB.buildSub({CmpTy}, CmpOpReg, CondLHS);
607 auto Diff = MIB.buildConstant(CmpTy, High - Low);
632 auto True = MIB.buildConstant(i1Ty, 1);
1082 auto OffsetMIB = MIRBuilder.buildConstant({OffsetTy}, Offset);
1096 auto ElementSizeMIB = MIRBuilder.buildConstant(
1108 auto OffsetMIB =
1127 auto ICall = MIRBuilder.buildIntrinsic(ID, Res, true);
1169 auto MIB = MIRBuilder.buildInstr(TargetOpcode::LOAD_STACK_GUARD);
1422 auto FMul = MIRBuilder.buildInstr(TargetOpcode::G_FMUL, {Ty}, {Op0, Op1},
1621 MachineInstrBuilder MIB =
1830 auto SAMinusOne = MIRBuilder.buildConstant(IntPtrTy, StackAlign - 1);
1831 auto AllocAdd = MIRBuilder.buildAdd(IntPtrTy, AllocSize, SAMinusOne,
1833 auto AlignCst =
1835 auto AlignedAlloc = MIRBuilder.buildAnd(IntPtrTy, AllocAdd, AlignCst);
1932 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_PHI, {Reg}, {});
2071 MachineInstrBuilder MIB(*MF, ComponentPHIs[j]);
lib/CodeGen/GlobalISel/LegalizerHelper.cpp 638 auto K = MIRBuilder.buildConstant(NarrowTy,
648 auto K = MIRBuilder.buildConstant(
676 auto ShiftAmt =
678 auto Shift = MIRBuilder.buildAShr(NarrowTy, SrcReg, ShiftAmt);
713 auto Unmerge = MIRBuilder.buildUnmerge(NarrowTy, MI.getOperand(1).getReg());
928 MachineInstrBuilder MIB =
969 MachineInstrBuilder XorL = MIRBuilder.buildXor(NarrowTy, LHSL, RHSL);
970 MachineInstrBuilder XorH = MIRBuilder.buildXor(NarrowTy, LHSH, RHSH);
971 MachineInstrBuilder Or = MIRBuilder.buildOr(NarrowTy, XorL, XorH);
972 MachineInstrBuilder Zero = MIRBuilder.buildConstant(NarrowTy, 0);
975 MachineInstrBuilder CmpH = MIRBuilder.buildICmp(Pred, ResTy, LHSH, RHSH);
976 MachineInstrBuilder CmpHEQ =
978 MachineInstrBuilder CmpLU = MIRBuilder.buildICmp(
1001 auto TruncMIB = MIRBuilder.buildTrunc(NarrowTy, MO1.getReg());
1084 auto ExtB = MIRBuilder.buildInstr(ExtOpcode, {WideTy}, {MO.getReg()});
1091 auto ExtB = MIRBuilder.buildInstr(TargetOpcode::G_TRUNC, {NarrowTy},
1142 auto Concat = MIRBuilder.buildConcatVectors(MoreTy, Parts);
1185 auto ZextInput = MIRBuilder.buildZExt(WideTy, SrcReg);
1190 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, Offset);
1191 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);
1240 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
1258 auto Merge = MIRBuilder.buildMerge(WideTy, Slicer.take_front(PartsPerGCD));
1267 auto FinalMerge = MIRBuilder.buildMerge(WideDstTy, NewMergeRegs);
1296 auto WideSrc = MIRBuilder.buildZExt(NewSrcTy, SrcReg);
1299 auto ShiftAmt = MIRBuilder.buildConstant(NewSrcTy, SizeDiff * I);
1300 auto Shl = MIRBuilder.buildShl(NewSrcTy, WideSrc, ShiftAmt);
1361 auto LShr = MIRBuilder.buildLShr(
1425 auto LHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1427 auto RHSZext = MIRBuilder.buildInstr(TargetOpcode::G_ZEXT, {WideTy},
1433 auto NewOp = MIRBuilder.buildInstr(Opcode, {WideTy}, {LHSZext, RHSZext});
1436 auto AndOp = MIRBuilder.buildInstr(
1462 auto MIBSrc = MIRBuilder.buildZExt(WideTy, SrcReg);
1475 auto MIBNewOp = MIRBuilder.buildInstr(MI.getOpcode(), {WideTy}, {MIBSrc});
1527 auto ShiftAmt = MIRBuilder.buildConstant(WideTy, DiffBits);
1528 auto Shift = MIRBuilder.buildLShr(WideTy, DstExt, ShiftAmt);
2001 auto Zero = MIRBuilder.buildFConstant(Ty, ZeroForNegation);
2081 auto LargeLoad =
2084 auto OffsetCst =
2087 auto SmallPtr = MIRBuilder.buildGEP(GEPReg, PtrReg, OffsetCst.getReg(0));
2088 auto SmallLoad = MIRBuilder.buildLoad(SmallLdReg, SmallPtr.getReg(0),
2091 auto ShiftAmt = MIRBuilder.buildConstant(AnyExtTy, LargeSplitSize);
2092 auto Shift = MIRBuilder.buildShl(AnyExtTy, SmallLoad, ShiftAmt);
2093 auto Or = MIRBuilder.buildOr(AnyExtTy, Shift, LargeLoad);
2146 auto ExtVal = MIRBuilder.buildAnyExt(ExtendTy, SrcReg);
2151 auto ShiftAmt = MIRBuilder.buildConstant(ExtendTy, LargeSplitSize);
2152 auto SmallVal = MIRBuilder.buildLShr(ExtendTy, ExtVal, ShiftAmt);
2156 auto OffsetCst =
2159 auto SmallPtr = MIRBuilder.buildGEP(GEPReg, PtrReg, OffsetCst.getReg(0));
2268 auto MIBSz = MIRBuilder.buildConstant(DstTy, DstTy.getScalarSizeInBits() - SizeInBits);
2439 SmallVector<MachineInstrBuilder, 4> NewInsts;
2493 for (auto &MIB : NewInsts)
2707 SmallVector<MachineInstrBuilder, 4> NewInsts;
2747 MachineInstrBuilder MIB = NewInsts[J];
2781 auto Unmerge = MIRBuilder.buildUnmerge(GCDTy, SrcReg);
2786 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
2840 auto BuildVec = MIRBuilder.buildBuildVector(NarrowTy, SubBuildVector);
2848 auto Concat = MIRBuilder.buildConcatVectors(WidenedDstTy, ConcatOps);
3072 auto OrLHS =
3074 auto OrRHS = MIRBuilder.buildLShr(
3089 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3091 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3092 auto OrRHS = MIRBuilder.buildShl(
3112 auto ShiftAmtConst = MIRBuilder.buildConstant(AmtTy, Amt);
3114 auto OrLHS = MIRBuilder.buildLShr(NVT, InL, ShiftAmtConst);
3115 auto OrRHS = MIRBuilder.buildShl(
3167 auto NewBits = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize);
3173 auto AmtExcess = MIRBuilder.buildSub(ShiftAmtTy, Amt, NewBits);
3174 auto AmtLack = MIRBuilder.buildSub(ShiftAmtTy, NewBits, Amt);
3176 auto Zero = MIRBuilder.buildConstant(ShiftAmtTy, 0);
3177 auto IsShort = MIRBuilder.buildICmp(ICmpInst::ICMP_ULT, CondTy, Amt, NewBits);
3178 auto IsZero = MIRBuilder.buildICmp(ICmpInst::ICMP_EQ, CondTy, Amt, Zero);
3184 auto LoS = MIRBuilder.buildShl(HalfTy, InL, Amt);
3186 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, AmtLack);
3187 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, Amt);
3188 auto HiS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3191 auto LoL = MIRBuilder.buildConstant(HalfTy, 0); // Lo part is zero.
3192 auto HiL = MIRBuilder.buildShl(HalfTy, InL, AmtExcess); // Hi from Lo part.
3194 auto Lo = MIRBuilder.buildSelect(HalfTy, IsShort, LoS, LoL);
3195 auto Hi = MIRBuilder.buildSelect(
3205 auto HiS = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy}, {InH, Amt});
3207 auto LoOr = MIRBuilder.buildLShr(HalfTy, InL, Amt);
3208 auto HiOr = MIRBuilder.buildShl(HalfTy, InH, AmtLack);
3209 auto LoS = MIRBuilder.buildOr(HalfTy, LoOr, HiOr);
3212 MachineInstrBuilder HiL;
3216 auto ShiftAmt = MIRBuilder.buildConstant(ShiftAmtTy, NewBitSize - 1);
3219 auto LoL = MIRBuilder.buildInstr(MI.getOpcode(), {HalfTy},
3222 auto Lo = MIRBuilder.buildSelect(
3225 auto Hi = MIRBuilder.buildSelect(HalfTy, IsShort, HiS, HiL);
3330 auto MIB = MIRBuilder.buildInstr(TargetOpcode::G_UNMERGE_VALUES);
3369 MachineInstrBuilder Mul =
3376 MachineInstrBuilder Umulh =
3388 MachineInstrBuilder Uaddo =
3393 MachineInstrBuilder Uaddo =
3396 MachineInstrBuilder Carry = B.buildZExt(NarrowTy, Uaddo.getReg(1));
3609 auto Inst = MIRBuilder.buildInstr(MI.getOpcode(), {NarrowTy},
3615 auto Inst = MIRBuilder.buildInstr(
3656 auto Select = MIRBuilder.buildSelect(NarrowTy,
3662 auto Select = MIRBuilder.buildSelect(
3697 auto MIBCtlzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTLZ_ZERO_UNDEF,
3699 auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3700 auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3701 auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3722 auto MIBShiftAmt = MIRBuilder.buildConstant(Ty, 1ULL << i);
3723 auto MIBOp = MIRBuilder.buildInstr(
3729 auto MIBPop = MIRBuilder.buildInstr(TargetOpcode::G_CTPOP, {Ty}, {Op});
3748 auto MIBCttzZU = MIRBuilder.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
3750 auto MIBZero = MIRBuilder.buildConstant(Ty, 0);
3751 auto MIBLen = MIRBuilder.buildConstant(Ty, Len);
3752 auto MIBICmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, LLT::scalar(1),
3763 auto MIBCstNeg1 = MIRBuilder.buildConstant(Ty, -1);
3764 auto MIBNot =
3766 auto MIBTmp = MIRBuilder.buildInstr(
3772 auto MIBCstLen = MIRBuilder.buildConstant(Ty, Len);
3809 auto Zero32 = MIRBuilder.buildConstant(S32, 0);
3810 auto Zero64 = MIRBuilder.buildConstant(S64, 0);
3812 auto LZ = MIRBuilder.buildCTLZ_ZERO_UNDEF(S32, Src);
3814 auto K = MIRBuilder.buildConstant(S32, 127U + 63U);
3815 auto Sub = MIRBuilder.buildSub(S32, K, LZ);
3817 auto NotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, Src, Zero64);
3818 auto E = MIRBuilder.buildSelect(S32, NotZero, Sub, Zero32);
3820 auto Mask0 = MIRBuilder.buildConstant(S64, (-1ULL) >> 1);
3821 auto ShlLZ = MIRBuilder.buildShl(S64, Src, LZ);
3823 auto U = MIRBuilder.buildAnd(S64, ShlLZ, Mask0);
3825 auto Mask1 = MIRBuilder.buildConstant(S64, 0xffffffffffULL);
3826 auto T = MIRBuilder.buildAnd(S64, U, Mask1);
3828 auto UShl = MIRBuilder.buildLShr(S64, U, MIRBuilder.buildConstant(S64, 40));
3829 auto ShlE = MIRBuilder.buildShl(S32, E, MIRBuilder.buildConstant(S32, 23));
3830 auto V = MIRBuilder.buildOr(S32, ShlE, MIRBuilder.buildTrunc(S32, UShl));
3832 auto C = MIRBuilder.buildConstant(S64, 0x8000000000ULL);
3833 auto RCmp = MIRBuilder.buildICmp(CmpInst::ICMP_UGT, S1, T, C);
3834 auto TCmp = MIRBuilder.buildICmp(CmpInst::ICMP_EQ, S1, T, C);
3835 auto One = MIRBuilder.buildConstant(S32, 1);
3837 auto VTrunc1 = MIRBuilder.buildAnd(S32, V, One);
3838 auto Select0 = MIRBuilder.buildSelect(S32, TCmp, VTrunc1, Zero32);
3839 auto R = MIRBuilder.buildSelect(S32, RCmp, One, Select0);
3887 auto SignBit = MIRBuilder.buildConstant(S64, 63);
3888 auto S = MIRBuilder.buildAShr(S64, L, SignBit);
3890 auto LPlusS = MIRBuilder.buildAdd(S64, L, S);
3891 auto Xor = MIRBuilder.buildXor(S64, LPlusS, S);
3892 auto R = MIRBuilder.buildUITOFP(S32, Xor);
3894 auto RNeg = MIRBuilder.buildFNeg(S32, R);
3895 auto SignNotZero = MIRBuilder.buildICmp(CmpInst::ICMP_NE, S1, S,
3928 MachineInstrBuilder FPTOSI = MIRBuilder.buildFPTOSI(DstTy, Src);
3930 MachineInstrBuilder Threshold = MIRBuilder.buildFConstant(SrcTy, TwoPExpFP);
3933 MachineInstrBuilder FSub = MIRBuilder.buildFSub(SrcTy, Src, Threshold);
3934 MachineInstrBuilder ResLowBits = MIRBuilder.buildFPTOSI(DstTy, FSub);
3935 MachineInstrBuilder ResHighBit = MIRBuilder.buildConstant(DstTy, TwoPExpInt);
3936 MachineInstrBuilder Res = MIRBuilder.buildXor(DstTy, ResLowBits, ResHighBit);
3938 MachineInstrBuilder FCMP =
3970 auto Cmp = MIRBuilder.buildICmp(Pred, CmpType, Src0, Src1);
3989 auto SignBitMask = MIRBuilder.buildConstant(
3992 auto NotSignBitMask = MIRBuilder.buildConstant(
3995 auto And0 = MIRBuilder.buildAnd(Src0Ty, Src0, NotSignBitMask);
3999 auto And1 = MIRBuilder.buildAnd(Src1Ty, Src0, SignBitMask);
4002 auto ShiftAmt = MIRBuilder.buildConstant(Src0Ty, Src0Size - Src1Size);
4003 auto Zext = MIRBuilder.buildZExt(Src0Ty, Src1);
4004 auto Shift = MIRBuilder.buildShl(Src0Ty, Zext, ShiftAmt);
4005 auto And1 = MIRBuilder.buildAnd(Src0Ty, Shift, SignBitMask);
4008 auto ShiftAmt = MIRBuilder.buildConstant(Src1Ty, Src1Size - Src0Size);
4009 auto Shift = MIRBuilder.buildLShr(Src1Ty, Src1, ShiftAmt);
4010 auto Trunc = MIRBuilder.buildTrunc(Src0Ty, Shift);
4011 auto And1 = MIRBuilder.buildAnd(Src0Ty, Trunc, SignBitMask);
4062 auto Mul = MIRBuilder.buildFMul(Ty, MI.getOperand(1), MI.getOperand(2),
4090 auto ShiftAmt = MIRBuilder.buildConstant(IntTy, Offset);
4091 auto Shift = MIRBuilder.buildLShr(IntTy, Cast, ShiftAmt);
4150 auto IdxK = MIRBuilder.buildConstant(IdxTy, ExtractIdx);
4151 auto Extract = MIRBuilder.buildExtractVectorElement(EltTy, SrcVec, IdxK);
4174 auto SPTmp = MIRBuilder.buildCopy(PtrTy, SPReg);
4180 auto Alloc = MIRBuilder.buildSub(IntPtrTy, SPTmp, AllocSize);
4184 auto AlignCst = MIRBuilder.buildConstant(IntPtrTy, AlignMask);
4217 auto ShiftAmt = MIRBuilder.buildConstant(SrcIntTy, Offset);
4218 auto Shr = MIRBuilder.buildLShr(SrcIntTy, Src, ShiftAmt);
4249 auto ShiftAmt = MIRBuilder.buildConstant(IntDstTy, Offset);
4256 auto Mask = MIRBuilder.buildConstant(IntDstTy, MaskVal);
4257 auto MaskedSrc = MIRBuilder.buildAnd(IntDstTy, Src, Mask);
4258 auto Or = MIRBuilder.buildOr(IntDstTy, MaskedSrc, ExtInsSrc);
4286 auto Zero = MIRBuilder.buildConstant(Ty, 0);
4294 auto ResultLowerThanLHS =
4296 auto ConditionRHS = MIRBuilder.buildICmp(
lib/CodeGen/GlobalISel/MachineIRBuilder.cpp 74 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
78 MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
79 MachineInstrBuilder MIB = BuildMI(getMF(), getDL(), getTII().get(Opcode));
83 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
83 MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
89 MachineInstrBuilder
102 MachineInstrBuilder
119 MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
138 MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
146 auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
162 MachineInstrBuilder MachineIRBuilder::buildDbgLabel(const MDNode *Label) {
166 auto MIB = buildInstr(TargetOpcode::DBG_LABEL);
171 MachineInstrBuilder MachineIRBuilder::buildDynStackAlloc(const DstOp &Res,
175 auto MIB = buildInstr(TargetOpcode::G_DYN_STACKALLOC);
182 MachineInstrBuilder MachineIRBuilder::buildFrameIndex(const DstOp &Res,
185 auto MIB = buildInstr(TargetOpcode::G_FRAME_INDEX);
191 MachineInstrBuilder MachineIRBuilder::buildGlobalValue(const DstOp &Res,
198 auto MIB = buildInstr(TargetOpcode::G_GLOBAL_VALUE);
204 MachineInstrBuilder MachineIRBuilder::buildJumpTable(const LLT PtrTy,
222 MachineInstrBuilder MachineIRBuilder::buildGEP(const DstOp &Res,
232 Optional<MachineInstrBuilder>
244 auto Cst = buildConstant(ValueTy, Value);
248 MachineInstrBuilder MachineIRBuilder::buildPtrMask(const DstOp &Res,
254 auto MIB = buildInstr(TargetOpcode::G_PTR_MASK);
261 MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
265 MachineInstrBuilder MachineIRBuilder::buildBrIndirect(Register Tgt) {
270 MachineInstrBuilder MachineIRBuilder::buildBrJT(Register TablePtr,
281 MachineInstrBuilder MachineIRBuilder::buildCopy(const DstOp &Res,
286 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
294 auto Const = buildInstr(TargetOpcode::G_CONSTANT)
300 auto Const = buildInstr(TargetOpcode::G_CONSTANT);
306 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
314 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
326 auto Const = buildInstr(TargetOpcode::G_FCONSTANT)
333 auto Const = buildInstr(TargetOpcode::G_FCONSTANT);
339 MachineInstrBuilder MachineIRBuilder::buildConstant(const DstOp &Res,
345 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
354 MachineInstrBuilder MachineIRBuilder::buildFConstant(const DstOp &Res,
361 MachineInstrBuilder MachineIRBuilder::buildBrCond(Register Tst,
368 MachineInstrBuilder MachineIRBuilder::buildLoad(const DstOp &Res,
374 MachineInstrBuilder MachineIRBuilder::buildLoadInstr(unsigned Opcode,
381 auto MIB = buildInstr(Opcode);
388 MachineInstrBuilder MachineIRBuilder::buildStore(const SrcOp &Val,
394 auto MIB = buildInstr(TargetOpcode::G_STORE);
401 MachineInstrBuilder MachineIRBuilder::buildUAddo(const DstOp &Res,
408 MachineInstrBuilder MachineIRBuilder::buildUAdde(const DstOp &Res,
417 MachineInstrBuilder MachineIRBuilder::buildAnyExt(const DstOp &Res,
422 MachineInstrBuilder MachineIRBuilder::buildSExt(const DstOp &Res,
427 MachineInstrBuilder MachineIRBuilder::buildZExt(const DstOp &Res,
444 MachineInstrBuilder MachineIRBuilder::buildBoolExt(const DstOp &Res,
451 MachineInstrBuilder MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc,
475 MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(const DstOp &Res,
480 MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(const DstOp &Res,
485 MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(const DstOp &Res,
490 MachineInstrBuilder MachineIRBuilder::buildCast(const DstOp &Dst,
510 MachineInstrBuilder MachineIRBuilder::buildExtract(const DstOp &Dst,
528 auto Extract = buildInstr(TargetOpcode::G_EXTRACT);
576 MachineInstrBuilder MachineIRBuilder::buildUndef(const DstOp &Res) {
580 MachineInstrBuilder MachineIRBuilder::buildMerge(const DstOp &Res,
590 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<LLT> Res,
600 MachineInstrBuilder MachineIRBuilder::buildUnmerge(LLT Res,
609 MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<Register> Res,
619 MachineInstrBuilder MachineIRBuilder::buildBuildVector(const DstOp &Res,
628 MachineInstrBuilder MachineIRBuilder::buildSplatVector(const DstOp &Res,
634 MachineInstrBuilder
644 MachineInstrBuilder
653 MachineInstrBuilder MachineIRBuilder::buildInsert(Register Res, Register Src,
671 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
674 auto MIB =
683 MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
686 auto MIB =
695 MachineInstrBuilder MachineIRBuilder::buildTrunc(const DstOp &Res,
700 MachineInstrBuilder MachineIRBuilder::buildFPTrunc(const DstOp &Res,
706 MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
713 MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
722 MachineInstrBuilder MachineIRBuilder::buildSelect(const DstOp &Res,
731 MachineInstrBuilder
737 MachineInstrBuilder
743 MachineInstrBuilder MachineIRBuilder::buildAtomicCmpXchgWithSuccess(
770 MachineInstrBuilder
795 MachineInstrBuilder MachineIRBuilder::buildAtomicRMW(
811 auto MIB = buildInstr(Opcode);
819 MachineInstrBuilder
825 MachineInstrBuilder
831 MachineInstrBuilder
837 MachineInstrBuilder
843 MachineInstrBuilder
849 MachineInstrBuilder MachineIRBuilder::buildAtomicRMWOr(Register OldValRes,
856 MachineInstrBuilder
862 MachineInstrBuilder
868 MachineInstrBuilder
874 MachineInstrBuilder
880 MachineInstrBuilder
887 MachineInstrBuilder
895 MachineInstrBuilder
902 MachineInstrBuilder
909 MachineInstrBuilder
953 MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opc,
1173 auto MIB = buildInstr(Opc);
lib/CodeGen/GlobalISel/RegBankSelect.cpp 192 auto MergeBuilder =
201 MachineInstrBuilder UnMergeBuilder =
lib/CodeGen/IfConversion.cpp 1495 MachineInstrBuilder MIB(*OpMI->getMF(), OpMI);
lib/CodeGen/ImplicitNullChecks.cpp 637 auto MIB = BuildMI(MBB, DL, TII->get(TargetOpcode::FAULTING_OP), DefReg)
lib/CodeGen/MachineInstr.cpp 2013 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2021 auto MIB = BuildMI(MF, DL, MCID).addReg(Reg, RegState::Debug);
2029 MachineInstrBuilder llvm::BuildMI(MachineFunction &MF, const DebugLoc &DL,
2040 auto MIB = BuildMI(MF, DL, MCID).add(MO);
2048 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
2059 MachineInstrBuilder llvm::BuildMI(MachineBasicBlock &BB,
lib/CodeGen/MachineInstrBundle.cpp 134 MachineInstrBuilder MIB =
lib/CodeGen/MachinePipeliner.cpp 368 auto Copy = BuildMI(PredB, At, DL, TII->get(TargetOpcode::COPY), NewReg)
lib/CodeGen/MachineSSAUpdater.cpp 116 MachineInstrBuilder InsertNewDef(unsigned Opcode,
189 MachineInstrBuilder InsertedPHI = InsertNewDef(TargetOpcode::PHI, BB,
lib/CodeGen/ModuloSchedule.cpp 550 MachineInstrBuilder NewPhi =
666 MachineInstrBuilder NewPhi =
lib/CodeGen/PatchableFunction.cpp 72 auto MIB = BuildMI(FirstMBB, FirstActualI, FirstActualI->getDebugLoc(),
lib/CodeGen/PeepholeOptimizer.cpp 766 MachineInstrBuilder MIB = BuildMI(*MBB, &OrigPHI, OrigPHI.getDebugLoc(),
lib/CodeGen/RenameIndependentSubregs.cpp 332 MachineInstrBuilder ImpDef = BuildMI(*PredMBB, InsertPos,
lib/CodeGen/SelectionDAG/FastISel.cpp 838 auto Builder =
845 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1022 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, CLI.Call, DbgLoc,
1050 MachineInstrBuilder MIB =
1071 MachineInstrBuilder MIB =
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 190 MachineInstrBuilder &MIB,
291 InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
362 void InstrEmitter::AddOperand(MachineInstrBuilder &MIB,
540 MachineInstrBuilder CopyMI =
578 MachineInstrBuilder MIB =
635 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II, NewVReg);
691 auto MIB = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE));
702 auto FrameMI = BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE))
713 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
772 MachineInstrBuilder MIB = BuildMI(*MF, DL, II);
845 MachineInstrBuilder MIB = BuildMI(*MF, Node->getDebugLoc(), II);
1054 MachineInstrBuilder MIB =
lib/CodeGen/SelectionDAG/InstrEmitter.h 46 MachineInstrBuilder &MIB,
59 void AddRegisterOperand(MachineInstrBuilder &MIB,
70 void AddOperand(MachineInstrBuilder &MIB,
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 1707 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first);
1833 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1886 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first);
1937 MachineInstrBuilder PHI(*MF, MBBI);
lib/CodeGen/SwiftErrorValueTracking.cpp 244 MachineInstrBuilder PHI =
lib/CodeGen/TailDuplicator.cpp 468 MachineInstrBuilder MIB(*FromBB->getParent(), MI);
984 auto C = BuildMI(*MBB, Loc, DebugLoc(), CopyD, CI.first)
lib/CodeGen/TargetInstrInfo.cpp 502 MachineInstrBuilder MIB(MF, NewMI);
837 MachineInstrBuilder MIB1 =
841 MachineInstrBuilder MIB2 =
lib/CodeGen/TargetLoweringBase.cpp 1046 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1105 auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
1120 auto MIB = BuildMI(MF, MI.getDebugLoc(), MI.getDesc());
lib/CodeGen/TwoAddressInstructionPass.cpp 1552 MachineInstrBuilder MIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
lib/CodeGen/XRayInstrumentation.cpp 108 auto MIB = BuildMI(MBB, T, T.getDebugLoc(), TII->get(Opc))
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 276 MachineInstrBuilder MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
lib/Target/AArch64/AArch64CallLowering.cpp 81 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
120 MachineInstrBuilder MIB, CCAssignFn *AssignFn)
127 MachineInstrBuilder MIB;
132 MachineInstrBuilder MIB, CCAssignFn *AssignFn,
204 MachineInstrBuilder MIB;
260 auto MIB = MIRBuilder.buildInstrNoInsert(AArch64::RET_ReallyLR);
323 auto Undef = MIRBuilder.buildUndef({OldLLT});
336 auto Undef = MIRBuilder.buildUndef({OldLLT});
804 MachineInstrBuilder CallSeqStart;
809 auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
963 MachineInstrBuilder CallSeqStart;
970 auto MIB = MIRBuilder.buildInstrNoInsert(Opc);
lib/Target/AArch64/AArch64CondBrTuning.cpp 105 MachineInstrBuilder MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
lib/Target/AArch64/AArch64ConditionalCompares.cpp 695 MachineInstrBuilder MIB = BuildMI(*Head, CmpMI, CmpMI->getDebugLoc(), MCID)
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 92 static void transferImpOps(MachineInstr &OldMI, MachineInstrBuilder &UseMI,
93 MachineInstrBuilder &DefMI) {
126 SmallVector<MachineInstrBuilder, 4> MIBS;
465 MachineInstrBuilder MIB1 =
484 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
500 MachineInstrBuilder MIB1 =
503 MachineInstrBuilder MIB2;
552 MachineInstrBuilder MIB1 =
573 MachineInstrBuilder MIB2 =
623 MachineInstrBuilder MIB =
655 MachineInstrBuilder MIB =
lib/Target/AArch64/AArch64FastISel.cpp 188 void addLoadStoreOperands(Address &Addr, const MachineInstrBuilder &MIB,
1121 const MachineInstrBuilder &MIB,
1897 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2172 MachineInstrBuilder MIB =
2409 MachineInstrBuilder MIB =
3266 MachineInstrBuilder MIB;
3933 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
lib/Target/AArch64/AArch64FrameLowering.cpp 492 MachineInstrBuilder MIB;
693 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc));
2046 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StrOpc));
2135 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdrOpc));
lib/Target/AArch64/AArch64InstrInfo.cpp 380 const MachineInstrBuilder MIB =
2391 static const MachineInstrBuilder &AddSubReg(const MachineInstrBuilder &MIB,
2391 static const MachineInstrBuilder &AddSubReg(const MachineInstrBuilder &MIB,
2430 const MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opcode));
2454 const MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opcode));
2902 const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
3033 const MachineInstrBuilder MI = BuildMI(MBB, MBBI, DebugLoc(), get(Opc))
3096 auto MBI = BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
4019 MachineInstrBuilder MIB;
4085 MachineInstrBuilder MIB =
4181 MachineInstrBuilder MIB1 =
4215 MachineInstrBuilder MIB1 =
4272 MachineInstrBuilder MIB1 =
4539 MachineInstrBuilder MIB1 =
4586 MachineInstrBuilder MIB1 =
4646 MachineInstrBuilder MIB1 =
4666 MachineInstrBuilder MIB1 =
4686 MachineInstrBuilder MIB1 =
lib/Target/AArch64/AArch64InstructionSelector.cpp 238 void renderTruncImm(MachineInstrBuilder &MIB, const MachineInstr &MI) const;
239 void renderLogicalImm32(MachineInstrBuilder &MIB, const MachineInstr &I) const;
240 void renderLogicalImm64(MachineInstrBuilder &MIB, const MachineInstr &I) const;
598 auto Copy = MIB.buildCopy({From}, {SrcReg});
599 auto SubRegCopy = MIB.buildInstr(TargetOpcode::COPY, {To}, {})
1033 auto UShl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg, Src2Reg});
1075 auto Neg = MIB.buildInstr(NegOpc, {RC}, {Src2Reg});
1077 auto SShl = MIB.buildInstr(Opc, {DstReg}, {Src1Reg, Neg});
1095 auto MIB =
1122 auto MovZ = MIB.buildInstr(AArch64::MOVZXi, {&AArch64::GPR64RegClass}, {});
1134 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg);
1183 auto Trunc = MIB.buildInstr(TargetOpcode::COPY, {SrcTy}, {})
1220 auto NewI =
1416 auto MIB = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::TBNZW))
1424 auto CMP = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::ANDSWri))
1429 auto Bcc =
1709 MachineInstrBuilder MIB(MF, I);
1912 auto AddsMI = MIRBuilder.buildInstr(
1921 auto CsetMI = MIRBuilder
2103 auto SubregToReg =
2229 auto CmpMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(CmpOpc))
2296 auto MovMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::MOVaddrBA),
2361 auto MovMI =
2382 auto Load = MIB.buildInstr(AArch64::LDRXui, {&AArch64::GPR64commonRegClass},
2667 auto Cmp = MIB.buildInstr(Opc, {SrcRC}, {SrcReg, Src2Reg});
2685 auto Undef = MIRBuilder.buildInstr(TargetOpcode::IMPLICIT_DEF, {DstRC}, {});
2688 auto Ins =
2728 auto Tmp = MIB.buildInstr(TargetOpcode::IMPLICIT_DEF, {DstTy}, {});
2838 auto Copy = MIRBuilder.buildInstr(TargetOpcode::COPY, {*DstReg}, {})
3018 auto FirstCopy = MIB.buildInstr(TargetOpcode::COPY, {CopyTo}, {})
3080 auto Adrp =
3155 auto AddMI = MIRBuilder.buildInstr(Opc, {DefReg}, {LHS.getReg()});
3181 auto CmpMI = MIRBuilder.buildInstr(Opc, {ZReg}, {LHS.getReg()});
3211 auto TstMI = MIRBuilder.buildInstr(Opc, {ZReg}, {LHS});
3257 auto CmpMI = MIRBuilder.buildInstr(CmpOpc).addDef(ZReg).addUse(LHS.getReg());
3321 auto InsElt =
3370 auto I =
3458 auto Cmp = MIB.buildInstr(CmpOpc, {}, {CondDef->getOperand(2).getReg()});
3466 auto CSel =
3631 auto Dup = MIB.buildInstr(Opc, {I.getOperand(0).getReg()}, {ScalarReg});
3710 auto TBL1 = MIRBuilder.buildInstr(
3715 auto Copy =
3726 auto RegSeq = MIRBuilder
3733 auto TBL2 =
3996 auto SHA1Inst = MIRBuilder.buildInstr(AArch64::SHA1Hrr, {DstReg}, {SrcReg});
4560 auto Copy = MIB.buildCopy({NarrowReg}, {ExtReg});
4635 void AArch64InstructionSelector::renderTruncImm(MachineInstrBuilder &MIB,
4645 MachineInstrBuilder &MIB, const MachineInstr &I) const {
4653 MachineInstrBuilder &MIB, const MachineInstr &I) const {
lib/Target/AArch64/AArch64LegalizerInfo.cpp 678 auto ExtCst = MIRBuilder.buildZExt(LLT::scalar(64), AmtReg);
711 auto Bitcast = MIRBuilder.buildBitcast({NewTy}, {ValReg});
715 auto NewLoad = MIRBuilder.buildLoad(NewReg, MI.getOperand(1).getReg(), MMO);
744 auto AlignMinus1 = MIRBuilder.buildConstant(IntPtrTy, Align - 1);
746 auto ListTmp = MIRBuilder.buildGEP(PtrTy, List, AlignMinus1.getReg(0));
759 auto Size = MIRBuilder.buildConstant(IntPtrTy, alignTo(ValSize, PtrSize));
761 auto NewList = MIRBuilder.buildGEP(PtrTy, DstPtr, Size.getReg(0));
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 763 MachineInstrBuilder MIB;
856 MachineInstrBuilder MIB;
915 MachineInstrBuilder MIBKill =
921 MachineInstrBuilder MIBSXTW =
1394 MachineInstrBuilder MIB;
lib/Target/AMDGPU/AMDGPUCallLowering.cpp 35 MachineInstrBuilder MIB, CCAssignFn *AssignFn)
38 MachineInstrBuilder MIB;
101 auto Copy = MIRBuilder.buildCopy(LLT::scalar(32), PhysReg);
110 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
234 auto UnmergeToEltTy = B.buildUnmerge(SrcTy.getElementType(),
249 auto ImpDef = B.buildUndef(BigTy);
263 MachineInstrBuilder &Ret) const {
317 auto Ret = B.buildInstrNoInsert(ReturnOpc);
513 auto RoundedConcat = B.buildConcatVectors(RoundedDestTy, Regs);
535 auto Merge = B.buildMerge(DstEltTy,
545 auto BV = B.buildBuildVector(BVType, Regs);
lib/Target/AMDGPU/AMDGPUCallLowering.h 42 ArrayRef<Register> VRegs, MachineInstrBuilder &Ret) const;
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 479 MachineInstrBuilder MIB =
1011 MachineInstrBuilder MIB = B.buildInstr(Opc)
1387 auto MIB = BuildMI(*MBB, I, DL, TII.get(NewOpc), DstReg)
2177 void AMDGPUInstructionSelector::renderTruncImm32(MachineInstrBuilder &MIB,
lib/Target/AMDGPU/AMDGPUInstructionSelector.h 167 void renderTruncImm32(MachineInstrBuilder &MIB,
lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp 1168 auto ShiftAmt = B.buildConstant(S32, WidthM1 + 1);
1253 auto HighAddr = B.buildConstant(
1265 auto SegmentNull = B.buildConstant(DstTy, NullVal);
1266 auto FlatNull = B.buildConstant(SrcTy, 0);
1287 auto SegmentNull =
1289 auto FlatNull =
1328 auto C1 = B.buildFConstant(Ty, C1Val);
1329 auto CopySign = B.buildFCopysign(Ty, C1, Src);
1332 auto Tmp1 = B.buildFAdd(Ty, Src, CopySign);
1333 auto Tmp2 = B.buildFSub(Ty, Tmp1, CopySign);
1335 auto C2 = B.buildFConstant(Ty, C2Val);
1336 auto Fabs = B.buildFAbs(Ty, Src);
1338 auto Cond = B.buildFCmp(CmpInst::FCMP_OGT, LLT::scalar(1), Fabs, C2);
1358 auto Trunc = B.buildInstr(TargetOpcode::G_INTRINSIC_TRUNC, {S64}, {Src});
1360 const auto Zero = B.buildFConstant(S64, 0.0);
1361 const auto One = B.buildFConstant(S64, 1.0);
1362 auto Lt0 = B.buildFCmp(CmpInst::FCMP_OGT, S1, Src, Zero);
1363 auto NeTrunc = B.buildFCmp(CmpInst::FCMP_ONE, S1, Src, Trunc);
1364 auto And = B.buildAnd(S1, Lt0, NeTrunc);
1365 auto Add = B.buildSelect(S64, And, One, Zero);
1372 static MachineInstrBuilder extractF64Exponent(unsigned Hi,
1378 auto Const0 = B.buildConstant(S32, FractBits - 32);
1379 auto Const1 = B.buildConstant(S32, ExpBits);
1381 auto ExpPart = B.buildIntrinsic(Intrinsic::amdgcn_ubfe, {S32}, false)
1401 auto Unmerge = B.buildUnmerge({S32, S32}, Src);
1406 auto Exp = extractF64Exponent(Hi, B);
1411 const auto SignBitMask = B.buildConstant(S32, UINT32_C(1) << 31);
1412 auto SignBit = B.buildAnd(S32, Hi, SignBitMask);
1414 const auto FractMask = B.buildConstant(S64, (UINT64_C(1) << FractBits) - 1);
1416 const auto Zero32 = B.buildConstant(S32, 0);
1419 auto SignBit64 = B.buildMerge(S64, {Zero32.getReg(0), SignBit.getReg(0)});
1421 auto Shr = B.buildAShr(S64, FractMask, Exp);
1422 auto Not = B.buildNot(S64, Shr);
1423 auto Tmp0 = B.buildAnd(S64, Src, Not);
1424 auto FiftyOne = B.buildConstant(S32, FractBits - 1);
1426 auto ExpLt0 = B.buildICmp(CmpInst::ICMP_SLT, S1, Exp, Zero32);
1427 auto ExpGt51 = B.buildICmp(CmpInst::ICMP_SGT, S1, Exp, FiftyOne);
1429 auto Tmp1 = B.buildSelect(S64, ExpLt0, SignBit64, Tmp0);
1447 auto Unmerge = B.buildUnmerge({S32, S32}, Src);
1449 auto CvtHi = Signed ?
1453 auto CvtLo = B.buildUITOFP(S64, Unmerge.getReg(0));
1455 auto ThirtyTwo = B.buildConstant(S32, 32);
1456 auto LdExp = B.buildIntrinsic(Intrinsic::amdgcn_ldexp, {S64}, false)
1560 auto OneOver2Pi = B.buildFConstant(Ty, 0.5 / M_PI);
1562 auto MulVal = B.buildFMul(Ty, SrcReg, OneOver2Pi, Flags);
1618 MachineInstrBuilder MIB = B.buildInstr(AMDGPU::SI_PC_ADD_REL_OFFSET)
1695 auto Load = B.buildLoad(PtrTy, GOTAddr, *GOTMMO);
1709 auto Cast = B.buildAddrSpaceCast(ConstPtr, MI.getOperand(1).getReg());
1808 auto ShiftAmt = B.buildConstant(S32, Shift);
1912 auto FNeg = B.buildFNeg(ResTy, RHS, Flags);
1924 auto RCP = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {ResTy}, false)
1949 auto LHSExt = B.buildFPExt(S32, LHS, Flags);
1950 auto RHSExt = B.buildFPExt(S32, RHS, Flags);
1952 auto RCP = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S32}, false)
1956 auto QUOT = B.buildFMul(S32, LHSExt, RCP, Flags);
1957 auto RDst = B.buildFPTrunc(S16, QUOT, Flags);
1981 auto Abs = B.buildFAbs(S32, RHS, Flags);
1984 auto C0 = B.buildConstant(S32, 0x6f800000);
1985 auto C1 = B.buildConstant(S32, 0x2f800000);
1986 auto C2 = B.buildConstant(S32, FloatToBits(1.0f));
1988 auto CmpRes = B.buildFCmp(CmpInst::FCMP_OGT, S1, Abs, C0, Flags);
1989 auto Sel = B.buildSelect(S32, CmpRes, C1, C2, Flags);
1991 auto Mul0 = B.buildFMul(S32, RHS, Sel, Flags);
1993 auto RCP = B.buildIntrinsic(Intrinsic::amdgcn_rcp, {S32}, false)
1997 auto Mul1 = B.buildFMul(S32, LHS, RCP, Flags);
2045 auto Hi32 = B.buildExtract(LLT::scalar(32), MI.getOperand(2).getReg(), 32);
2063 auto Unmerge = B.buildUnmerge(S16, Reg);
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 1484 MachineInstrBuilder MIB =
1529 MachineInstrBuilder MIB =
1578 MachineInstrBuilder MIB =
1769 MachineInstrBuilder MIB = BuildMI(*MergeBB, MergeBB->instr_begin(), DL,
2160 MachineInstrBuilder MIB = BuildMI(*Entry, Entry->instr_begin(), DL,
2178 MachineInstrBuilder BackedgePHI =
2453 MachineInstrBuilder MIB =
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 827 auto Unmerge = B.buildUnmerge(UnmergeTy, Op.getReg());
906 auto Merge = B.buildBuildVector(OpTy, ReadlanePieces);
909 auto Merge = B.buildMerge(OpTy, ReadlanePieces);
1160 auto Unmerge = B.buildUnmerge(S16, Reg);
1219 auto OverflowVal = B.buildConstant(S32, Overflow);
1303 MachineInstrBuilder MIB = B.buildInstr(Opc)
1521 auto ShiftAmt = B.buildConstant(S32, 31);
1550 auto True = B.buildConstant(SelType, Signed ? -1 : 1);
1551 auto False = B.buildConstant(SelType, 0);
1561 auto Sel = B.buildSelect(SelType, SrcReg, True, False);
1575 auto Ext = B.buildAnyExt(DstTy, SrcReg);
1576 auto ShiftAmt = B.buildConstant(LLT::scalar(32), DstTy.getSizeInBits() - 1);
1577 auto Shl = B.buildShl(DstTy, Ext, ShiftAmt);
1625 auto ShiftAmt = B.buildConstant(S32, 16);
1634 auto ShiftAmt = B.buildConstant(S32, 16);
1644 auto Or = B.buildOr(S32, ZextLo, ShiftHi);
1675 auto CastSrc = B.buildBitcast(Vec32, SrcReg);
1676 auto One = B.buildConstant(S32, 1);
1685 auto IdxLo = B.buildShl(S32, IdxReg, One);
1686 auto IdxHi = B.buildAdd(S32, IdxLo, One);
1742 auto CastSrc = B.buildBitcast(Vec32, SrcReg);
1743 auto One = B.buildConstant(S32, 1);
1752 auto IdxLo = B.buildShl(S32, IdxReg, One);
1753 auto IdxHi = B.buildAdd(S32, IdxLo, One);
1755 auto InsLo = B.buildInsertVectorElement(Vec32, CastSrc, InsRegs[0], IdxLo);
1756 auto InsHi = B.buildInsertVectorElement(Vec32, InsLo, InsRegs[1], IdxHi);
lib/Target/AMDGPU/AMDILCFGStructurizer.cpp 496 MachineInstrBuilder MIB(*MF, NewMI);
lib/Target/AMDGPU/GCNDPPCombine.cpp 167 auto DPPInst = BuildMI(*OrigMI.getParent(), OrigMI,
437 auto UndefInst = BuildMI(*MovMI.getParent(), MovMI, MovMI.getDebugLoc(),
lib/Target/AMDGPU/R600ControlFlowFinalizer.cpp 443 MachineInstrBuilder MILit = BuildMI(MBB, I, I->getDebugLoc(),
lib/Target/AMDGPU/R600ISelLowering.cpp 304 MachineInstrBuilder NewMI;
360 auto MIB = TII->buildDefaultInstruction(
lib/Target/AMDGPU/R600InstrInfo.cpp 989 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
997 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1113 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1120 MachineInstrBuilder R600InstrInfo::buildIndirectWrite(MachineBasicBlock *MBB,
1137 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV,
1145 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1152 MachineInstrBuilder R600InstrInfo::buildIndirectRead(MachineBasicBlock *MBB,
1169 MachineInstrBuilder Mov = buildDefaultInstruction(*MBB, I, R600::MOV,
1237 MachineInstrBuilder R600InstrInfo::buildDefaultInstruction(MachineBasicBlock &MBB,
1243 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
lib/Target/AMDGPU/R600InstrInfo.h 48 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
54 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
244 MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
252 MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
266 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
lib/Target/AMDGPU/SIFoldOperands.cpp 697 MachineInstrBuilder B(*MBB.getParent(), UseMI);
lib/Target/AMDGPU/SIFormMemoryClauses.cpp 362 auto B = BuildMI(MBB, I, DebugLoc(), TII->get(TargetOpcode::BUNDLE));
lib/Target/AMDGPU/SIISelLowering.cpp 3799 MachineInstrBuilder MIB(*MF, &MI);
3815 MachineInstrBuilder MIB;
3838 auto I = BuildMI(*BB, MI, DL, TII->get(Opc), MI.getOperand(0).getReg());
lib/Target/AMDGPU/SIInsertSkips.cpp 260 auto I = BuildMI(MBB, &MI, DL, TII->get(Opcode));
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 1152 auto SWaitInst = BuildMI(*MI.getParent(), MI.getIterator(),
1166 auto SWaitInst =
lib/Target/AMDGPU/SIInstrInfo.cpp 720 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
801 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
1095 auto MIB = BuildMI(MBB, MI, DL, get(Opcode));
1214 auto MIB = BuildMI(MBB, MI, DL, get(Opcode), DestReg);
1520 MachineInstrBuilder MIB = BuildMI(MF, DL, get(AMDGPU::S_ADDC_U32), RegHi)
1577 auto MovDPP = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_dpp));
2228 MachineInstrBuilder MIB = BuildMI(
3061 MachineInstrBuilder Inst32 =
4243 MachineInstrBuilder MIB =
4757 MachineInstrBuilder MIB =
6104 MachineInstrBuilder HeaderPHIBuilder =
6188 MachineInstrBuilder
6204 MachineInstrBuilder SIInstrInfo::getAddNoCarry(MachineBasicBlock &MBB,
lib/Target/AMDGPU/SIInstrInfo.h 989 MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
994 MachineInstrBuilder getAddNoCarry(MachineBasicBlock &MBB,
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 925 MachineInstrBuilder Read2 =
1018 MachineInstrBuilder Write2 =
1050 auto MIB = BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode), DestReg);
1154 auto MIB = BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode), DestReg);
1319 auto MIB = BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode))
lib/Target/AMDGPU/SIPeepholeSDWA.cpp 509 MachineInstrBuilder MIB(*MBB->getParent(), MI);
924 auto NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(Opc));
930 auto NewInst = BuildMI(MBB, MISucc, MISucc.getDebugLoc(), TII->get(SuccOpc));
1009 MachineInstrBuilder SDWAInst =
1193 auto Copy = BuildMI(*MI.getParent(), MI.getIterator(), MI.getDebugLoc(),
lib/Target/AMDGPU/SIRegisterInfo.cpp 543 static MachineInstrBuilder spillVGPRtoAGPR(const GCNSubtarget &ST,
594 MachineInstrBuilder NewMI =
699 auto MIB = spillVGPRtoAGPR(ST, MI, Index, i, SubReg, IsKill);
823 MachineInstrBuilder Mov
902 auto MIB =
934 auto MIB =
1121 if (auto MIB = TII->getAddNoCarry(*MBB, MI, DL, ResultReg, *RS)) {
lib/Target/ARC/ARCInstrInfo.cpp 387 MachineInstrBuilder MIB = BuildMI(&MBB, dl, get(BccOpc));
lib/Target/ARM/ARMBaseInstrInfo.cpp 776 MachineInstrBuilder MIB =
796 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
808 void llvm::addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB) {
813 void llvm::addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB,
819 void llvm::addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond) {
824 void llvm::addPredicatedMveVpredROp(MachineInstrBuilder &MIB,
861 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
958 MachineInstrBuilder Mov;
1015 const MachineInstrBuilder &
1016 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
1087 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STRD));
1095 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::STMIA))
1124 auto MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::MVE_VSTRWU32));
1145 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
1170 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(),
1185 MachineInstrBuilder MIB = BuildMI(MBB, I, DebugLoc(), get(ARM::VSTMDIA))
1323 MachineInstrBuilder MIB;
1363 auto MIB = BuildMI(MBB, I, DL, get(ARM::MVE_VLDRWU32), DestReg);
1381 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1404 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1420 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1521 MachineInstrBuilder LDM, STM;
1615 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
2256 MachineInstrBuilder NewMI =
2513 MachineInstrBuilder MIB(MF, &*MI);
4778 MachineInstrBuilder MIB;
4932 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
5072 MachineInstrBuilder NewMIB;
lib/Target/ARM/ARMBaseInstrInfo.h 234 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
234 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
621 void addUnpredicatedMveVpredNOp(MachineInstrBuilder &MIB);
622 void addUnpredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned DestReg);
624 void addPredicatedMveVpredNOp(MachineInstrBuilder &MIB, unsigned Cond);
625 void addPredicatedMveVpredROp(MachineInstrBuilder &MIB, unsigned Cond,
lib/Target/ARM/ARMBaseRegisterInfo.cpp 648 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
lib/Target/ARM/ARMCallLowering.cpp 90 MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
184 MachineInstrBuilder &MIB;
239 MachineInstrBuilder &Ret) const {
272 auto Ret = MIRBuilder.buildInstrNoInsert(Opcode).add(predOps(ARMCC::AL));
475 MachineInstrBuilder MIB, CCAssignFn *AssignFn)
482 MachineInstrBuilder MIB;
517 auto CallSeqStart = MIRBuilder.buildInstr(ARM::ADJCALLSTACKDOWN);
523 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpcode);
lib/Target/ARM/ARMCallLowering.h 47 MachineInstrBuilder &Ret) const;
lib/Target/ARM/ARMConstantIslandPass.cpp 1918 MachineInstrBuilder MIB = BuildMI(*MBB, Br.MI, Br.MI->getDebugLoc(),
lib/Target/ARM/ARMExpandPseudoInsts.cpp 62 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
62 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
92 MachineInstrBuilder &UseMI,
93 MachineInstrBuilder &DefMI) {
479 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
590 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
667 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
752 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
837 MachineInstrBuilder LO16, HI16;
954 MachineInstrBuilder MIB =
967 MachineInstrBuilder MIB;
1035 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg,
1084 MachineInstrBuilder MIB;
1182 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
1396 MachineInstrBuilder MIB =
1411 MachineInstrBuilder MIB;
1452 MachineInstrBuilder MIB1 =
1457 MachineInstrBuilder MIB2 =
1504 MachineInstrBuilder MIB =
1512 MachineInstrBuilder MIB =
1543 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1553 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1575 MachineInstrBuilder MIB =
1588 MachineInstrBuilder MIB =
1619 MachineInstrBuilder MIB =
1929 MachineInstrBuilder MIB;
lib/Target/ARM/ARMFastISel.cpp 239 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
239 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB);
241 const MachineInstrBuilder &MIB,
283 const MachineInstrBuilder &
284 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) {
591 MachineInstrBuilder MIB;
612 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
623 MachineInstrBuilder MIB;
871 const MachineInstrBuilder &MIB,
1003 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1141 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1451 MachineInstrBuilder MIB;
2169 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2265 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2406 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
2721 MachineInstrBuilder MIB = BuildMI(
2802 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2969 MachineInstrBuilder MIB =
lib/Target/ARM/ARMFrameLowering.cpp 1024 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
1120 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
1137 MachineInstrBuilder MIB =
1228 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
lib/Target/ARM/ARMISelLowering.cpp 9557 MachineInstrBuilder MIB;
9847 MachineInstrBuilder MIB(*MF, &*II);
10212 MachineInstrBuilder MIB =
10469 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(NewOpc));
10697 MachineInstrBuilder MIB(*MF, MI);
lib/Target/ARM/ARMInstrInfo.cpp 121 MachineInstrBuilder MIB;
lib/Target/ARM/ARMInstructionSelector.cpp 46 bool selectCmp(CmpConstants Helper, MachineInstrBuilder &MIB,
59 bool selectGlobal(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
60 bool selectSelect(MachineInstrBuilder &MIB, MachineRegisterInfo &MRI) const;
61 bool selectShift(unsigned ShiftOpc, MachineInstrBuilder &MIB) const;
140 void renderVFPF32Imm(MachineInstrBuilder &New, const MachineInstr &Old) const;
141 void renderVFPF64Imm(MachineInstrBuilder &New, const MachineInstr &Old) const;
230 static bool selectMergeValues(MachineInstrBuilder &MIB,
261 static bool selectUnmergeValues(MachineInstrBuilder &MIB,
482 InsertInfo(MachineInstrBuilder &MIB)
526 MachineInstrBuilder &MIB,
578 auto CmpI =
588 auto ReadI = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc,
596 auto Mov1I = BuildMI(I.MBB, I.InsertBefore, I.DbgLoc,
608 bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB,
693 auto MIBLoad = BuildMI(MBB, InsertBefore, MIB->getDebugLoc(),
719 MachineInstrBuilder OffsetMIB;
766 bool ARMInstructionSelector::selectSelect(MachineInstrBuilder &MIB,
776 auto CmpI = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.TSTri))
791 auto Mov1I = BuildMI(MBB, InsertBefore, DbgLoc, TII.get(Opcodes.MOVCCr))
804 MachineInstrBuilder &MIB) const {
813 MachineInstrBuilder &NewInstBuilder, const MachineInstr &OldInst) const {
825 MachineInstrBuilder &NewInstBuilder, const MachineInstr &OldInst) const {
856 MachineInstrBuilder MIB{MF, I};
883 auto SubI =
932 auto MovI =
1105 auto AndI = BuildMI(MBB, InsertBefore, I.getDebugLoc(), TII.get(Opcodes.AND))
1140 auto Test =
1149 auto Branch =
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 789 MachineInstrBuilder MIB;
836 MachineInstrBuilder MIB = BuildMI(MBB, InsertBefore, DL,
949 MachineInstrBuilder MIB(*Merged->getParent()->getParent(), Merged);
1317 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc))
1541 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(NewOpc));
1628 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
1637 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MBBI->getDebugLoc(),
2329 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
2343 MachineInstrBuilder MIB = BuildMI(*MBB, InsertPos, dl, MCID)
lib/Target/ARM/ARMLowOverheadLoops.cpp 362 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
395 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
420 MachineInstrBuilder MIB = BuildMI(*MBB, MI, MI->getDebugLoc(),
433 MachineInstrBuilder MIB =
451 MachineInstrBuilder MIB =
470 MachineInstrBuilder MIB = BuildMI(*MBB, End, End->getDebugLoc(),
lib/Target/ARM/MLxExpansionPass.cpp 290 MachineInstrBuilder MIB = BuildMI(MBB, MI, MI->getDebugLoc(), MCID1, TmpReg)
lib/Target/ARM/MVEVPTBlockPass.cpp 231 MachineInstrBuilder MIBuilder;
lib/Target/ARM/Thumb1FrameLowering.cpp 637 MachineInstrBuilder MIB =
752 MachineInstrBuilder MIB =
851 MachineInstrBuilder MIB =
892 MachineInstrBuilder PushMIB = BuildMI(MF, DL, TII.get(ARM::tPUSH))
1002 MachineInstrBuilder PopMIB =
1021 MachineInstrBuilder MIB =
lib/Target/ARM/Thumb2ITBlockPass.cpp 214 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII->get(ARM::t2IT))
lib/Target/ARM/Thumb2InstrInfo.cpp 167 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2STRDi8));
208 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::t2LDRDi8));
353 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
493 MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
lib/Target/ARM/Thumb2SizeReduction.cpp 480 auto MIB = BuildMI(MBB, MI, dl, TII->get(Entry.NarrowOpc1))
582 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, TII->get(Opc));
650 MachineInstrBuilder MIB =
823 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
915 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
lib/Target/ARM/ThumbRegisterInfo.cpp 172 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
312 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg);
329 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg);
368 MachineInstrBuilder MIB(*MBB.getParent(), &MI);
464 MachineInstrBuilder MIB(*MBB.getParent(), &MI);
lib/Target/AVR/AVRExpandPseudoInsts.cpp 62 MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode) {
66 MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode,
157 auto MIBHI = buildMI(MBB, MBBI, OpHi)
185 auto MIBLO = buildMI(MBB, MBBI, Op)
193 auto MIBHI = buildMI(MBB, MBBI, Op)
233 auto MIBLO = buildMI(MBB, MBBI, Op)
243 auto MIBHI = buildMI(MBB, MBBI, Op)
281 auto MIBLO = buildMI(MBB, MBBI, AVR::SUBIRdK)
285 auto MIBHI = buildMI(MBB, MBBI, AVR::SBCIRdK)
338 auto MIBLO = buildMI(MBB, MBBI, OpLo)
346 auto MIBHI = buildMI(MBB, MBBI, OpHi)
398 auto MIBLO = buildMI(MBB, MBBI, OpLo)
405 auto MIBHI = buildMI(MBB, MBBI, OpHi)
435 auto MIBHI = buildMI(MBB, MBBI, OpHi)
463 auto MIBLO = buildMI(MBB, MBBI, OpLo)
470 auto MIBHI = buildMI(MBB, MBBI, OpHi)
494 auto MIBLO = buildMI(MBB, MBBI, OpLo)
497 auto MIBHI = buildMI(MBB, MBBI, OpHi)
543 auto MIBLO = buildMI(MBB, MBBI, OpLo)
546 auto MIBHI = buildMI(MBB, MBBI, OpHi)
597 auto MIBLO = buildMI(MBB, MBBI, OpLo)
606 auto MIBHI = buildMI(MBB, MBBI, OpHi)
640 auto MIBLO = buildMI(MBB, MBBI, OpLo)
645 auto MIBHI = buildMI(MBB, MBBI, OpHi)
671 auto MIBHI = buildMI(MBB, MBBI, OpHi)
676 auto MIBLO = buildMI(MBB, MBBI, OpLo)
713 auto MIBLO = buildMI(MBB, MBBI, OpLo)
723 auto MIBHI = buildMI(MBB, MBBI, OpHi)
763 auto MIBLO = buildMI(MBB, MBBI, OpLo)
772 auto MIBHI = buildMI(MBB, MBBI, OpHi)
978 auto MIBHI = buildMI(MBB, MBBI, OpHi);
979 auto MIBLO = buildMI(MBB, MBBI, OpLo);
1024 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1028 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1055 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1061 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1089 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1095 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1125 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1130 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1157 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1161 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1188 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1192 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1263 auto MIBHI = buildMI(MBB, MBBI, OpHi)
1295 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1338 auto MIBLO = buildMI(MBB, MBBI, OpLo)
1376 auto MOV = buildMI(MBB, MBBI, AVR::MOVRdRr)
1396 auto SBC = buildMI(MBB, MBBI, AVR::SBCRdRr)
1435 auto EOR = buildMI(MBB, MBBI, AVR::EORRdRr)
lib/Target/AVR/AVRISelLowering.cpp 1548 auto ShiftMI = BuildMI(LoopBB, dl, TII.get(Opc), ShiftReg2).addReg(ShiftReg);
lib/Target/AVR/AVRRelaxMemOperations.cpp 53 MachineInstrBuilder buildMI(Block &MBB, BlockIt MBBI, unsigned Opcode) {
lib/Target/BPF/BPFISelLowering.cpp 591 MachineInstrBuilder MIB(*MF, MI);
lib/Target/Hexagon/HexagonBitSimplify.cpp 2157 auto MIB = BuildMI(B, At, DL, HII.get(NewOpc), NewR)
2299 auto NewBS = BuildMI(B, At, DL, HII.get(Hexagon::A4_bitspliti), NewR)
2544 auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR)
3086 auto MIB = BuildMI(LB, At, DL, HII->get(SI->getOpcode()), NewDR);
lib/Target/Hexagon/HexagonConstExtenders.cpp 1627 MachineInstrBuilder MIB = BuildMI(MBB, At, dl, HII->get(RegOpc));
1673 MachineInstrBuilder MIB = BuildMI(MBB, At, dl, HII->get(RegOpc));
1799 MachineInstrBuilder MIB = BuildMI(MBB, At, dl, HII->get(IdxOpc));
lib/Target/Hexagon/HexagonConstPropagation.cpp 2875 const MachineInstrBuilder &MIB = BuildMI(B, At, DL, *NewD, NewR);
3152 auto NI = BuildMI(B, BrI.getIterator(), BrI.getDebugLoc(), JD)
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 722 MachineInstrBuilder MIB = BuildMI(*ToB, At, DL, HII->get(COpc));
923 MachineInstrBuilder MIB = BuildMI(*FP.SplitB, FP.SplitB->end(), DL, D);
lib/Target/Hexagon/HexagonExpandCondsets.cpp 639 MachineInstrBuilder MIB;
873 MachineInstrBuilder MB = BuildMI(B, Where, DL, HII->get(PredOpc));
lib/Target/Hexagon/HexagonFixupHwLoops.cpp 173 MachineInstrBuilder MIB;
lib/Target/Hexagon/HexagonGenMux.cpp 337 auto NewMux = BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR)
lib/Target/Hexagon/HexagonGenPredicate.cpp 422 MachineInstrBuilder MIB = BuildMI(B, MI, DL, TII->get(NewOpc), NewPR.R);
lib/Target/Hexagon/HexagonHardwareLoops.cpp 914 MachineInstrBuilder SubIB =
935 MachineInstrBuilder SubIB =
lib/Target/Hexagon/HexagonInstrInfo.cpp 1034 auto MIB = BuildMI(MBB, MI, DL, get(Opc)).add(MI.getOperand(0))
1266 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vcmov))
1275 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vncmov))
1302 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vccombine))
1314 auto T = BuildMI(MBB, MI, DL, get(Hexagon::V6_vnccombine))
1579 MachineInstrBuilder T = BuildMI(B, MI, DL, get(PredOpc));
lib/Target/Hexagon/HexagonOptAddrMode.cpp 491 MachineInstrBuilder MIB;
552 MachineInstrBuilder MIB;
636 MachineInstrBuilder MIB =
lib/Target/Lanai/LanaiInstrInfo.cpp 513 MachineInstrBuilder NewMI =
lib/Target/Lanai/LanaiMemAluCombiner.cpp 258 MachineInstrBuilder InstrBuilder =
lib/Target/Mips/MicroMipsSizeReduction.cpp 711 MachineInstrBuilder MIB = BuildMI(MBB, MI, dl, NewMCID);
lib/Target/Mips/Mips16InstrInfo.cpp 90 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
188 static void addSaveRestoreRegs(MachineInstrBuilder &MIB,
222 MachineInstrBuilder MIB;
252 MachineInstrBuilder MIB;
291 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
293 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
295 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
298 MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
lib/Target/Mips/MipsBranchExpansion.cpp 340 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
386 MachineInstrBuilder Instr =
484 MachineInstrBuilder BalInstr =
486 MachineInstrBuilder ADDiuInstr =
595 MachineInstrBuilder BalInstr =
597 MachineInstrBuilder DADDiuInstr =
lib/Target/Mips/MipsCallLowering.cpp 123 MachineInstrBuilder &MIB)
131 MachineInstrBuilder &MIB;
168 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
228 MachineInstrBuilder &MIB)
246 MachineInstrBuilder &MIB;
417 MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(Mips::RetRA);
521 MachineInstrBuilder Copy =
525 MachineInstrBuilder FrameIndex =
563 MachineInstrBuilder CallSeqStart =
569 MachineInstrBuilder MIB = MIRBuilder.buildInstrNoInsert(
lib/Target/Mips/MipsFastISel.cpp 210 MachineInstrBuilder emitInst(unsigned Opc) {
214 MachineInstrBuilder emitInst(unsigned Opc, unsigned DstReg) {
219 MachineInstrBuilder emitInstStore(unsigned Opc, unsigned SrcReg,
224 MachineInstrBuilder emitInstLoad(unsigned Opc, unsigned DstReg,
1561 MachineInstrBuilder MIB =
1774 MachineInstrBuilder MIB = emitInst(Mips::RetRA);
lib/Target/Mips/MipsISelLowering.cpp 1272 MachineInstrBuilder MIB;
lib/Target/Mips/MipsInstrInfo.cpp 110 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID);
593 MachineInstrBuilder
596 MachineInstrBuilder MIB;
lib/Target/Mips/MipsInstrInfo.h 148 MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
lib/Target/Mips/MipsInstructionSelector.cpp 488 MachineInstrBuilder MTC1 =
502 MachineInstrBuilder PairF64 = B.buildInstr(
691 MachineInstrBuilder MIB = B.buildInstr(
lib/Target/Mips/MipsLegalizerInfo.cpp 273 MachineInstrBuilder Bitcast = MIRBuilder.buildInstr(
279 MachineInstrBuilder TwoP52FP = MIRBuilder.buildFConstant(
285 MachineInstrBuilder ResF64 = MIRBuilder.buildFSub(s64, Bitcast, TwoP52FP);
lib/Target/Mips/MipsSEISelDAGToDAG.cpp 53 MachineInstrBuilder MIB(MF, &MI);
129 MachineInstrBuilder MIB(MF, &MI);
lib/Target/Mips/MipsSEISelLowering.cpp 3582 MachineInstrBuilder MIB =
lib/Target/Mips/MipsSEInstrInfo.cpp 174 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
680 MachineInstrBuilder MIB;
731 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
732 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
lib/Target/NVPTX/NVPTXPeephole.cpp 111 MachineInstrBuilder MIB =
lib/Target/PowerPC/PPCFastISel.cpp 576 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
722 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc))
1643 MachineInstrBuilder MIB;
1792 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
lib/Target/PowerPC/PPCFrameLowering.cpp 977 MachineInstrBuilder MIB =
1002 MachineInstrBuilder MIB =
2201 MachineInstrBuilder CRMIB;
lib/Target/PowerPC/PPCISelLowering.cpp10653 MachineInstrBuilder MIB;
10776 MachineInstrBuilder MIB;
lib/Target/PowerPC/PPCInstrBuilder.h 31 static inline const MachineInstrBuilder&
32 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0,
lib/Target/PowerPC/PPCReduceCRLogicals.cpp 98 MachineInstrBuilder MIB(*MI.getParent()->getParent(), &MI);
lib/Target/RISCV/RISCVCallLowering.cpp 28 MachineInstrBuilder Ret = MIRBuilder.buildInstrNoInsert(RISCV::PseudoRET);
lib/Target/Sparc/SparcInstrInfo.cpp 382 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(movOpc), Dst);
lib/Target/SystemZ/SystemZElimCompare.cpp 235 MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch);
299 auto MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), TII->get(Opcode));
563 MachineInstrBuilder MIB(*Branch->getParent()->getParent(), Branch);
lib/Target/SystemZ/SystemZFrameLowering.cpp 117 static void addSavedGPR(MachineBasicBlock &MBB, MachineInstrBuilder &MIB,
183 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::STMG));
261 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(SystemZ::LMG));
lib/Target/SystemZ/SystemZInstrBuilder.h 25 static inline const MachineInstrBuilder &
26 addFrameReference(const MachineInstrBuilder &MIB, int FI) {
lib/Target/SystemZ/SystemZInstrInfo.cpp 199 MachineInstrBuilder MIB =
245 MachineInstrBuilder
824 auto MIB = BuildMI(MBB, MBBI, DL, get(SystemZ::IPM), DestReg);
973 MachineInstrBuilder MIB =
1191 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
lib/Target/SystemZ/SystemZInstrInfo.h 177 MachineInstrBuilder
lib/Target/WebAssembly/WebAssemblyFastISel.cpp 155 void addLoadStoreOperands(const Address &Addr, const MachineInstrBuilder &MIB,
396 const MachineInstrBuilder &MIB,
869 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
1204 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1261 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc));
lib/Target/WebAssembly/WebAssemblyFixIrreducibleControlFlow.cpp 356 MachineInstrBuilder MIB =
lib/Target/X86/X86CallLowering.cpp 100 MachineInstrBuilder &MIB, CCAssignFn *AssignFn)
141 auto MIB = MIRBuilder.buildAnyExt(LLT::scalar(PhysRegSize), ValVReg);
178 MachineInstrBuilder &MIB;
192 auto MIB = MIRBuilder.buildInstrNoInsert(X86::RET).addImm(0);
274 auto Copy = MIRBuilder.buildCopy(LLT::scalar(PhysRegSize), PhysReg);
285 auto Copy = MIRBuilder.buildCopy(LLT{VA.getLocVT()}, PhysReg);
314 CCAssignFn *AssignFn, MachineInstrBuilder &MIB)
322 MachineInstrBuilder &MIB;
394 auto CallSeqStart = MIRBuilder.buildInstr(AdjStackDown);
403 auto MIB = MIRBuilder.buildInstrNoInsert(CallOpc)
lib/Target/X86/X86CmovConversion.cpp 696 MachineInstrBuilder MIB;
lib/Target/X86/X86CondBrFolding.cpp 226 MachineInstrBuilder MIB =
253 MachineInstrBuilder MIB = BuildMI(*MBB, BrMI, MBB->findDebugLoc(BrMI),
lib/Target/X86/X86DomainReassignment.cpp 154 MachineInstrBuilder Bld =
188 MachineInstrBuilder Bld = BuildMI(*MBB, MI, DL, TII->get(DstOpcode), Reg);
lib/Target/X86/X86ExpandPseudo.cpp 245 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
262 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, TII->get(Op));
311 MachineInstrBuilder MIB;
lib/Target/X86/X86FastISel.cpp 174 const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
174 const MachineInstrBuilder &addFullAddress(const MachineInstrBuilder &MIB,
225 const MachineInstrBuilder &
226 X86FastISel::addFullAddress(const MachineInstrBuilder &MIB,
470 MachineInstrBuilder MIB =
647 MachineInstrBuilder MIB =
683 MachineInstrBuilder MIB =
791 MachineInstrBuilder LoadMI =
1276 MachineInstrBuilder MIB;
2489 MachineInstrBuilder MIB;
2846 MachineInstrBuilder MIB;
3487 MachineInstrBuilder MIB;
3796 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
lib/Target/X86/X86FixupBWInsts.cpp 287 MachineInstrBuilder MIB =
322 MachineInstrBuilder MIB =
350 MachineInstrBuilder MIB =
lib/Target/X86/X86FlagsCopyLowering.cpp 744 auto SetI = BuildMI(TestMBB, TestPos, TestLoc,
769 auto TestI =
818 auto AddI =
1035 auto MIB = BuildMI(*SetCCI.getParent(), SetCCI.getIterator(),
lib/Target/X86/X86FrameLowering.cpp 346 MachineInstrBuilder X86FrameLowering::BuildStackAdjustment(
375 MachineInstrBuilder MI;
781 MachineInstrBuilder CI;
lib/Target/X86/X86FrameLowering.h 209 MachineInstrBuilder BuildStackAdjustment(MachineBasicBlock &MBB,
lib/Target/X86/X86ISelLowering.cpp29661 static MachineInstrBuilder createPHIsForCMOVsInSinkBB(
29681 MachineInstrBuilder MIB;
29847 MachineInstrBuilder MIB =
30208 MachineInstrBuilder CallseqStart =
30216 MachineInstrBuilder CallseqEnd =
30245 MachineInstrBuilder MIB =
30257 MachineInstrBuilder MIB =
30269 MachineInstrBuilder MIB =
30428 MachineInstrBuilder MIB;
30523 MachineInstrBuilder MIB;
30713 MachineInstrBuilder MIB =
30824 MachineInstrBuilder MIB;
30925 MachineInstrBuilder MIB = BuildMI(*MBB, MI, DL, TII->get(Op));
31140 MachineInstrBuilder MIB(*MF, &II);
lib/Target/X86/X86InsertPrefetch.cpp 215 MachineInstrBuilder MIB(MF, PFetch);
lib/Target/X86/X86InstrBuilder.h 123 static inline const MachineInstrBuilder &
124 addDirectMem(const MachineInstrBuilder &MIB, unsigned Reg) {
142 static inline const MachineInstrBuilder &
143 addOffset(const MachineInstrBuilder &MIB, int Offset) {
147 static inline const MachineInstrBuilder &
148 addOffset(const MachineInstrBuilder &MIB, const MachineOperand& Offset) {
156 static inline const MachineInstrBuilder &
157 addRegOffset(const MachineInstrBuilder &MIB,
164 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
164 static inline const MachineInstrBuilder &addRegReg(const MachineInstrBuilder &MIB,
171 static inline const MachineInstrBuilder &
172 addFullAddress(const MachineInstrBuilder &MIB,
197 static inline const MachineInstrBuilder &
198 addFrameReference(const MachineInstrBuilder &MIB, int FI, int Offset = 0) {
222 static inline const MachineInstrBuilder &
223 addConstantPoolReference(const MachineInstrBuilder &MIB, unsigned CPI,
lib/Target/X86/X86InstrInfo.cpp 803 MachineInstrBuilder MIB =
957 MachineInstrBuilder MIB =
993 MachineInstrBuilder MIB =
1016 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1059 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc)).add(Dest);
1100 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1141 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
1161 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(),
2461 auto MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opc));
3877 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
3898 static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
3906 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
3924 static bool ExpandMOVImmSExti8(MachineInstrBuilder &MIB,
3982 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4004 static bool expandXorFP(MachineInstrBuilder &MIB, const TargetInstrInfo &TII) {
4019 static bool expandNOVLXLoad(MachineInstrBuilder &MIB,
4042 static bool expandNOVLXStore(MachineInstrBuilder &MIB,
4064 static bool expandSHXDROT(MachineInstrBuilder &MIB, const MCInstrDesc &Desc) {
4079 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4608 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
4667 MachineInstrBuilder MIB(MF, NewMI);
4697 MachineInstrBuilder MIB(MF, NewMI);
4721 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5510 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), Reg);
5528 MachineInstrBuilder MIB(MF, DataMI);
5585 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
lib/Target/X86/X86InstructionSelector.cpp 536 MachineInstrBuilder MIB(MF, I);
572 MachineInstrBuilder MIB(MF, I);
624 MachineInstrBuilder MIB(MF, I);
lib/Target/X86/X86SpeculativeLoadHardening.cpp 253 auto BrBuilder =
481 auto ZeroI = BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::MOV32r0),
756 auto CMovI = BuildMI(CheckingMBB, InsertPt, DebugLoc(),
1109 auto AddrI = BuildMI(*Pred, InsertPt, DebugLoc(),
1117 auto AddrI = BuildMI(*Pred, InsertPt, DebugLoc(), TII->get(X86::LEA64r),
1148 auto CheckI = BuildMI(MBB, InsertPt, DebugLoc(), TII->get(X86::CMP64ri32))
1157 auto AddrI =
1167 auto CheckI = BuildMI(MBB, InsertPt, DebugLoc(), TII->get(X86::CMP64rr))
1179 auto CMovI =
1912 auto ShiftI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::SHL64ri), TmpReg)
1917 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), X86::RSP)
1936 auto ShiftI =
2049 auto MovI =
2058 auto BroadcastI = BuildMI(MBB, InsertPt, Loc,
2069 auto OrI =
2091 auto BroadcastI =
2102 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(OrOp), TmpReg)
2115 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), TmpReg)
2124 auto ShiftI =
2308 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(OrOpCode), NewReg)
2561 auto CMovI = BuildMI(MBB, InsertPt, Loc, TII->get(CMovOp), UpdatedStateReg)
lib/Target/XCore/XCoreFrameLowering.cpp 264 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
401 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode))
tools/llvm-exegesis/lib/Assembler.cpp 96 MachineInstrBuilder Builder = BuildMI(MBB, DL, MCID);
unittests/CodeGen/GlobalISel/CSETest.cpp 21 auto MIBInput = B.buildInstr(TargetOpcode::G_TRUNC, {s16}, {Copies[0]});
22 auto MIBInput1 = B.buildInstr(TargetOpcode::G_TRUNC, {s16}, {Copies[1]});
23 auto MIBAdd = B.buildInstr(TargetOpcode::G_ADD, {s16}, {MIBInput, MIBInput});
32 auto MIBAddCopy =
35 auto MIBAdd2 =
38 auto MIBAdd4 =
41 auto MIBAdd5 =
46 auto MIBCst = CSEB.buildConstant(s32, 0);
47 auto MIBCst1 = CSEB.buildConstant(s32, 0);
50 auto MIBCF1 = CSEB.buildInstr(TargetOpcode::G_ADD, {s32}, {MIBCst, MIBCst});
54 auto MIBFP0 = CSEB.buildFConstant(s32, 1.0);
55 auto MIBFP0_1 = CSEB.buildFConstant(s32, 1.0);
61 auto Splat0 = CSEB.buildConstant(LLT::vector(2, s32), 0);
66 auto FSplat = CSEB.buildFConstant(LLT::vector(2, s32), 1.0);
72 auto MIBUnmerge = CSEB.buildUnmerge({s32, s32}, Copies[0]);
73 auto MIBUnmerge2 = CSEB.buildUnmerge({s32, s32}, Copies[0]);
83 auto MIBInput = B.buildInstr(TargetOpcode::G_TRUNC, {s16}, {Copies[0]});
84 auto MIBAdd = B.buildInstr(TargetOpcode::G_ADD, {s16}, {MIBInput, MIBInput});
85 auto MIBZero = B.buildConstant(s16, 0);
92 auto MIBAdd1 =
98 auto MIBZeroTmp = CSEB.buildConstant(s16, 0);
unittests/CodeGen/GlobalISel/ConstantFoldingTest.cpp 28 auto MIBCAdd =
34 auto MIBCAdd1 =
46 auto MIBCSub =
54 auto MIBCSext1 =
62 auto MIBCSext2 =
77 auto MIBCst1 = B.buildConstant(s32, 16);
78 auto MIBCst2 = B.buildConstant(s32, 9);
79 auto MIBFCst1 = B.buildFConstant(s32, 1.0000001);
80 auto MIBFCst2 = B.buildFConstant(s32, 2.0);
unittests/CodeGen/GlobalISel/KnownBitsTest.cpp 128 auto SignBit = B.buildConstant(S32, 0x80000000);
129 auto Zero = B.buildConstant(S32, 0);
unittests/CodeGen/GlobalISel/LegalizerHelperTest.cpp 38 auto MIBCTTZ =
70 auto MIBCTTZ =
104 auto MIBCTTZ =
138 auto MIBTrunc = B.buildTrunc(s8, Copies[0]);
139 auto MIBCTPOP = B.buildInstr(TargetOpcode::G_CTPOP, {s16}, {MIBTrunc});
171 auto MIBTrunc = B.buildTrunc(s8, Copies[0]);
172 auto MIBCTPOP = B.buildInstr(TargetOpcode::G_CTPOP, {s32}, {MIBTrunc});
200 auto MIBCTTZ = B.buildInstr(TargetOpcode::G_CTTZ_ZERO_UNDEF,
227 auto MIBCTLZ =
258 auto MIBCTLZ =
291 auto MIBTrunc = B.buildTrunc(s8, Copies[0]);
292 auto MIBCTLZ = B.buildInstr(TargetOpcode::G_CTLZ, {s8}, {MIBTrunc});
333 auto MIBTrunc = B.buildTrunc(s8, Copies[0]);
334 auto MIBCTLZ = B.buildInstr(TargetOpcode::G_CTLZ, {s8}, {MIBTrunc});
368 auto MIBTrunc = B.buildTrunc(s8, Copies[0]);
369 auto MIBCTLZ_ZU =
404 auto MIBTrunc = B.buildTrunc(s8, Copies[0]);
405 auto MIBCTPOP = B.buildInstr(TargetOpcode::G_CTPOP, {s8}, {MIBTrunc});
437 auto MIBTrunc = B.buildTrunc(s8, Copies[0]);
438 auto MIBCTTZ_ZERO_UNDEF =
471 auto MIBTrunc = B.buildTrunc(s8, Copies[0]);
472 auto MIBCTTZ = B.buildInstr(TargetOpcode::G_CTTZ, {s8}, {MIBTrunc});
505 auto MIBTrunc = B.buildTrunc(s8, Copies[0]);
507 auto MIBUAddO =
544 auto MIBTrunc = B.buildTrunc(s8, Copies[0]);
546 auto MIBUSUBO =
582 auto Op0 = B.buildUndef(V5S32);
583 auto Op1 = B.buildUndef(V5S32);
584 auto And = B.buildAnd(V5S32, Op0, Op1);
635 auto Val0 = B.buildBitcast(v2s32, Copies[0]);
636 auto Val1 = B.buildBitcast(v2s32, Copies[1]);
638 auto And = B.buildAnd(v2s32, Val0, Val1);
687 auto InitVal = B.buildUndef(PhiTy);
688 auto InitOtherVal = B.buildConstant(s64, 999);
690 auto ICmp = B.buildICmp(CmpInst::ICMP_EQ, s1, Copies[0], Copies[1]);
696 auto MidVal = B.buildUndef(PhiTy);
697 auto MidOtherVal = B.buildConstant(s64, 345);
701 auto Phi = B.buildInstr(TargetOpcode::G_PHI)
762 auto FAdd =
767 auto FNeg0 =
772 auto FNeg1 =
809 auto SMin = B.buildSMin(s64, Copies[0], Copies[1]);
810 auto SMax = B.buildSMax(s64, Copies[0], Copies[1]);
811 auto UMin = B.buildUMin(s64, Copies[0], Copies[1]);
812 auto UMax = B.buildUMax(s64, Copies[0], Copies[1]);
814 auto VecVal0 = B.buildBitcast(v2s32, Copies[0]);
815 auto VecVal1 = B.buildBitcast(v2s32, Copies[1]);
817 auto SMinV = B.buildSMin(v2s32, VecVal0, VecVal1);
818 auto SMaxV = B.buildSMax(v2s32, VecVal0, VecVal1);
819 auto UMinV = B.buildUMin(v2s32, VecVal0, VecVal1);
820 auto UMaxV = B.buildUMax(v2s32, VecVal0, VecVal1);
896 auto BV0 = B.buildBuildVector(V2S16, {Constant0, Constant1});
897 auto BV1 = B.buildBuildVector(V2S16, {Constant0, Constant1});
951 auto Merge0 = B.buildMerge(S24, Merge0Ops);
960 auto Merge1 = B.buildMerge(S21, Merge1Ops);
966 auto Merge2 = B.buildMerge(S16, Merge2Ops);
1037 auto Lo = B.buildTrunc(S32, Copies[0]);
1038 auto Hi = B.buildTrunc(S32, Copies[1]);
1040 auto Merge = B.buildMerge(P0, {Lo.getReg(0), Hi.getReg(0)});
1068 auto MIB = B.buildInstr(
1099 auto MIB = B.buildInstr(
1129 auto MIB = B.buildInstr(
1161 auto MIB = B.buildInstr(
unittests/CodeGen/GlobalISel/MachineIRBuilderTest.cpp 85 auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
201 auto Merge = B.buildMerge(S128, {Copies[0], Copies[1]});
312 auto Ptr = B.buildUndef(P0);
unittests/CodeGen/GlobalISel/PatternMatchTest.cpp 37 auto MIBCst = B.buildConstant(LLT::scalar(64), 42);
49 auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
62 auto MIBMul = B.buildMul(s64, MIBAdd, Copies[2]);
80 auto MIBMul2 = B.buildMul(s64, Copies[0], B.buildConstant(s64, 42));
91 auto MIBSub = B.buildSub(s64, Copies[0], B.buildConstant(s64, 42));
96 auto MIBFMul = B.buildInstr(TargetOpcode::G_FMUL, {s64},
106 auto MIBFSub = B.buildInstr(TargetOpcode::G_FSUB, {s64},
114 auto MIBAnd = B.buildAnd(s64, Copies[0], Copies[1]);
123 auto MIBOr = B.buildOr(s64, Copies[0], Copies[1]);
139 auto Copy0s32 = B.buildFPTrunc(s32, Copies[0]);
142 auto MIBFabs = B.buildInstr(TargetOpcode::G_FABS, {s32}, {Copy0s32});
148 auto MIBFNeg = B.buildInstr(TargetOpcode::G_FNEG, {s32}, {Copy0s32});
158 auto MIBFCst = B.buildFConstant(s32, .5);
169 auto MIBFCst64 = B.buildFConstant(s64, .5);
181 auto MIBFCst16 = B.buildFConstant(s16, .5);
202 auto MIBTrunc = B.buildTrunc(s32, Copies[0]);
203 auto MIBAExt = B.buildAnyExt(s64, MIBTrunc);
204 auto MIBZExt = B.buildZExt(s64, MIBTrunc);
205 auto MIBSExt = B.buildSExt(s64, MIBTrunc);
249 auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
257 auto MIBCast = B.buildCast(v2s32, Copies[0]);
267 auto MIBIntToPtr = B.buildCast(PtrTy, Copies[0]);
268 auto MIBPtrToInt = B.buildCast(s64, MIBIntToPtr);
285 auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
318 auto MIBAdd = B.buildAdd(s64, Copies[0], Copies[1]);
usr/include/c++/7.4.0/bits/move.h 72 constexpr _Tp&&
73 forward(typename std::remove_reference<_Tp>::type& __t) noexcept
83 constexpr _Tp&&
84 forward(typename std::remove_reference<_Tp>::type&& __t) noexcept
98 move(_Tp&& __t) noexcept
usr/include/c++/7.4.0/bits/std_function.h 314 _M_invoke(const _Any_data& __functor, _ArgTypes&&... __args)
628 using _Invoker_type = _Res (*)(const _Any_data&, _ArgTypes&&...);
usr/include/c++/7.4.0/type_traits 215 : public __is_void_helper<typename remove_cv<_Tp>::type>::type
326 : public __is_integral_helper<typename remove_cv<_Tp>::type>::type
354 : public __is_floating_point_helper<typename remove_cv<_Tp>::type>::type
381 : public __is_pointer_helper<typename remove_cv<_Tp>::type>::type
567 : public __is_null_pointer_helper<typename remove_cv<_Tp>::type>::type
581 : public __or_<is_lvalue_reference<_Tp>,
582 is_rvalue_reference<_Tp>>::type
588 : public __or_<is_integral<_Tp>, is_floating_point<_Tp>>::type
588 : public __or_<is_integral<_Tp>, is_floating_point<_Tp>>::type
601 : public __not_<__or_<is_function<_Tp>, is_reference<_Tp>,
601 : public __not_<__or_<is_function<_Tp>, is_reference<_Tp>,
602 is_void<_Tp>>>::type
611 : public __or_<is_arithmetic<_Tp>, is_enum<_Tp>, is_pointer<_Tp>,
611 : public __or_<is_arithmetic<_Tp>, is_enum<_Tp>, is_pointer<_Tp>,
611 : public __or_<is_arithmetic<_Tp>, is_enum<_Tp>, is_pointer<_Tp>,
612 is_member_pointer<_Tp>, is_null_pointer<_Tp>>::type
612 is_member_pointer<_Tp>, is_null_pointer<_Tp>>::type
631 : public __is_member_pointer_helper<typename remove_cv<_Tp>::type>::type
638 : public __or_<is_object<_Tp>, is_reference<_Tp>>::type
638 : public __or_<is_object<_Tp>, is_reference<_Tp>>::type
777 : public __and_<is_array<_Tp>, __not_<extent<_Tp>>>
777 : public __and_<is_array<_Tp>, __not_<extent<_Tp>>>
798 typedef decltype(__test<_Tp>(0)) type;
811 remove_all_extents<_Tp>::type>::type
825 : public __is_destructible_safe<_Tp>::type
984 typedef decltype(__test<_Tp, _Arg>(0)) type;
989 : public __and_<is_destructible<_Tp>,
990 __is_direct_constructible_impl<_Tp, _Arg>>
1072 __is_direct_constructible_ref_cast<_Tp, _Arg>,
1073 __is_direct_constructible_new_safe<_Tp, _Arg>
1079 : public __is_direct_constructible_new<_Tp, _Arg>::type
1119 : public __is_direct_constructible<_Tp, _Arg>
1130 : public __is_constructible_impl<_Tp, _Args...>::type
1142 : public is_constructible<_Tp, const _Tp&>
1142 : public is_constructible<_Tp, const _Tp&>
1148 : public __is_copy_constructible_impl<_Tp>
1160 : public is_constructible<_Tp, _Tp&&>
1160 : public is_constructible<_Tp, _Tp&&>
1166 : public __is_move_constructible_impl<_Tp>
1554 { typedef _Tp type; };
1563 { typedef _Tp type; };
1574 remove_const<typename remove_volatile<_Tp>::type>::type type;
1629 { typedef _Tp type; };
1633 { typedef _Tp type; };
1659 { typedef _Tp&& type; };
1955 { typedef _Tp type; };