reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h
  824       OutMIs[InsnID].addDef(RegNum, RegState::Implicit);
  835       OutMIs[InsnID].addUse(RegNum, RegState::Implicit);
include/llvm/CodeGen/MachineInstrBuilder.h
   54     ImplicitDefine = Implicit | Define,
   55     ImplicitKill   = Implicit | Kill
   94                                                flags & RegState::Implicit,
  474   return B ? RegState::Implicit : 0;
lib/CodeGen/IfConversion.cpp
 1500         MIB.addReg(Reg, RegState::Implicit);
 1507       MIB.addReg(Reg, RegState::Implicit | RegState::Define);
 1511       MIB.addReg(Reg, RegState::Implicit);
 1521         MIB.addReg(Reg, RegState::Implicit);
lib/CodeGen/MIRParser/MIParser.cpp
 1290     Flags |= RegState::Implicit;
 1470       Reg, Flags & RegState::Define, Flags & RegState::Implicit,
lib/Target/AArch64/AArch64CallLowering.cpp
  124     MIB.addDef(PhysReg, RegState::Implicit);
  171     MIB.addUse(PhysReg, RegState::Implicit);
  365     MIB.addUse(AArch64::X21, RegState::Implicit);
  889       MIB.addReg(ForwardedReg, RegState::Implicit);
 1013     MIB.addDef(AArch64::X21, RegState::Implicit);
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
  212       .addReg(AArch64::NZCV, RegState::Implicit | RegState::Kill);
  511                    .addReg(DstReg, DstFlags | RegState::Implicit);
lib/Target/AArch64/AArch64FastISel.cpp
 3308     MIB.addReg(Reg, RegState::Implicit);
 3936     MIB.addReg(RetReg, RegState::Implicit);
lib/Target/AArch64/AArch64FrameLowering.cpp
 1058           .addReg(AArch64::X15, RegState::Implicit)
 1059           .addReg(AArch64::X16, RegState::Implicit | RegState::Define | RegState::Dead)
 1060           .addReg(AArch64::X17, RegState::Implicit | RegState::Define | RegState::Dead)
 1061           .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define | RegState::Dead)
 1083           .addReg(AArch64::X15, RegState::Implicit | RegState::Define)
 1084           .addReg(AArch64::X16, RegState::Implicit | RegState::Define | RegState::Dead)
 1085           .addReg(AArch64::X17, RegState::Implicit | RegState::Define | RegState::Dead)
 1086           .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define | RegState::Dead)
lib/Target/AArch64/AArch64InstrInfo.cpp
 1518           .addDef(Reg, RegState::Implicit);
 1560           .addDef(Reg, RegState::Implicit);
 2486             .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
 2511             .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
 2767         .addReg(AArch64::NZCV, RegState::Implicit | RegState::Define);
 2775         .addReg(AArch64::NZCV, RegState::Implicit | getKillRegState(KillSrc));
lib/Target/AArch64/AArch64InstructionSelector.cpp
 2390       .addDef(AArch64::X0, RegState::Implicit)
lib/Target/AMDGPU/AMDGPUCallLowering.cpp
   63     MIB.addUse(PhysReg, RegState::Implicit);
lib/Target/AMDGPU/R600InstrInfo.cpp
   85                                       RegState::Define | RegState::Implicit);
  990     MIB.addReg(R600::PREDICATE_BIT, RegState::Implicit);
  998     MIB.addReg(R600::PREDICATE_BIT, RegState::Implicit);
 1140                                            RegState::Implicit | RegState::Kill);
 1173                                            RegState::Implicit | RegState::Kill);
lib/Target/AMDGPU/SIAddIMGInit.cpp
  168           MachineInstrBuilder(MF, MI).addReg(NewDst, RegState::Implicit);
lib/Target/AMDGPU/SIFormMemoryClauses.cpp
  138     S |= RegState::Implicit;
lib/Target/AMDGPU/SIISelLowering.cpp
 3419         .addReg(SrcReg, RegState::Implicit)
 3420         .addReg(AMDGPU::M0, RegState::Implicit);
 3425         .addReg(SrcReg, RegState::Implicit);
 3448       .addReg(SrcReg, RegState::Implicit)
 3449       .addReg(AMDGPU::M0, RegState::Implicit);
 3454       .addReg(SrcReg, RegState::Implicit);
 3528           .addReg(SrcVec->getReg(), RegState::Implicit)
 3529           .addReg(AMDGPU::M0, RegState::Implicit);
 3562         .addReg(PhiReg, RegState::Implicit)
 3563         .addReg(AMDGPU::M0, RegState::Implicit);
 3805         .addReg(Info->getStackPtrOffsetReg(), RegState::Implicit)
 3806         .addReg(Info->getFrameOffsetReg(), RegState::Implicit);
lib/Target/AMDGPU/SIInstrInfo.cpp
  726       Builder.addReg(DestReg, RegState::Define | RegState::Implicit);
  729     Builder.addReg(SrcReg, getKillRegState(UseKill) | RegState::Implicit);
 1081       .addReg(MFI->getScratchRSrcReg(), RegState::Implicit)
 1082       .addReg(MFI->getStackPtrOffsetReg(), RegState::Implicit);
 1207       .addReg(MFI->getScratchRSrcReg(), RegState::Implicit)
 1208       .addReg(MFI->getStackPtrOffsetReg(), RegState::Implicit);
 1430         .addReg(Dst, RegState::Implicit | RegState::Define);
 1433         .addReg(Dst, RegState::Implicit | RegState::Define);
 1438         .addReg(Dst, RegState::Implicit | RegState::Define);
 1441         .addReg(Dst, RegState::Implicit | RegState::Define);
 1493                     RegState::Implicit | (IsUndef ? RegState::Undef : 0));
 6554         .addReg(AMDGPU::EXEC, RegState::Implicit);
lib/Target/AMDGPU/SIRegisterInfo.cpp
  734       MIB.addReg(ValueReg, RegState::Implicit | SrcDstRegState);
  834         Mov.addReg(SuperReg, RegState::Implicit | SuperKillState);
lib/Target/ARC/ARCFrameLowering.cpp
  167         .addReg(ARC::BLINK, RegState::Implicit | RegState::Kill);
  297         .addReg(ARC::BLINK, RegState::Implicit | RegState::Kill);
lib/Target/ARM/ARMBaseInstrInfo.cpp
  785      .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
  805      .addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
  821   MIB.addReg(ARM::VPR, RegState::Implicit);
 1634   MIB.addReg(SrcRegS, RegState::Implicit);
 4987     MIB.addReg(SrcReg, RegState::Implicit);
 5018     MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
 5020       MIB.addReg(ImplicitSReg, RegState::Implicit);
 5053         MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
 5054         MIB.addReg(SrcReg, RegState::Implicit);
 5056           MIB.addReg(ImplicitSReg, RegState::Implicit);
 5090         NewMIB.addReg(SrcReg, RegState::Implicit);
 5108         MIB.addReg(SrcReg, RegState::Implicit);
 5112       MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
 5114         MIB.addReg(ImplicitSReg, RegState::Implicit);
lib/Target/ARM/ARMCallLowering.cpp
  125     MIB.addUse(PhysReg, RegState::Implicit);
  479     MIB.addDef(PhysReg, RegState::Implicit);
lib/Target/ARM/ARMExpandPseudoInsts.cpp
  645     MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
  777   MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
lib/Target/ARM/ARMFastISel.cpp
 2173     MIB.addReg(R, RegState::Implicit);
 2277     MIB.addReg(R, RegState::Implicit);
 2421     MIB.addReg(R, RegState::Implicit);
lib/Target/ARM/ARMFrameLowering.cpp
  540           .addReg(ARM::R4, RegState::Implicit)
  551           .addReg(ARM::R4, RegState::Implicit)
lib/Target/ARM/ARMISelLowering.cpp
10292         .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
10293         .addReg(ARM::R4, RegState::Implicit | RegState::Define)
10295                 RegState::Implicit | RegState::Define | RegState::Dead)
10297                 RegState::Implicit | RegState::Define | RegState::Dead);
10308         .addReg(ARM::R4, RegState::Implicit | RegState::Kill)
10309         .addReg(ARM::R4, RegState::Implicit | RegState::Define)
10311                 RegState::Implicit | RegState::Define | RegState::Dead)
10313                 RegState::Implicit | RegState::Define | RegState::Dead);
lib/Target/Hexagon/HexagonExpandCondsets.cpp
  520       MachineInstrBuilder(MF, DefI).addReg(R.Reg, RegState::Implicit, R.Sub);
lib/Target/Hexagon/HexagonInstrInfo.cpp
 1038     MIB.addReg(CSx, RegState::Implicit);
 1271           T.addReg(Op0.getReg(), RegState::Implicit);
 1280           T.addReg(Op0.getReg(), RegState::Implicit);
 1308           T.addReg(Op0.getReg(), RegState::Implicit);
 1320           T.addReg(Op0.getReg(), RegState::Implicit);
 4273     PredRegFlags = RegState::Implicit;
lib/Target/Mips/MipsCallLowering.cpp
  128     MIB.addDef(PhysReg, RegState::Implicit);
  283     MIB.addUse(PhysReg, RegState::Implicit);
  571   MIB.addDef(Mips::SP, RegState::Implicit);
  635     MIB.addDef(Mips::GP, RegState::Implicit);
lib/Target/Mips/MipsFastISel.cpp
 1567     MIB.addReg(Reg, RegState::Implicit);
 1776     MIB.addReg(RetRegs[i], RegState::Implicit);
lib/Target/Mips/MipsISelLowering.cpp
 1531                            RegState::Implicit | RegState::Dead);
 1704                            RegState::Dead | RegState::Implicit)
 1706                             RegState::Dead | RegState::Implicit)
 1708                             RegState::Dead | RegState::Implicit);
 1770                            RegState::Dead | RegState::Implicit);
 1892                            RegState::Dead | RegState::Implicit)
 1894                             RegState::Dead | RegState::Implicit);
lib/Target/Mips/MipsSEISelDAGToDAG.cpp
   56       IsDef ? RegState::ImplicitDefine : RegState::Implicit | RegState::Undef;
  137     MIB.addUse(Mips::AT_64, RegState::Implicit);
  150     MIB.addUse(Mips::AT, RegState::Implicit);
lib/Target/Mips/MipsSEInstrInfo.cpp
  112         .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
lib/Target/PowerPC/PPCFastISel.cpp
 1668     MIB.addReg(RegArgs[II], RegState::Implicit);
 1673   MIB.addReg(PPC::X2, RegState::Implicit);
 1796     MIB.addReg(RetRegs[i], RegState::Implicit);
lib/Target/PowerPC/PPCRegisterInfo.cpp
  789               RegState::Implicit | getKillRegState(MI.getOperand(0).isKill()));
  854       .addReg(getCRFromCRBit(DestReg), RegState::Implicit);
lib/Target/SystemZ/SystemZInstrInfo.cpp
   89     unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
  729       .addReg(SystemZ::CC, RegState::Implicit);
  736       .addReg(SystemZ::CC, RegState::Implicit);
  750         .addReg(SystemZ::CC, RegState::Implicit);
  760       .addReg(SystemZ::CC, RegState::Implicit);
  777       .addReg(SrcReg, RegState::Implicit);
  781       .addReg(SrcReg, (getKillRegState(KillSrc) | RegState::Implicit));
lib/Target/X86/X86CallLowering.cpp
  126     MIB.addUse(PhysReg, RegState::Implicit);
  318     MIB.addDef(PhysReg, RegState::Implicit);
  441     MIB.addUse(X86::AL, RegState::Implicit);
lib/Target/X86/X86FastISel.cpp
 1286     MIB.addReg(RetRegs[i], RegState::Implicit);
 3525     MIB.addReg(X86::EBX, RegState::Implicit);
 3528     MIB.addReg(X86::AL, RegState::Implicit);
 3532     MIB.addReg(Reg, RegState::Implicit);
lib/Target/X86/X86FixupBWInsts.cpp
  325           .addReg(OldSrc.getReg(), RegState::Implicit);
lib/Target/X86/X86FixupLEAs.cpp
  397         .addReg(Base.getReg(), RegState::Implicit)
  398         .addReg(Index.getReg(), RegState::Implicit);
  417           .addReg(BaseReg).addReg(Base.getReg(), RegState::Implicit);
  428           .addReg(Base.getReg(), RegState::Implicit);
  586                   .addReg(Base.getReg(), RegState::Implicit)
  587                   .addReg(Index.getReg(), RegState::Implicit);
lib/Target/X86/X86FrameLowering.cpp
  799   CI.addReg(AX, RegState::Implicit)
  800       .addReg(SP, RegState::Implicit)
  801       .addReg(AX, RegState::Define | RegState::Implicit)
  802       .addReg(SP, RegState::Define | RegState::Implicit)
  803       .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit);
lib/Target/X86/X86ISelLowering.cpp
30097       .addReg(X86::RDI, RegState::Implicit)
30105       .addReg(X86::EDI, RegState::Implicit)
30406       .addReg(AvailableReg, RegState::Implicit | RegState::Kill);
lib/Target/X86/X86InstrInfo.cpp
 2474     MIB.addReg(C.first, RegState::Implicit);
 2475     MIB.addReg(C.first, RegState::Implicit | RegState::Define);
 5541                RegState::Implicit |