|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
include/llvm/CodeGen/MachineInstrBuilder.h 371 return BuildMI(BB, *I, DL, MCID, DestReg);
lib/CodeGen/ModuloSchedule.cpp 1437 BuildMI(*BB, MI, DebugLoc(), TII->get(TargetOpcode::PHI), R)
lib/CodeGen/TailDuplicator.cpp 437 BuildMI(*PredBB, NewMI, NewMI.getDebugLoc(),
lib/Target/AArch64/AArch64AdvSIMDScalarPass.cpp 276 MachineInstrBuilder MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
362 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), Dst)
lib/Target/AArch64/AArch64CleanupLocalDynamicTLSPass.cpp 104 MachineInstr *Copy = BuildMI(*I.getParent(), I, I.getDebugLoc(),
lib/Target/AArch64/AArch64CondBrTuning.cpp 105 MachineInstrBuilder MIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
lib/Target/AArch64/AArch64InstrInfo.cpp 1509 BuildMI(MBB, MI, DL, get(AArch64::LOADgot), Reg)
1520 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1527 BuildMI(MBB, MI, DL, get(AArch64::MOVZXi), Reg)
1530 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1534 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1538 BuildMI(MBB, MI, DL, get(AArch64::MOVKXi), Reg)
1542 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
1547 BuildMI(MBB, MI, DL, get(AArch64::ADR), Reg)
1550 BuildMI(MBB, MI, DL, get(AArch64::ADRP), Reg)
1562 BuildMI(MBB, MI, DL, get(AArch64::LDRXui), Reg)
lib/Target/AArch64/AArch64InstructionSelector.cpp 725 BuildMI(*I.getParent(), I, I.getDebugLoc(),
2296 auto MovMI = BuildMI(MBB, I, I.getDebugLoc(), TII.get(AArch64::MOVaddrBA),
2993 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(TargetOpcode::IMPLICIT_DEF),
2999 *BuildMI(MBB, I, I.getDebugLoc(),
3027 *BuildMI(MBB, I, I.getDebugLoc(), TII.get(CopyOpc), CopyTo)
lib/Target/AArch64/AArch64RegisterInfo.cpp 506 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(AArch64::LDG), ScratchReg)
lib/Target/AArch64/AArch64SIMDInstrOpt.cpp 446 BuildMI(MBB, MI, DL, *DupMCID, DupDest)
450 BuildMI(MBB, MI, DL, *MulMCID, MulDest)
458 BuildMI(MBB, MI, DL, *DupMCID, DupDest)
462 BuildMI(MBB, MI, DL, *MulMCID, MulDest)
562 BuildMI(MBB, MI, DL, *ReplInstrMCID[0], ZipDest[0])
565 BuildMI(MBB, MI, DL, *ReplInstrMCID[1], ZipDest[1])
584 BuildMI(MBB, MI, DL, *ReplInstrMCID[0], ZipDest[0])
587 BuildMI(MBB, MI, DL, *ReplInstrMCID[1], ZipDest[1])
590 BuildMI(MBB, MI, DL, *ReplInstrMCID[2], ZipDest[2])
593 BuildMI(MBB, MI, DL, *ReplInstrMCID[3], ZipDest[3])
596 BuildMI(MBB, MI, DL, *ReplInstrMCID[4], ZipDest[4])
599 BuildMI(MBB, MI, DL, *ReplInstrMCID[5], ZipDest[5])
602 BuildMI(MBB, MI, DL, *ReplInstrMCID[6], ZipDest[6])
605 BuildMI(MBB, MI, DL, *ReplInstrMCID[7], ZipDest[7])
lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp 1246 BuildMI(MBB, I, DL, TII.get(AMDGPU::COPY), TmpReg)
1248 BuildMI(MBB, I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
1252 BuildMI(MBB, I, DL, TII.get(Opcode), DstReg)
1264 BuildMI(MBB, I, DL, TII.get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
1284 BuildMI(MBB, I, DL, TII.get(AMDGPU::V_AND_B32_e32), DstReg)
1293 BuildMI(MBB, I, DL, TII.get(BFE), DstReg)
1308 BuildMI(MBB, I, DL, TII.get(SextOpc), DstReg)
1322 BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg);
1323 BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), ExtReg)
1329 BuildMI(MBB, I, DL, TII.get(BFE64), DstReg)
1339 BuildMI(MBB, I, DL, TII.get(AMDGPU::S_AND_B32), DstReg)
1343 BuildMI(MBB, I, DL, TII.get(BFE32), DstReg)
1382 BuildMI(*MBB, I, DL, TII.get(AMDGPU::COPY), AMDGPU::SCC)
1387 auto MIB = BuildMI(*MBB, I, DL, TII.get(NewOpc), DstReg)
lib/Target/AMDGPU/AMDGPUMachineCFGStructurizer.cpp 1485 BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
1530 BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
1579 BuildMI(*MBB, PHI, PHI.getDebugLoc(), TII->get(TargetOpcode::PHI),
lib/Target/AMDGPU/GCNDPPCombine.cpp 437 auto UndefInst = BuildMI(*MovMI.getParent(), MovMI, MovMI.getDebugLoc(),
lib/Target/AMDGPU/SIAddIMGInit.cpp 144 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), PrevDst)
148 BuildMI(MBB, MI, DL, TII->get(AMDGPU::IMPLICIT_DEF), PrevDst);
155 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), SubReg)
lib/Target/AMDGPU/SIFixSGPRCopies.cpp 625 BuildMI(MBB, MI, MI.getDebugLoc(),
740 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
lib/Target/AMDGPU/SIISelLowering.cpp 3631 BuildMI(*BB, MI, DL, TII->get(LoOpc), DestSub0)
3634 BuildMI(*BB, MI, DL, TII->get(HiOpc), DestSub1)
3637 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest.getReg())
3764 BuildMI(*BB, MI, DL, TII->get(AMDGPU::COPY), SrcCondCopy)
3766 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
3772 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
3779 BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst)
3816 MIB = BuildMI(*BB, MI, DL, TII->get(AMDGPU::SI_CALL), ReturnAddrReg);
3838 auto I = BuildMI(*BB, MI, DL, TII->get(Opc), MI.getOperand(0).getReg());
10457 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
lib/Target/AMDGPU/SIInsertWaitcnts.cpp 1430 BuildMI(Block, Inst, Inst.getDebugLoc(),
lib/Target/AMDGPU/SIInstrInfo.cpp 1428 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1431 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1436 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstLo)
1439 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DstHi)
1453 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1455 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), MI.getOperand(0).getReg())
1457 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1465 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1467 MachineInstr *Copy = BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO),
1471 BuildMI(MBB, MI, DL, get(NotOpc), Exec)
1611 BuildMI(MBB, MI, DL, get(AMDGPU::REG_SEQUENCE), Dst)
4038 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4045 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4071 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4142 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4148 BuildMI(*MI.getParent(), MI, DL, get(AMDGPU::V_READFIRSTLANE_B32), Reg)
4221 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
4228 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
4237 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
4244 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(),
4490 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B64), Zero64)
4494 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), SRsrcFormatLo)
4498 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::S_MOV_B32), SRsrcFormatHi)
4502 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(AMDGPU::REG_SEQUENCE), NewSRsrc)
4711 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADD_I32_e64), NewVAddrLo)
4718 BuildMI(MBB, MI, DL, get(AMDGPU::V_ADDC_U32_e64), NewVAddrHi)
4726 BuildMI(MBB, MI, MI.getDebugLoc(), get(AMDGPU::REG_SEQUENCE), NewVAddr)
4950 BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(AMDGPU::S_AND_B32),
4955 BuildMI(*MBB, Inst, Inst.getDebugLoc(), get(AMDGPU::S_AND_B64),
5668 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
5671 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_B32_e64), TmpReg)
5675 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHL_OR_B32), ResultReg)
5683 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
5685 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_BFI_B32), ResultReg)
5694 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_LSHRREV_B32_e64), TmpReg)
5697 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_MOV_B32_e32), ImmReg)
5699 BuildMI(*MBB, Inst, DL, get(AMDGPU::V_AND_OR_B32), ResultReg)
lib/Target/AMDGPU/SILowerI1Copies.cpp 525 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
704 BuildMI(MBB, MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64), TmpReg)
lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp 259 BuildMI(MBB, *And, And->getDebugLoc(), TII->get(Andn2Opc),
lib/Target/AMDGPU/SIRegisterInfo.cpp 1125 BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64),
1146 BuildMI(*MBB, *MIB, DL, TII->get(AMDGPU::S_MOV_B32), ConstOffsetReg)
lib/Target/ARC/ARCExpandPseudos.cpp 65 BuildMI(*SI.getParent(), SI, SI.getDebugLoc(), TII->get(AddOpc), AddrReg)
lib/Target/ARM/ARMBaseInstrInfo.cpp 2257 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
3318 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc),
5073 NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32),
5225 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg)
lib/Target/ARM/ARMISelLowering.cpp 9379 BuildMI(*MBB, MI, dl, TII->get(ARM::t2LDRpci), NewVReg1)
9385 BuildMI(*MBB, MI, dl, TII->get(ARM::t2ORRri), NewVReg2)
9391 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg3)
9409 BuildMI(*MBB, MI, dl, TII->get(ARM::tLDRpci), NewVReg1)
9414 BuildMI(*MBB, MI, dl, TII->get(ARM::tPICADD), NewVReg2)
9419 BuildMI(*MBB, MI, dl, TII->get(ARM::tMOVi8), NewVReg3)
9424 BuildMI(*MBB, MI, dl, TII->get(ARM::tORR), NewVReg4)
9430 BuildMI(*MBB, MI, dl, TII->get(ARM::tADDframe), NewVReg5)
9445 BuildMI(*MBB, MI, dl, TII->get(ARM::LDRi12), NewVReg1)
9451 BuildMI(*MBB, MI, dl, TII->get(ARM::PICADD), NewVReg2)
10303 BuildMI(*MBB, MI, DL, TII.get(ARM::t2MOVi32imm), Reg)
10318 BuildMI(*MBB, MI, DL, TII.get(ARM::t2SUBrr), ARM::SP)
lib/Target/ARM/ARMInstructionSelector.cpp 721 OffsetMIB = BuildMI(MBB, *MIB, MIB->getDebugLoc(),
726 OffsetMIB = BuildMI(MBB, *MIB, MIB->getDebugLoc(),
lib/Target/BPF/BPFMIPeephole.cpp 170 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::SUBREG_TO_REG), DstReg)
437 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::MOV_rr), DstReg)
lib/Target/BPF/BPFMISimplifyPatchable.cpp 128 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(BPF::COPY), DstReg)
lib/Target/Hexagon/HexagonInstrInfo.cpp 1032 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrrcr), CSx)
1056 BuildMI(MBB, MI, DL, get(Hexagon::A2_andir), MI.getOperand(0).getReg())
1065 BuildMI(MBB, MI, DL, get(Hexagon::V6_vcombine), DstReg)
1120 MachineInstr *MI1New = BuildMI(MBB, MI, DL, get(NewOpc),
1126 BuildMI(MBB, MI, DL, get(NewOpc), HRI.getSubReg(DstReg, Hexagon::vsub_hi))
1136 BuildMI(MBB, MI, DL, get(Hexagon::C2_orn), Reg)
1144 BuildMI(MBB, MI, DL, get(Hexagon::C2_andn), Reg)
1151 BuildMI(MBB, MI, DL, get(Hexagon::V6_veqw), MI.getOperand(0).getReg())
1158 BuildMI(MBB, MI, DL, get(Hexagon::V6_vgtw), MI.getOperand(0).getReg())
1166 BuildMI(MBB, MI, DL, get(Hexagon::V6_vsubw_dv), Vd)
1181 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1185 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_mpyi),
1208 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1213 BuildMI(MBB, MI, MI.getDebugLoc(), get(Hexagon::M2_maci),
1241 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpt), Rd)
1245 BuildMI(MBB, MI, DL, get(Hexagon::A2_tfrpf), Rd)
1351 BuildMI(MBB, MI, DL, get(Hexagon::PS_loadrdabs), Hexagon::D13)
lib/Target/Hexagon/HexagonSplitConst32AndConst64.cpp 82 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestReg)
95 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestLo)
97 BuildMI(B, MI, DL, TII->get(Hexagon::A2_tfrsi), DestHi)
lib/Target/Lanai/LanaiFrameLowering.cpp 78 BuildMI(*MBB, MI, DL, LII.get(Lanai::ADD_I_LO), Dst)
lib/Target/Lanai/LanaiInstrInfo.cpp 514 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
lib/Target/MSP430/MSP430ISelLowering.cpp 1450 BuildMI(*BB, MI, dl, TII.get(MSP430::BIC16rc), MSP430::SR)
1456 BuildMI(*BB, MI, dl, TII.get(RrcOpc), DstReg)
lib/Target/Mips/Mips16ISelLowering.cpp 767 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
785 BuildMI(*BB, MI, MI.getDebugLoc(), TII->get(Mips::MoveR3216), CC)
lib/Target/Mips/MipsSEISelLowering.cpp 3185 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3188 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3194 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
3195 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3225 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3229 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3230 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
3257 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3261 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
3291 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3295 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
3376 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3386 BuildMI(*BB, MI, DL, TII->get(ShiftOp), LaneTmp1)
3394 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
3402 BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
3409 BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
3419 BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
3423 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
3454 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3455 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3459 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3485 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3486 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3490 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
3529 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_U_H), Rs).addReg(Ws).addImm(0);
3532 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Tmp)
3583 BuildMI(*BB, MI, DL, TII->get(UsingMips32 ? Mips::LH : Mips::LH64), Rt);
3589 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Tmp).addReg(Rt, 0, Mips::sub_32);
3593 BuildMI(*BB, MI, DL, TII->get(Mips::FILL_H), Wd).addReg(Rt);
3677 BuildMI(*BB, MI, DL, TII->get(MFC1Opc), Rtemp).addReg(Fs);
3678 BuildMI(*BB, MI, DL, TII->get(FILLOpc), Wtemp).addReg(Rtemp);
3683 BuildMI(*BB, MI, DL, TII->get(Mips::MFHC1_D64), Rtemp2).addReg(Fs);
3686 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp2)
3690 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_W), Wtemp3)
3699 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_W), Wtemp2)
3705 BuildMI(*BB, MI, DL, TII->get(Mips::FEXDO_H), Wd).addReg(WPHI).addReg(WPHI);
3782 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_W), Wtemp).addReg(Ws);
3785 BuildMI(*BB, MI, DL, TII->get(Mips::FEXUPR_D), WPHI).addReg(Wtemp);
3793 BuildMI(*BB, MI, DL, TII->get(COPYOpc), Rtemp).addReg(WPHI).addImm(0);
3794 BuildMI(*BB, MI, DL, TII->get(MTC1Opc), FPRPHI).addReg(Rtemp);
3798 BuildMI(*BB, MI, DL, TII->get(Mips::COPY_S_W), Rtemp2)
3801 BuildMI(*BB, MI, DL, TII->get(Mips::MTHC1_D64), Fd)
3827 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
3828 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3831 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI.getOperand(0).getReg())
3856 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
3857 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
3860 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI.getOperand(0).getReg())
lib/Target/PowerPC/PPCFrameLowering.cpp 386 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
390 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
395 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
399 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
404 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
408 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
412 BuildMI(*MI.getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
lib/Target/PowerPC/PPCISelLowering.cpp10709 BuildMI(*thisMBB, MI, DL, TII->get(PPC::LI), restoreDstReg).addImm(1);
10789 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), FP)
10793 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), FP)
10801 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), Tmp)
10805 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), Tmp)
10813 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), SP)
10817 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), SP)
10825 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), BP)
10829 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LWZ), BP)
10838 MIB = BuildMI(*MBB, MI, DL, TII->get(PPC::LD), PPC::X2)
11443 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), MFFSReg);
11450 BuildMI(*BB, MI, dl, TII->get(PPC::FADD), Dest).addReg(Src1).addReg(Src2);
11470 BuildMI(*BB, MI, dl, TII->get(Opcode), Dest)
11473 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY),
11480 BuildMI(*BB, MI, Dl, TII->get(PPC::TCHECK), CRReg);
11481 BuildMI(*BB, MI, Dl, TII->get(TargetOpcode::COPY),
11488 BuildMI(*BB, MI, Dl, TII->get(TargetOpcode::COPY),
11496 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), OldFPSCRReg);
11523 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), DestReg)
11567 BuildMI(*BB, MI, dl, TII->get(LoadOp), DestReg)
11577 BuildMI(*BB, MI, dl, TII->get(PPC::MFFS), OldFPSCRReg);
11599 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::IMPLICIT_DEF), ImDefReg);
11600 BuildMI(*BB, MI, dl, TII->get(PPC::INSERT_SUBREG), ExtSrcReg)
11606 BuildMI(*BB, MI, dl, TII->get(PPC::RLDIMI), NewFPSCRTmpReg)
lib/Target/PowerPC/PPCInstrInfo.cpp 2222 BuildMI(MBB, MI, DL, get(PPC::CMPD), PPC::CR7).addReg(Val).addReg(Val);
lib/Target/PowerPC/PPCVSXCopy.cpp 106 BuildMI(MBB, MI, MI.getDebugLoc(),
128 BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(TargetOpcode::COPY),
lib/Target/RISCV/RISCVISelLowering.cpp 1170 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg)
1174 BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg)
lib/Target/SystemZ/SystemZISelLowering.cpp 6512 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LA), Reg)
7178 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Tmp1);
7179 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Tmp2)
7181 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
7204 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
7209 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
7211 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
7215 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
7352 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LAY), Reg)
7361 BuildMI(*MBB, MI, MI.getDebugLoc(), TII->get(SystemZ::LAY), Reg)
7525 BuildMI(*MBB, MI, DL, TII->get(Opcode), DstReg)
lib/Target/WebAssembly/WebAssemblyPeephole.cpp 121 BuildMI(MBB, MI, MI.getDebugLoc(), TII.get(CopyLocalOpc), NewReg)
lib/Target/WebAssembly/WebAssemblyRegisterInfo.cpp 121 BuildMI(MBB, *II, II->getDebugLoc(), TII->get(WebAssembly::CONST_I32),
125 BuildMI(MBB, *II, II->getDebugLoc(), TII->get(WebAssembly::ADD_I32),
lib/Target/X86/X86FixupLEAs.cpp 649 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
668 NewMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
lib/Target/X86/X86ISelLowering.cpp30246 BuildMI(*BB, MI, DL, TII->get(X86::MOV64rm), X86::RDI)
30258 BuildMI(*BB, MI, DL, TII->get(X86::MOV32rm), X86::EAX)
30270 BuildMI(*BB, MI, DL, TII->get(X86::MOV32rm), X86::EAX)
30401 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY), AvailableReg)
30447 BuildMI(*MBB, MI, DL, TII->get(RdsspOpc), SSPCopyReg).addReg(ZReg);
30543 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA64r), LabelReg)
30551 MIB = BuildMI(*thisMBB, MI, DL, TII->get(X86::LEA32r), LabelReg)
30840 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrLoadOpc), FP);
30852 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrLoadOpc), Tmp);
30866 MIB = BuildMI(*thisMBB, MI, DL, TII->get(PtrLoadOpc), SP);
30910 BuildMI(*MBB, MI, DL, TII->get(X86::LEA64r), VR)
30917 BuildMI(*MBB, MI, DL, TII->get(X86::LEA32r), VR)
31229 BuildMI(*BB, MI, DL, TII->get(Pop), MI.getOperand(0).getReg());
31265 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOVZX32rm16), OldCW),
31270 BuildMI(*BB, MI, DL, TII->get(X86::OR32ri), NewCW)
31276 BuildMI(*BB, MI, DL, TII->get(TargetOpcode::COPY), NewCW16)
31399 BuildMI(*BB, *MBBI, DL, TII->get(X86::LEA32r), computedAddrVReg), AM);
lib/Target/X86/X86InstrInfo.cpp 4578 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
4586 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
4595 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), XReg)
4601 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::XOR32rr), Reg)
7907 BuildMI(*I.getParent(), I, I.getDebugLoc(),
lib/Target/X86/X86InstructionSelector.cpp 863 BuildMI(*I.getParent(), I, I.getDebugLoc(),
871 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(AndOpc), DstReg)
977 MachineInstr &SetInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1039 MachineInstr &Set1 = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1041 MachineInstr &Set2 = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1043 MachineInstr &Set3 = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1071 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SETCCr), ResultReg).addImm(CC);
1105 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), X86::EFLAGS)
1122 *BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Opcode), DstReg)
1126 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), CarryOutReg)
1226 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::COPY), DstReg)
1340 *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1379 MachineInstr &InsertInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1391 MachineInstr &CopyInst = *BuildMI(*I.getParent(), I, I.getDebugLoc(),
1453 BuildMI(*I.getParent(), I, DbgLoc, TII.get(X86::MOV64ri), AddrReg)
1461 addDirectMem(BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg),
1479 BuildMI(*I.getParent(), I, DbgLoc, TII.get(Opc), DstReg), CPI, PICBase,
1643 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(OpEntry.OpCopy),
1653 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::MOV32r0),
1660 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy),
1664 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy),
1668 BuildMI(*I.getParent(), I, I.getDebugLoc(),
1692 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(Copy), SourceSuperReg)
1696 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(X86::SHR16ri),
1709 BuildMI(*I.getParent(), I, I.getDebugLoc(), TII.get(TargetOpcode::COPY),