|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/X86/X86GenFastISel.inc 6952 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::AL).addReg(Op0);
7435 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
7537 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
7699 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
8025 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
8041 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY), X86::CL).addReg(Op1);
include/llvm/CodeGen/MachineInstrBuilder.h 365 return BuildMI(BB, MachineBasicBlock::iterator(I), DL, MCID, DestReg);
425 return BuildMI(*BB, BB->end(), DL, MCID, DestReg);
include/llvm/CodeGen/TargetInstrInfo.h 1706 return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
1718 return BuildMI(MBB, InsPt, DL, get(TargetOpcode::COPY), Dst)
lib/CodeGen/BranchFolding.cpp 442 BuildMI(OldMBB, OldInst, DL, TII->get(TargetOpcode::IMPLICIT_DEF), Reg);
941 BuildMI(*Pred, InsertBefore, DL, TII->get(TargetOpcode::IMPLICIT_DEF),
lib/CodeGen/GlobalISel/Utils.cpp 57 BuildMI(MBB, InsertIt, InsertPt.getDebugLoc(),
62 BuildMI(MBB, std::next(InsertIt), InsertPt.getDebugLoc(),
lib/CodeGen/MachineBasicBlock.cpp 517 BuildMI(*this, I, DebugLoc(), TII.get(TargetOpcode::COPY), VirtReg)
lib/CodeGen/MachinePipeliner.cpp 368 auto Copy = BuildMI(PredB, At, DL, TII->get(TargetOpcode::COPY), NewReg)
lib/CodeGen/MachineRegisterInfo.cpp 486 BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
lib/CodeGen/MachineSSAUpdater.cpp 122 return BuildMI(*BB, I, DebugLoc(), TII->get(Opcode), NewVR);
lib/CodeGen/ModuloSchedule.cpp 551 BuildMI(*NewBB, NewBB->getFirstNonPHI(), DebugLoc(),
667 BuildMI(*NewBB, NewBB->getFirstNonPHI(), DebugLoc(),
1486 BuildMI(*BB, BB->getFirstNonPHI(), DebugLoc(), TII->get(TargetOpcode::PHI), R)
1506 BuildMI(*InsertBB, InsertBB->getFirstTerminator(), DebugLoc(),
lib/CodeGen/PHIElimination.cpp 267 PHICopy = BuildMI(MBB, AfterPHIsIt, MPhi->getDebugLoc(),
405 NewSrcInstr = BuildMI(opBlock, InsertPos, MPhi->getDebugLoc(),
lib/CodeGen/PrologEpilogInserter.cpp 547 BuildMI(SaveBlock, I, DebugLoc(),
575 BuildMI(RestoreBlock, I, DebugLoc(), TII.get(TargetOpcode::COPY), Reg)
lib/CodeGen/RegisterCoalescer.cpp 1123 MachineInstr *NewCopyMI = BuildMI(*CopyLeftBB, InsPos, CopyMI.getDebugLoc(),
lib/CodeGen/RenameIndependentSubregs.cpp 332 MachineInstrBuilder ImpDef = BuildMI(*PredMBB, InsertPos,
lib/CodeGen/SelectionDAG/FastISel.cpp 446 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1555 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2029 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2042 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg);
2055 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2060 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2078 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2085 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2104 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2113 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2128 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2135 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2151 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2160 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2174 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2179 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2196 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2205 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2217 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
2221 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2234 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
lib/CodeGen/SelectionDAG/InstrEmitter.cpp 177 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
276 BuildMI(*MBB, InsertPos, Op.getDebugLoc(),
323 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
390 BuildMI(*MBB, InsertPos, Op.getNode()->getDebugLoc(),
468 BuildMI(*MBB, InsertPos, DL, TII->get(TargetOpcode::COPY), NewReg)
524 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
541 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
617 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
1000 BuildMI(*MBB, InsertPos, Node->getDebugLoc(),
1013 BuildMI(*MBB, InsertPos, Node->getDebugLoc(), TII->get(TargetOpcode::COPY),
lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp 806 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), Reg)
815 BuildMI(*BB, InsertPos, DebugLoc(), TII->get(TargetOpcode::COPY), VRBase)
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 1246 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(),
lib/CodeGen/SplitKit.cpp 545 BuildMI(MBB, InsertBefore, DebugLoc(), Desc, ToReg).addReg(FromReg);
lib/CodeGen/SwiftErrorValueTracking.cpp 136 BuildMI(*MBB, MBB->getFirstNonPHI(), DbgLoc,
232 BuildMI(*MBB, MBB->getFirstNonPHI(), DLoc, TII->get(TargetOpcode::COPY),
245 BuildMI(*MBB, MBB->getFirstNonPHI(), DLoc,
lib/CodeGen/TailDuplicator.cpp 984 auto C = BuildMI(*MBB, Loc, DebugLoc(), CopyD, CI.first)
lib/CodeGen/UnreachableBlockElim.cpp 195 BuildMI(*BB, BB->getFirstNonPHI(), phi->getDebugLoc(),
lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp 466 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opcode),
484 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
501 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg);
553 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::ADRP), DstReg)
567 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MOVKXi), DstReg)
607 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(AArch64::MRS), DstReg)
lib/Target/AArch64/AArch64FalkorHWPFFix.cpp 784 BuildMI(*MBB, std::next(MachineBasicBlock::iterator(MI)), DL,
lib/Target/AArch64/AArch64FastISel.cpp 369 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
392 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
424 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc1), TmpReg)
428 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
443 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
448 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
475 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
487 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(LdrOpc),
507 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
512 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
1057 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADDXri),
1346 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1390 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1433 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1478 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
1897 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1912 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2583 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2623 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2628 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2642 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::CSINCWr),
2813 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
2849 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTDSr),
2865 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::FCVTSDr),
2899 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
3054 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3115 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3179 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3283 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(AArch64::ADRP),
3288 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3481 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3506 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3640 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
3814 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3926 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3997 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4021 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4127 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4174 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4234 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4295 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4355 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4404 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4463 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4560 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
4604 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
lib/Target/AArch64/AArch64FrameLowering.cpp 991 BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::COPY), AArch64::FP)
1030 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVZXi), AArch64::X15)
1037 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVKXi), AArch64::X15)
1046 BuildMI(MBB, MBBI, DL, TII->get(AArch64::MOVi64imm), AArch64::X15)
1096 BuildMI(MBB, MBBI, DL, TII->get(AArch64::SUBXrx64), AArch64::SP)
1149 BuildMI(MBB, MBBI, DL, TII->get(AArch64::ANDXri), AArch64::SP)
2378 BuildMI(MBB, MBBI, DL, TII.get(AArch64::MOVi64imm), DstReg).addImm(-2);
lib/Target/AArch64/AArch64ISelLowering.cpp 1371 BuildMI(*EndBB, EndBB->begin(), DL, TII->get(AArch64::PHI), DestReg)
12404 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
12409 BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
lib/Target/AArch64/AArch64InstrInfo.cpp 580 BuildMI(MBB, I, DL, get(AArch64::SUBSXri), AArch64::XZR)
586 BuildMI(MBB, I, DL, get(AArch64::SUBSWri), AArch64::WZR)
609 BuildMI(MBB, I, DL, get(AArch64::ANDSWri), AArch64::WZR)
614 BuildMI(MBB, I, DL, get(AArch64::ANDSXri), AArch64::XZR)
668 BuildMI(MBB, I, DL, get(Opc), DstReg)
2482 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestRegX)
2488 BuildMI(MBB, I, DL, get(AArch64::ADDWri), DestReg)
2494 BuildMI(MBB, I, DL, get(AArch64::MOVZWi), DestReg)
2508 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestRegX)
2514 BuildMI(MBB, I, DL, get(AArch64::ORRWrr), DestReg)
2526 BuildMI(MBB, I, DL, get(AArch64::ORR_PPzPP), DestReg)
2537 BuildMI(MBB, I, DL, get(AArch64::ORR_ZZZ), DestReg)
2547 BuildMI(MBB, I, DL, get(AArch64::ADDXri), DestReg)
2552 BuildMI(MBB, I, DL, get(AArch64::MOVZXi), DestReg)
2557 BuildMI(MBB, I, DL, get(AArch64::ORRXrr), DestReg)
2641 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
2666 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
2670 BuildMI(MBB, I, DL, get(AArch64::FMOVDr), DestReg)
2683 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
2687 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
2700 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
2708 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
2721 BuildMI(MBB, I, DL, get(AArch64::ORRv16i8), DestReg)
2729 BuildMI(MBB, I, DL, get(AArch64::FMOVSr), DestReg)
2738 BuildMI(MBB, I, DL, get(AArch64::FMOVXDr), DestReg)
2744 BuildMI(MBB, I, DL, get(AArch64::FMOVDXr), DestReg)
2751 BuildMI(MBB, I, DL, get(AArch64::FMOVWSr), DestReg)
2757 BuildMI(MBB, I, DL, get(AArch64::FMOVSWr), DestReg)
2773 BuildMI(MBB, I, DL, get(AArch64::MRS), DestReg)
3096 auto MBI = BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp 916 BuildMI(*MBB, InsertionPoint, DL, TII->get(TargetOpcode::KILL), DstRegW)
922 BuildMI(*MBB, InsertionPoint, DL, TII->get(AArch64::SBFMXri), DstRegX)
978 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
1018 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
1026 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
lib/Target/AArch64/AArch64RegisterInfo.cpp 421 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp 782 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
844 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
849 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
875 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32),
942 BuildMI(MBB, MBB.end(), DL, TII->get(MovTermOpc), SaveExecReg)
lib/Target/AMDGPU/R600ISelLowering.cpp 400 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::PRED_X),
414 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(R600::PRED_X),
lib/Target/AMDGPU/R600InstrInfo.cpp 1243 MachineInstrBuilder MIB = BuildMI(MBB, I, MBB.findDebugLoc(I), get(Opcode),
lib/Target/AMDGPU/R600OptimizeVectorRegisters.cpp 215 MachineInstr *Tmp = BuildMI(MBB, Pos, DL, TII->get(R600::INSERT_SUBREG),
231 BuildMI(MBB, Pos, DL, TII->get(R600::COPY), Reg).addReg(SrcVec);
lib/Target/AMDGPU/SIAddIMGInit.cpp 158 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewDst)
lib/Target/AMDGPU/SIFrameLowering.cpp 123 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg)
153 BuildMI(MBB, I, DebugLoc(),
170 BuildMI(MBB, I, DebugLoc(), TII->get(AMDGPU::V_MOV_B32_e32), OffsetReg)
173 BuildMI(MBB, I, DebugLoc(),
224 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo)
227 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), FlatScrInitHi)
241 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), AMDGPU::FLAT_SCR_LO)
244 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), AMDGPU::FLAT_SCR_HI)
254 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), AMDGPU::FLAT_SCR_LO)
259 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo)
264 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_LSHR_B32), AMDGPU::FLAT_SCR_HI)
489 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)
501 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchWaveOffsetReg)
506 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)
522 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), SPReg)
525 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), SPReg)
553 BuildMI(MBB, I, DL, SMovB32, RsrcHi)
558 BuildMI(MBB, I, DL, GetPC64, Rsrc01);
575 BuildMI(MBB, I, DL, SMovB32, RsrcLo)
594 BuildMI(MBB, I, DL, LoadDwordX4, ScratchRsrcReg)
620 BuildMI(MBB, I, DL, Mov64, Rsrc01)
635 BuildMI(MBB, I, DL, LoadDwordX2, Rsrc01)
650 BuildMI(MBB, I, DL, SMovB32, Rsrc0)
654 BuildMI(MBB, I, DL, SMovB32, Rsrc1)
660 BuildMI(MBB, I, DL, SMovB32, Rsrc2)
664 BuildMI(MBB, I, DL, SMovB32, Rsrc3)
712 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FuncInfo->SGPRForFPSaveRestoreCopy)
737 BuildMI(MBB, MBBI, DL, TII->get(OrSaveExec),
752 BuildMI(MBB, MBBI, DL, TII->get(ExecMov), Exec)
768 BuildMI(MBB, MBBI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_WRITELANE_B32),
793 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_U32), ScratchSPReg)
797 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_AND_B32), FramePtrReg)
807 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FramePtrReg)
813 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_ADD_U32), StackPtrReg)
848 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::S_SUB_U32), StackPtrReg)
855 BuildMI(MBB, MBBI, DL, TII->get(AMDGPU::COPY), FuncInfo->getFrameOffsetReg())
869 BuildMI(MBB, MBBI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
897 BuildMI(MBB, MBBI, DL, TII->get(OrSaveExec), ScratchExecCopy)
910 BuildMI(MBB, MBBI, DL, TII->get(ExecMov), Exec)
1121 BuildMI(MBB, I, DL, TII->get(Op), SPReg)
lib/Target/AMDGPU/SIISelLowering.cpp 2006 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
2011 BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
3146 BuildMI(*LoopBB, I, DL, TII->get(AMDGPU::S_GETREG_B32), Reg)
3189 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg)
3195 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiExec)
3202 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), CurrentIdxReg)
3206 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg)
3211 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_AND_SAVEEXEC_B32
3224 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), IdxReg)
3238 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3241 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3250 BuildMI(LoopBB, I, DL, TII->get(ST.isWave32() ? AMDGPU::S_XOR_B32_term
3292 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), TmpExec);
3295 BuildMI(MBB, I, DL, TII->get(MovExecOpc), SaveExec)
3309 BuildMI(*RemainderBB, First, DL, TII->get(MovExecOpc), Exec)
3362 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), Tmp)
3377 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
3380 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
3417 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
3423 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3439 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg);
3446 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
3452 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
3510 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dst)
10715 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), AMDGPU::VCC_HI);
lib/Target/AMDGPU/SIInstrInfo.cpp 520 BuildMI(MBB, MI, DL, TII->get(AMDGPU::SI_ILLEGAL_COPY), DestReg)
536 BuildMI(MBB, MI, DL, get(Opc), DestReg)
544 BuildMI(MBB, MI, DL, get(AMDGPU::S_CSELECT_B32), DestReg)
552 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), AMDGPU::VCC_LO)
570 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
578 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), AMDGPU::VCC)
596 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
639 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg)
671 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg)
676 BuildMI(MBB, MI, DL, get(AMDGPU::V_ACCVGPR_WRITE_B32), DestReg)
720 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
761 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg)
769 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg)
775 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B32_e32), DestReg)
780 BuildMI(MBB, MI, DL, get(AMDGPU::V_MOV_B64_PSEUDO), DestReg)
801 MachineInstrBuilder Builder = BuildMI(MBB, MI, DL,
828 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
830 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
841 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
845 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
855 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
859 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
871 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
873 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
885 BuildMI(MBB, I, DL, get(AMDGPU::COPY), SReg)
887 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
898 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
901 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
905 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
916 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_OR_SAVEEXEC_B32
919 BuildMI(MBB, I, DL, get(ST.isWave32() ? AMDGPU::S_CSELECT_B32
923 BuildMI(MBB, I, DL, get(AMDGPU::V_CNDMASK_B32_e64), DstReg)
946 BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_EQ_I32_e64), Reg)
959 BuildMI(*MBB, I, DL, get(AMDGPU::V_CMP_NE_I32_e64), Reg)
1204 BuildMI(MBB, MI, DL, OpDesc, DestReg)
1214 auto MIB = BuildMI(MBB, MI, DL, get(Opcode), DestReg);
1268 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp0)
1271 BuildMI(Entry, Insert, DL, get(AMDGPU::S_LOAD_DWORD_IMM), STmp1)
1276 BuildMI(Entry, Insert, DL, get(AMDGPU::S_MUL_I32), STmp1)
1280 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MUL_U32_U24_e32), TIDReg)
1284 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MAD_U32_U24), TIDReg)
1295 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_LO_U32_B32_e64),
1300 BuildMI(Entry, Insert, DL, get(AMDGPU::V_MBCNT_HI_U32_B32_e64),
1306 BuildMI(Entry, Insert, DL, get(AMDGPU::V_LSHLREV_B32_e32),
1788 MachineInstr *GetPC = BuildMI(MBB, I, DL, get(AMDGPU::S_GETPC_B64), PCReg);
2177 BuildMI(MBB, I, DL, get(SelOp), DstReg)
2187 BuildMI(MBB, I, DL, get(AMDGPU::S_CSELECT_B64), DstReg)
2228 MachineInstrBuilder MIB = BuildMI(
2241 BuildMI(MBB, I, DL, get(SelOp), DstElt)
3848 BuildMI(*MI.getParent(), I, DL, get(Opcode), Reg).add(MO);
3864 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
3875 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), NewSuperReg)
3878 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg)
4290 BuildMI(InsertMBB, I, DL, get(AMDGPU::COPY), DstReg).add(Op);
4350 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub0)
4352 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub1)
4354 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub2)
4356 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), SRsrcSub3)
4359 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), SRsrc)
4374 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg0)
4377 BuildMI(LoopBB, I, DL, TII.get(AMDGPU::V_CMP_EQ_U64_e64), CondReg1)
4380 BuildMI(LoopBB, I, DL, TII.get(AndOpc), AndCond)
4387 BuildMI(LoopBB, I, DL, TII.get(SaveExecOpc), SaveExec)
4394 BuildMI(LoopBB, I, DL, TII.get(XorTermOpc), Exec)
4418 BuildMI(MBB, I, DL, TII.get(MovExecOpc), SaveExec).addReg(Exec);
4467 BuildMI(*RemainderBB, First, DL, TII.get(MovExecOpc), Exec).addReg(SaveExec);
5151 BuildMI(MBB, MII, DL, get(SubOp), TmpReg)
5155 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg)
5179 BuildMI(MBB, MII, DL, get(AMDGPU::V_XNOR_B32_e64), NewDest)
5202 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src0);
5203 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
5207 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Temp).add(Src1);
5208 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), NewDest)
5212 Xor = BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B32), Temp)
5216 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest).addReg(Temp);
5243 MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), Interm)
5247 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), NewDest)
5272 MachineInstr &Not = *BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B32), Interm)
5275 MachineInstr &Op = *BuildMI(MBB, MII, DL, get(Opcode), NewDest)
5313 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0).add(SrcReg0Sub0);
5319 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1).add(SrcReg0Sub1);
5322 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
5380 BuildMI(MBB, MII, DL, get(LoOpc), DestSub0)
5388 BuildMI(MBB, MII, DL, get(HiOpc), DestSub1)
5395 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
5451 MachineInstr &LoHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub0)
5456 MachineInstr &HiHalf = *BuildMI(MBB, MII, DL, InstDesc, DestSub1)
5461 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), FullDestReg)
5504 BuildMI(MBB, MII, DL, get(AMDGPU::S_NOT_B64), Interm)
5509 MachineInstr &Xor = *BuildMI(MBB, MII, DL, get(AMDGPU::S_XOR_B64), NewDest)
5544 BuildMI(MBB, MII, DL, InstDesc, MidReg).add(SrcRegSub0).addImm(0);
5546 BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg);
5578 BuildMI(MBB, MII, DL, get(AMDGPU::V_BFE_I32), MidRegLo)
5583 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e32), MidRegHi)
5587 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
5602 BuildMI(MBB, MII, DL, get(AMDGPU::V_ASHRREV_I32_e64), TmpReg)
5606 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg)
6194 return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_U32_e64), DestReg);
6200 return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_I32_e64), DestReg)
6210 return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_U32_e32), DestReg);
6217 return BuildMI(MBB, I, DL, get(AMDGPU::V_ADD_I32_e64), DestReg)
6532 return BuildMI(MBB, Cur, DL, get(TargetOpcode::COPY), Dst).addReg(Src);
6549 return BuildMI(MBB, InsPt, InsPt->getDebugLoc(),
lib/Target/AMDGPU/SILoadStoreOptimizer.cpp 912 BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg)
926 BuildMI(*MBB, CI.Paired, DL, Read2Desc, DestReg)
1005 BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::S_MOV_B32), ImmReg)
1050 auto MIB = BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode), DestReg);
1111 BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode), DestReg)
1154 auto MIB = BuildMI(*MBB, CI.Paired, DL, TII->get(Opcode), DestReg);
1313 BuildMI(*MBB, CI.Paired, DL, TII->get(AMDGPU::REG_SEQUENCE), SrcReg)
1397 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADD_I32_e64), DestSub0)
1406 BuildMI(*MBB, MBBI, DL, TII->get(AMDGPU::V_ADDC_U32_e64), DestSub1)
1417 BuildMI(*MBB, MBBI, DL, TII->get(TargetOpcode::REG_SEQUENCE), FullDestReg)
lib/Target/AMDGPU/SILowerControlFlow.cpp 219 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), CopyReg)
226 BuildMI(MBB, I, DL, TII->get(AndOpc), Tmp)
235 BuildMI(MBB, I, DL, TII->get(XorOpc), SaveExecReg)
244 BuildMI(MBB, I, DL, TII->get(MovTermOpc), Exec)
295 BuildMI(MBB, Start, DL, TII->get(AMDGPU::COPY), CopyReg)
303 BuildMI(MBB, Start, DL, TII->get(OrSaveExecOpc), SaveReg)
312 BuildMI(MBB, ElsePt, DL, TII->get(AndOpc), DstReg)
321 BuildMI(MBB, ElsePt, DL, TII->get(XorTermrOpc), Exec)
426 MachineInstr *NewMI = BuildMI(MBB, InsPt, DL, TII->get(OrOpc), Exec)
lib/Target/AMDGPU/SILowerI1Copies.cpp 439 BuildMI(MBB, MBB.getFirstTerminator(), {}, TII->get(AMDGPU::IMPLICIT_DEF),
824 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(CurReg);
826 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg).addReg(ExecReg);
828 BuildMI(MBB, I, DL, TII->get(XorOp), DstReg)
842 BuildMI(MBB, I, DL, TII->get(AndN2Op), PrevMaskedReg)
853 BuildMI(MBB, I, DL, TII->get(AndOp), CurMaskedReg)
860 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)
863 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), DstReg)
866 BuildMI(MBB, I, DL, TII->get(OrN2Op), DstReg)
870 BuildMI(MBB, I, DL, TII->get(OrOp), DstReg)
lib/Target/AMDGPU/SIRegisterInfo.cpp 356 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_MOV_B32_e32), BaseReg)
366 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
368 BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::V_MOV_B32_e32), FIReg)
568 return BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(Opc), Dst)
679 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), SOffset)
705 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ACCVGPR_READ_B32), TmpReg)
728 MIB = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_ACCVGPR_WRITE_B32),
739 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), ScratchOffsetReg)
804 BuildMI(*MBB, MI, DL,
824 = BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR)
854 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), AMDGPU::M0)
903 BuildMI(*MBB, MI, DL, TII->getMCOpcodeFromPseudo(AMDGPU::V_READLANE_B32),
927 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::SI_SPILL_V32_RESTORE), TmpVGPR)
935 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), SubReg)
944 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), AMDGPU::M0)
1110 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), DiffReg)
1117 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_LSHRREV_B32_e64), ResultReg)
1164 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHR_B32), ScaledReg)
1167 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), ScaledReg)
1170 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), ResultReg)
1175 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_SUB_U32), ScaledReg)
1178 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_LSHL_B32), ScaledReg)
1187 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), FrameReg)
1230 BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpReg)
lib/Target/AMDGPU/SIWholeQuadMode.cpp 562 BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), SaveReg)
565 BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), AMDGPU::SCC)
632 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ?
638 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ?
655 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), Exec)
658 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ?
673 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::ENTER_WWM), SaveOrig)
684 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::EXIT_WWM),
904 MachineInstr *MI = BuildMI(Entry, EntryMI, DebugLoc(),
914 BuildMI(Entry, EntryMI, DebugLoc(), TII->get(ST->isWave32() ?
lib/Target/ARC/ARCFrameLowering.cpp 72 BuildMI(MBB, MBBI, dl, TII.get(AdjOp), StackPtr)
143 BuildMI(MBB, MBBI, dl, TII->get(Opc), ARC::SP)
187 BuildMI(MBB, MBBI, dl,
258 BuildMI(MBB, MBBI, DebugLoc(), TII->get(Opc), ARC::SP)
288 BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(Opc), ARC::SP)
303 BuildMI(MBB, MBBI, MBB.findDebugLoc(MBBI), TII->get(Opc), ARC::SP)
464 BuildMI(MBB, MBBI, dl, TII->get(Opc), Reg)
lib/Target/ARC/ARCInstrInfo.cpp 289 BuildMI(MBB, I, dl, get(ARC::MOV_rr), DestReg)
363 return BuildMI(MBB, MI, dl, get(ARC::MOV_rs12), Reg)
lib/Target/ARC/ARCRegisterInfo.cpp 50 BuildMI(MBB, II, dl, TII.get(ARC::LD_rlimm), Reg)
93 BuildMI(MBB, II, dl, TII.get(MI.getOpcode()), Reg)
lib/Target/ARM/A15SDOptimizer.cpp 423 BuildMI(MBB, InsertBefore, DL,
438 BuildMI(MBB,
452 BuildMI(MBB,
470 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::VEXTd32), Out)
482 BuildMI(MBB,
498 BuildMI(MBB,
lib/Target/ARM/ARMBaseInstrInfo.cpp 777 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
838 BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
861 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
931 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_P0), DestReg)
937 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_P0), DestReg)
943 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMSR_FPSCR_NZCVQC), DestReg)
949 BuildMI(MBB, I, I->getDebugLoc(), get(ARM::VMRS_FPSCR_NZCVQC), DestReg)
976 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
1285 BuildMI(MBB, I, DL, get(ARM::VLDRH), DestReg)
1295 BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1301 BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1307 BuildMI(MBB, I, DL, get(ARM::VLDR_P0_off), DestReg)
1317 BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1350 BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1356 BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1363 auto MIB = BuildMI(MBB, I, DL, get(ARM::MVE_VLDRWU32), DestReg);
1375 BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1398 BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1710 BuildMI(MBB, I, Orig.getDebugLoc(), get(Opcode), DestReg)
2365 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
2388 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
4780 BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4784 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4794 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
lib/Target/ARM/ARMBaseRegisterInfo.cpp 648 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
lib/Target/ARM/ARMExpandPseudoInsts.cpp 846 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
878 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
955 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), DesiredReg)
1219 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
1232 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1244 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1257 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
1273 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1285 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1299 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1322 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1369 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
1384 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1397 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1420 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1453 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg)
1505 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
1543 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1548 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
1576 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
lib/Target/ARM/ARMFastISel.cpp 311 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
316 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
337 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
344 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
363 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
370 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
384 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II,
389 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
402 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
412 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
438 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
458 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
476 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
492 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
519 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
525 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
569 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
594 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
602 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
612 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
626 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
631 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
679 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
853 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1003 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1011 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1067 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1115 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1491 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc), DestReg)
1511 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1530 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1576 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1603 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1672 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1680 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovCCOpc),
1782 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1829 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1993 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2007 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2056 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2077 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2162 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2511 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2721 MachineInstrBuilder MIB = BuildMI(
2802 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2970 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), TempReg)
2982 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2991 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3064 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
lib/Target/ARM/ARMFrameLowering.cpp 303 BuildMI(MBB, MBBI, DL, TII.get(ARM::BFC), Reg)
308 BuildMI(MBB, MBBI, DL, TII.get(ARM::BICri), Reg)
318 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
323 BuildMI(MBB, MBBI, DL, TII.get(ARM::MOVsi), Reg)
333 BuildMI(MBB, MBBI, DL, TII.get(ARM::t2BFC), Reg)
522 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), ARM::R4)
527 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R4)
544 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ARM::R12)
556 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), ARM::SP)
733 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
738 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
753 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), RegInfo->getBaseRegister())
758 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), RegInfo->getBaseRegister())
835 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
842 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), ARM::SP)
847 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
1024 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
1031 BuildMI(MBB, MI, DL, TII.get(StrOpc), ARM::SP)
1120 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
1138 BuildMI(MBB, MI, DL, TII.get(LdrOpc), Regs[0])
1209 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1228 MachineInstrBuilder MIB = BuildMI(MBB, MI, DL, TII.get(Opc), ARM::SP)
1244 BuildMI(MBB, MI, DL, TII.get(ARM::VST1d64Qwb_fixed), ARM::R4)
1362 BuildMI(MBB, MI, DL, TII.get(Opc), ARM::R4)
1375 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Qwb_fixed), NextReg)
1393 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1d64Q), NextReg)
1406 BuildMI(MBB, MI, DL, TII.get(ARM::VLD1q64), SupReg)
1416 BuildMI(MBB, MI, DL, TII.get(ARM::VLDRD), NextReg)
lib/Target/ARM/ARMISelLowering.cpp 9933 BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
9940 BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
9944 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut)
9950 BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
9956 BuildMI(*BB, Pos, dl, TII->get(LdOpc), Data)
9974 BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
9986 BuildMI(*BB, Pos, dl, TII->get(ARM::tADDi8), AddrOut)
9992 BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
9998 BuildMI(*BB, Pos, dl, TII->get(StOpc), AddrOut)
10186 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), varPhi)
10206 BuildMI(*BB, BB->end(), dl, TII->get(ARM::tSUBi8), varLoop)
10213 BuildMI(*BB, BB->end(), dl,
10530 BuildMI(*BB, BB->begin(), dl, TII->get(ARM::PHI), MI.getOperand(0).getReg())
10657 BuildMI(*RSBBB, RSBBB->begin(), dl,
10666 BuildMI(*SinkBB, SinkBB->begin(), dl,
17125 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
17130 BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
lib/Target/ARM/ARMInstrInfo.cpp 123 MIB = BuildMI(MBB, MI, DL, get(ARM::MOV_ga_pcrel_ldr), Reg)
131 BuildMI(MBB, MI, DL, get(ARM::LDRi12), Reg)
lib/Target/ARM/ARMLoadStoreOptimizer.cpp 550 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base)
571 BuildMI(MBB, MBBI, DL, TII->get(ARM::tSUBi8), Base)
736 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVSr), NewBase)
739 BuildMI(MBB, InsertBefore, DL, TII->get(ARM::tMOVr), NewBase)
749 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
754 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
760 BuildMI(MBB, InsertBefore, DL, TII->get(BaseOpc), NewBase)
1452 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1458 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1468 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), MI->getOperand(0).getReg())
1483 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
1492 BuildMI(MBB, MBBI, DL, TII->get(NewOpc), Base)
lib/Target/ARM/Thumb1FrameLowering.cpp 84 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), ScratchReg)
90 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDhirr), ARM::SP)
302 BuildMI(MBB, MBBI, dl, TII.get(ARM::tADDrSPi), FramePtr)
412 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::R4)
416 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSRri), ARM::R4)
422 BuildMI(MBB, MBBI, dl, TII.get(ARM::tLSLri), ARM::R4)
428 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
440 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), BasePtr)
519 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
523 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), ARM::SP)
lib/Target/ARM/Thumb1InstrInfo.cpp 51 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
61 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg)
125 BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg)
lib/Target/ARM/Thumb2InstrInfo.cpp 129 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg)
191 BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg)
238 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
255 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg)
261 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVTi16), DestReg)
270 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2SUBrr), DestReg)
282 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2ADDrr), DestReg)
298 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVr), DestReg)
312 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
353 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
lib/Target/ARM/ThumbRegisterInfo.cpp 149 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)
154 BuildMI(MBB, MBBI, dl, TII.get(ARM::tMOVi8), LdReg)
158 BuildMI(MBB, MBBI, dl, TII.get(ARM::tRSB), LdReg)
163 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi32imm), LdReg)
172 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg);
312 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(CopyOpc), DestReg);
329 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(ExtraOpc), DestReg);
lib/Target/AVR/AVRExpandPseudoInsts.cpp 68 return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(Opcode), DstReg);
lib/Target/AVR/AVRFrameLowering.cpp 84 BuildMI(MBB, MBBI, DL, TII.get(AVR::INRdA), AVR::R0)
114 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPREAD), AVR::R29R28)
131 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
139 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
170 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPRd), AVR::R0);
174 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPWRd), AVR::R1R0);
178 BuildMI(MBB, MBBI, DL, TII.get(AVR::POPWRd), AVR::R29R28);
208 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opcode), AVR::R29R28)
215 BuildMI(MBB, MBBI, DL, TII.get(AVR::SPWRITE), AVR::SP)
295 BuildMI(MBB, MI, DL, TII.get(AVR::POPRd), Reg);
401 BuildMI(MBB, MI, DL, TII.get(AVR::SPREAD), AVR::R31R30).addReg(AVR::SP);
403 MachineInstr *New = BuildMI(MBB, MI, DL, TII.get(addOpcode), AVR::R31R30)
408 BuildMI(MBB, MI, DL, TII.get(AVR::SPWRITE), AVR::SP)
518 BuildMI(EntryMBB, MBBI, DL, TII.get(AVR::COPY), SPCopy).addReg(AVR::SP);
526 BuildMI(MBB, MBBI, DL, TII.get(AVR::COPY), AVR::SP)
lib/Target/AVR/AVRISelLowering.cpp 1559 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(AVR::PHI), DstReg)
1590 BuildMI(*BB, I, MI.getDebugLoc(), TII.get(AVR::EORRdRr), AVR::R1)
1673 BuildMI(*trueMBB, trueMBB->begin(), dl, TII.get(AVR::PHI), MI.getOperand(0).getReg())
lib/Target/AVR/AVRInstrInfo.cpp 52 BuildMI(MBB, MI, DL, get(AVR::MOVWRdRr), DestReg)
61 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestLo)
63 BuildMI(MBB, MI, DL, get(AVR::MOVRdRr), DestHi)
77 BuildMI(MBB, MI, DL, get(Opc), DestReg)
188 BuildMI(MBB, MI, DL, get(Opcode), DestReg)
lib/Target/AVR/AVRRegisterInfo.cpp 196 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(Opcode), DstReg)
222 BuildMI(MBB, II, dl, TII.get(AVR::INRdA), AVR::R0).addImm(0x3f);
224 MachineInstr *New = BuildMI(MBB, II, dl, TII.get(AddOpc), AVR::R29R28)
236 BuildMI(MBB, std::next(II), dl, TII.get(SubOpc), AVR::R29R28)
lib/Target/BPF/BPFISelLowering.cpp 744 BuildMI(*BB, BB->begin(), DL, TII.get(BPF::PHI), MI.getOperand(0).getReg())
lib/Target/BPF/BPFInstrInfo.cpp 36 BuildMI(MBB, I, DL, get(BPF::MOV_rr), DestReg)
39 BuildMI(MBB, I, DL, get(BPF::MOV_rr_32), DestReg)
157 BuildMI(MBB, I, DL, get(BPF::LDD), DestReg).addFrameIndex(FI).addImm(0);
159 BuildMI(MBB, I, DL, get(BPF::LDW32), DestReg).addFrameIndex(FI).addImm(0);
lib/Target/BPF/BPFRegisterInfo.cpp 90 BuildMI(MBB, ++II, DL, TII.get(BPF::ADD_ri), reg)
110 BuildMI(MBB, ++II, DL, TII.get(BPF::MOV_rr), reg)
112 BuildMI(MBB, II, DL, TII.get(BPF::ADD_ri), reg)
lib/Target/Hexagon/HexagonBitSimplify.cpp 1347 BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
1414 BuildMI(B, At, DL, HII.get(Hexagon::A2_tfrsi), Reg)
1421 BuildMI(B, At, DL, HII.get(Hexagon::A2_tfrpi), Reg)
1430 BuildMI(B, At, DL, HII.get(Opc), Reg)
1436 BuildMI(B, At, DL, HII.get(Hexagon::CONST64), Reg)
1449 BuildMI(B, At, DL, HII.get(Opc), Reg);
1610 BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
1629 BuildMI(B, At, DL, HII.get(TargetOpcode::REG_SEQUENCE), NewR)
2029 BuildMI(B, At, DL, HII.get(Hexagon::S2_packhl), NewR)
2058 BuildMI(B, At, DL, HII.get(Hexagon::A2_zxth), NewR)
2100 BuildMI(B, At, DL, HII.get(COpc), NewR)
2157 auto MIB = BuildMI(B, At, DL, HII.get(NewOpc), NewR)
2299 auto NewBS = BuildMI(B, At, DL, HII.get(Hexagon::A4_bitspliti), NewR)
2360 BuildMI(B, At, DL, HII.get(Hexagon::S2_tstbit_i), NewR)
2370 BuildMI(B, At, DL, HII.get(NewOpc), NewR);
2544 auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR)
2614 BuildMI(B, At, DL, HII.get(Hexagon::A2_tfrsi), NewR)
2679 BuildMI(B, At, DL, HII.get(Hexagon::C2_muxii), NewR)
3072 BuildMI(LB, At, At->getDebugLoc(), HII->get(TargetOpcode::PHI), PhiR)
3086 auto MIB = BuildMI(LB, At, DL, HII->get(SI->getOpcode()), NewDR);
3289 BuildMI(*C.PB, T, DL, HII->get(TfrI), PrehR)
lib/Target/Hexagon/HexagonConstExtenders.cpp 1542 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::PS_fi), DefR)
1549 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_tfrsi), DefR)
1554 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_subri), DefR)
1559 InitI = BuildMI(MBB, At, dl, HII->get(Hexagon::A2_addi), DefR)
1567 InitI = BuildMI(MBB, At, dl, HII->get(NewOpc), DefR)
lib/Target/Hexagon/HexagonConstPropagation.cpp 2875 const MachineInstrBuilder &MIB = BuildMI(B, At, DL, *NewD, NewR);
2901 NewMI = BuildMI(B, At, DL, *NewD, NewR)
2906 NewMI = BuildMI(B, At, DL, *NewD, NewR)
2913 NewMI = BuildMI(B, At, DL, *NewD, NewR)
2918 NewMI = BuildMI(B, At, DL, *NewD, NewR)
2984 NewMI = BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
3014 NewMI = BuildMI(B, At, DL, D, NewR)
3050 NewMI = BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
3082 NewMI = BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR)
lib/Target/Hexagon/HexagonCopyToCombine.cpp 659 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::CONST64), DoubleDestReg)
672 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
679 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
688 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
695 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
704 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
710 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
718 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
725 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
736 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
744 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineii), DoubleDestReg)
752 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A2_combineii), DoubleDestReg)
769 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
777 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
785 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
792 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
800 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineir), DoubleDestReg)
817 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
825 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
833 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
840 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
849 BuildMI(*BB, InsertPt, DL, TII->get(Hexagon::A4_combineri), DoubleDestReg)
877 BuildMI(*BB, InsertPt, DL, TII->get(NewOpc), DoubleDestReg)
lib/Target/Hexagon/HexagonEarlyIfConv.cpp 802 BuildMI(*B, At, DL, D, MuxR)
1001 NonPHI = BuildMI(*B, NonPHI, DL, HII->get(TargetOpcode::COPY), NewR)
lib/Target/Hexagon/HexagonFrameLowering.cpp 628 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_andir), SP)
640 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
659 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
674 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_add), SP)
762 BuildMI(MBB, InsertPt, dl, HII.get(Hexagon::A2_addi), SP)
1580 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), TmpR).add(MI->getOperand(1));
1581 BuildMI(B, It, DL, HII.get(TargetOpcode::COPY), DstR)
1607 BuildMI(B, It, DL, HII.get(TfrOpc), TmpR)
1636 BuildMI(B, It, DL, HII.get(Hexagon::L2_loadri_io), TmpR)
1645 BuildMI(B, It, DL, HII.get(TfrOpc), DstR)
1673 BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1676 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandqrt), TmpR1)
1708 BuildMI(B, It, DL, HII.get(Hexagon::A2_tfrsi), TmpR0)
1715 BuildMI(B, It, DL, HII.get(Hexagon::V6_vandvrt), DstR)
1809 BuildMI(B, It, DL, HII.get(LoadOpc), DstLo)
1817 BuildMI(B, It, DL, HII.get(LoadOpc), DstHi)
1873 BuildMI(B, It, DL, HII.get(LoadOpc), DstR)
2275 CopyIn = BuildMI(B, StartIt, DL, HII.get(TargetOpcode::COPY), FoundR)
2314 CopyOut = BuildMI(B, It, DL, HII.get(CopyOpc), DstR)
lib/Target/Hexagon/HexagonGenInsert.cpp 1433 BuildMI(B, At, DL, D, NewR)
lib/Target/Hexagon/HexagonGenMux.cpp 337 auto NewMux = BuildMI(B, MX.At, DL, HII->get(MxOpc), MX.DefR)
lib/Target/Hexagon/HexagonGenPredicate.cpp 274 BuildMI(B, std::next(DefIt), DL, TII->get(TargetOpcode::COPY), NewPR)
lib/Target/Hexagon/HexagonHardwareLoops.cpp 915 BuildMI(*PH, InsertPos, DL, SubD, SubR);
936 BuildMI(*PH, InsertPos, DL, SubD, SubR);
955 BuildMI(*PH, InsertPos, DL, AddD, AddR)
976 BuildMI(*PH, InsertPos, DL, LsrD, LsrR)
1248 BuildMI(*Preheader, InsertPos, DL, TII->get(TargetOpcode::COPY), CountReg)
1261 BuildMI(*Preheader, InsertPos, DL, TII->get(Hexagon::A2_tfrsi), CountReg)
lib/Target/Hexagon/HexagonInstrInfo.cpp 795 BuildMI(MBB, I, DL, get(Hexagon::A2_tfr), DestReg)
800 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrp), DestReg)
806 BuildMI(MBB, I, DL, get(Hexagon::C2_or), DestReg)
812 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
818 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrcrr), DestReg)
824 BuildMI(MBB, I, DL, get(Hexagon::A2_tfrrcr), DestReg)
830 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
836 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrrp), DestReg)
842 BuildMI(MBB, I, DL, get(Hexagon::C2_tfrpr), DestReg)
847 BuildMI(MBB, I, DL, get(Hexagon::V6_vassign), DestReg).
854 BuildMI(MBB, I, DL, get(Hexagon::V6_vcombine), DestReg)
860 BuildMI(MBB, I, DL, get(Hexagon::V6_pred_and), DestReg)
966 BuildMI(MBB, I, DL, get(Hexagon::L2_loadri_io), DestReg)
969 BuildMI(MBB, I, DL, get(Hexagon::L2_loadrd_io), DestReg)
972 BuildMI(MBB, I, DL, get(Hexagon::LDriw_pred), DestReg)
975 BuildMI(MBB, I, DL, get(Hexagon::LDriw_ctr), DestReg)
978 BuildMI(MBB, I, DL, get(Hexagon::PS_vloadrq_ai), DestReg)
989 BuildMI(MBB, I, DL, get(Opc), DestReg)
1000 BuildMI(MBB, I, DL, get(Opc), DestReg)
lib/Target/Hexagon/HexagonRegisterInfo.cpp 222 BuildMI(MB, II, DL, HII.get(Hexagon::A2_addi), TmpR)
lib/Target/Lanai/LanaiFrameLowering.cpp 122 BuildMI(MBB, MBBI, DL, LII.get(Lanai::ADD_I_LO), Lanai::FP)
130 BuildMI(MBB, MBBI, DL, LII.get(Lanai::SUB_I_LO), Lanai::SP)
186 BuildMI(MBB, MBBI, DL, LII.get(Lanai::ADD_I_LO), Lanai::SP)
191 BuildMI(MBB, MBBI, DL, LII.get(Lanai::LDW_RI), Lanai::FP)
lib/Target/Lanai/LanaiInstrInfo.cpp 44 BuildMI(MBB, Position, DL, get(Lanai::OR_I_LO), DestinationRegister)
82 BuildMI(MBB, Position, DL, get(Lanai::LDW_RI), DestinationRegister)
lib/Target/Lanai/LanaiRegisterInfo.cpp 188 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::MOVHI), Reg)
190 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::OR_I_LO), Reg)
195 BuildMI(*MI.getParent(), II, DL, TII->get(Lanai::ADD_I_LO), Reg)
201 BuildMI(*MI.getParent(), II, DL,
238 BuildMI(*MI.getParent(), II, DL, TII->get(NewOpcode),
lib/Target/MSP430/MSP430FrameLowering.cpp 70 BuildMI(MBB, MBBI, DL, TII.get(MSP430::MOV16rr), MSP430::FP)
98 BuildMI(MBB, MBBI, DL, TII.get(MSP430::SUB16ri), MSP430::SP)
135 BuildMI(MBB, MBBI, DL, TII.get(MSP430::POP16r), MSP430::FP);
156 BuildMI(MBB, MBBI, DL,
160 BuildMI(MBB, MBBI, DL,
170 BuildMI(MBB, MBBI, DL, TII.get(MSP430::ADD16ri), MSP430::SP)
220 BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());
lib/Target/MSP430/MSP430ISelLowering.cpp 1531 BuildMI(*RemBB, RemBB->begin(), dl, TII.get(MSP430::PHI), DstReg)
1600 BuildMI(*BB, BB->begin(), dl, TII.get(MSP430::PHI), MI.getOperand(0).getReg())
lib/Target/MSP430/MSP430InstrInfo.cpp 102 BuildMI(MBB, I, DL, get(Opc), DestReg)
lib/Target/MSP430/MSP430RegisterInfo.cpp 144 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::SUB16ri), DstReg)
147 BuildMI(MBB, std::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
lib/Target/Mips/Mips16FrameLowering.cpp 87 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
104 BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP)
lib/Target/Mips/Mips16ISelDAGToDAG.cpp 83 BuildMI(MBB, I, DL, TII.get(Mips::LiRxImmX16), V0)
85 BuildMI(MBB, I, DL, TII.get(Mips::AddiuRxPcImmX16), V1)
88 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16);
89 BuildMI(MBB, I, DL, TII.get(Mips::AdduRxRyRz16), GlobalBaseReg)
lib/Target/Mips/Mips16ISelLowering.cpp 563 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
627 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
693 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
lib/Target/Mips/Mips16InstrInfo.cpp 142 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
291 MachineInstrBuilder MIB1 = BuildMI(MBB, I, DL, get(Mips::LwConstant32), Reg1);
293 MachineInstrBuilder MIB2 = BuildMI(MBB, I, DL, get(Mips::MoveR3216), Reg2);
295 MachineInstrBuilder MIB3 = BuildMI(MBB, I, DL, get(Mips::AdduRxRyRz16), Reg1);
298 MachineInstrBuilder MIB4 = BuildMI(MBB, I, DL, get(Mips::Move32R16),
404 BuildMI(MBB, II, DL, get(Mips::LwConstant32), Reg).addImm(Imm).addImm(-1);
421 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(SpReg, RegState::Kill)
425 BuildMI(MBB, II, DL, get(Mips:: AdduRxRyRz16), Reg).addReg(FrameReg)
lib/Target/Mips/MipsBranchExpansion.cpp 456 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
480 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
502 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
505 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
517 BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::ADDiu), Mips::SP)
525 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
579 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
586 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
591 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
613 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
616 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
623 BuildMI(*BalTgtMBB, std::prev(Pos), DL, TII->get(Mips::DADDiu),
628 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
676 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi2Op_64),
679 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu2Op),
683 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
686 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu2Op),
690 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
693 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu2Op),
698 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi2Op),
701 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_ADDiu2Op),
724 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
726 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
lib/Target/Mips/MipsFastISel.cpp 215 return BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
346 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
804 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1233 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1303 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1473 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1562 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::JALR),
1768 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2140 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
lib/Target/Mips/MipsISelLowering.cpp 1523 BuildMI(*BB, II, DL, TII->get(Mips::COPY), IncrCopy).addReg(Incr);
1524 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1756 BuildMI(*BB, II, DL, TII->get(Mips::COPY), PtrCopy).addReg(Ptr);
1757 BuildMI(*BB, II, DL, TII->get(Mips::COPY), OldValCopy).addReg(OldVal);
1758 BuildMI(*BB, II, DL, TII->get(Mips::COPY), NewValCopy).addReg(NewVal);
4481 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4551 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(0).getReg())
4556 BuildMI(*BB, BB->begin(), DL, TII->get(Mips::PHI), MI.getOperand(1).getReg())
lib/Target/Mips/MipsMachineFunction.cpp 88 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
90 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
92 BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
102 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
104 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
117 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
119 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
120 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
146 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
lib/Target/Mips/MipsOptimizePICCall.cpp 156 BuildMI(*MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), DstReg)
lib/Target/Mips/MipsSEFrameLowering.cpp 178 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), Dst)
192 BuildMI(MBB, I, I->getDebugLoc(), TII.get(TargetOpcode::COPY), VR)
216 BuildMI(MBB, I, DL, Desc, Lo).addReg(VR0, RegState::Kill);
218 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill);
238 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
240 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
272 BuildMI(MBB, I, DL, TII.get(MFLoOpc), VR0).addReg(Src);
273 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstLo)
275 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill);
276 BuildMI(MBB, I, DL, TII.get(TargetOpcode::COPY), DstHi)
350 BuildMI(MBB, I, I->getDebugLoc(), TII.get(Mips::IMPLICIT_DEF), DstReg);
529 BuildMI(MBB, MBBI, dl, TII.get(MOVE), FP).addReg(SP).addReg(ZERO)
546 BuildMI(MBB, MBBI, dl, TII.get(ADDiu), VR).addReg(ZERO) .addImm(MaxAlign);
547 BuildMI(MBB, MBBI, dl, TII.get(AND), SP).addReg(SP).addReg(VR);
552 BuildMI(MBB, MBBI, dl, TII.get(MOVE), BP)
598 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K0)
603 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::EXT), Mips::K0)
612 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
623 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MFC0), Mips::K1)
657 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
665 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
674 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::INS), Mips::K1)
682 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
715 BuildMI(MBB, I, DL, TII.get(MOVE), SP).addReg(FP).addReg(ZERO);
757 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::DI), Mips::ZERO);
764 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP014)
772 BuildMI(MBB, MBBI, DL, STI.getInstrInfo()->get(Mips::MTC0), Mips::COP012)
828 BuildMI(MBB, MI, DL, TII.get(Op), Mips::K0)
lib/Target/Mips/MipsSEISelLowering.cpp 3068 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
3074 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
3078 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3137 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3143 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
3147 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
lib/Target/Mips/MipsSEInstrInfo.cpp 111 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
304 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
307 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
310 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
313 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
380 BuildMI(MBB, I, DL, get(Opc), DestReg)
400 BuildMI(MBB, I, DL, get(Opc), Reg)
592 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
602 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
634 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
636 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
641 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
715 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
768 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
769 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
806 BuildMI(MBB, I, dl,
812 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
847 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
862 BuildMI(MBB, I, dl,
871 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
894 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
897 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
900 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
lib/Target/Mips/MipsSERegisterInfo.cpp 229 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAddiuOp()), Reg)
247 BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg)
lib/Target/NVPTX/NVPTXInstrInfo.cpp 68 BuildMI(MBB, I, DL, get(Op), DestReg)
lib/Target/PowerPC/PPCFastISel.cpp 158 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
436 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
541 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
549 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
576 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
948 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
951 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CmpOpc), DestReg)
993 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
998 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1003 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1098 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1142 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1253 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1348 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
1366 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1480 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1527 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::FRSP),
1728 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1785 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1822 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
1834 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLWINM),
1847 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2028 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocCPT),
2031 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2035 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8),
2041 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
2043 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2047 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), DestReg)
2079 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtoc),
2093 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDIStocHA8),
2097 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::LDtocL),
2101 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDItocL),
2120 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2126 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2129 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2134 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2174 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::RLDICR),
2182 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORIS8),
2189 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ORI8),
2205 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2225 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ImmReg)
2277 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(PPC::ADDI8),
2387 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
lib/Target/PowerPC/PPCFrameLowering.cpp 978 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
988 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
1003 BuildMI(MBB, MBBI, dl, TII.get(MfcrOpcode), TempReg);
1050 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
1062 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
1067 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
1073 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
1078 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
1080 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
1083 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
1088 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
1095 BuildMI(MBB, StackUpdateLoc, dl, StoreUpdtInst, SPReg)
1101 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1103 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1106 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
1136 BuildMI(MBB, MBBI, dl, TII.get(PPC::SUBF), ScratchReg)
1147 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1159 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1170 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), ScratchReg)
1179 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDIC), BPReg)
1204 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
1229 BuildMI(MBB, MBBI, dl, TII.get(PPC::ADDI), BPReg)
1295 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1548 BuildMI(MBB, MBBI, dl, AddImmInst, RBReg)
1551 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1553 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1563 BuildMI(MBB, StackUpdateLoc, dl, AddImmInst, SPReg)
1582 BuildMI(MBB, MBBI, dl, OrInst, ScratchReg)
1587 BuildMI(MBB, StackUpdateLoc, dl, LoadInst, RBReg)
1606 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1610 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1620 BuildMI(MBB, StackUpdateLoc, dl, LoadInst, ScratchReg)
1630 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
1639 BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
1643 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1649 BuildMI(MBB, MBBI, dl, LoadInst, PPC::R30)
1654 BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
1664 BuildMI(MBB, MBBI, dl, OrInst, SPReg)
1668 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1674 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
1680 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
1688 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
1705 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1708 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
1710 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
2257 BuildMI(MBB, MI, DL, TII.get(PPC::MTVSRD), CSI[i].getDstReg())
2327 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
2332 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
2334 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
2337 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
2414 BuildMI(MBB, I, DL, TII.get(PPC::MFVSRD), Reg)
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 405 BuildMI(EntryBB, IP, dl, TII.get(PPC::MFVRSAVE), InVRSAVE);
406 BuildMI(EntryBB, IP, dl, TII.get(PPC::UPDATE_VRSAVE),
445 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
449 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
451 BuildMI(FirstMBB, MBBI, dl,
460 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR), GlobalBaseReg);
475 BuildMI(FirstMBB, MBBI, dl, TII.get(PPC::MFLR8), GlobalBaseReg);
lib/Target/PowerPC/PPCISelLowering.cpp10603 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest)
10742 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
10991 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::PHI), MI.getOperand(0).getReg())
11427 BuildMI(*BB, BB->begin(), dl, TII->get(PPC::SRW), dest)
15057 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
15062 BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
lib/Target/PowerPC/PPCInstrInfo.cpp 868 BuildMI(MBB, MI, dl, get(TargetOpcode::COPY), FirstReg)
872 BuildMI(MBB, MI, dl, get(OpCode), DestReg)
935 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(CRReg);
939 BuildMI(MBB, I, DL, get(PPC::RLWINM), DestReg)
947 BuildMI(MBB, I, DL, get(PPC::MFOCRF8), DestReg).addReg(SrcReg);
952 BuildMI(MBB, I, DL, get(PPC::MFOCRF), DestReg).addReg(SrcReg);
959 BuildMI(MBB, I, DL, get(PPC::MTVSRD), DestReg).addReg(SrcReg);
967 BuildMI(MBB, I, DL, get(PPC::MFVSRD), DestReg).addReg(SrcReg);
972 BuildMI(MBB, I, DL, get(PPC::EFSCFD), DestReg).addReg(SrcReg);
977 BuildMI(MBB, I, DL, get(PPC::EFDCFS), DestReg).addReg(SrcReg);
1021 BuildMI(MBB, I, DL, MCID, DestReg)
1024 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc));
1913 BuildMI(*MI->getParent(), std::next(MII), MI->getDebugLoc(),
lib/Target/PowerPC/PPCMIPeephole.cpp 1297 BuildMI(MBB2, MBB2.begin(), DL,
lib/Target/PowerPC/PPCRegisterInfo.cpp 533 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), Reg)
537 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), Reg)
541 BuildMI(MBB, II, dl, TII.get(PPC::LD), Reg)
545 BuildMI(MBB, II, dl, TII.get(PPC::LWZ), Reg)
562 BuildMI(MBB, II, dl, TII.get(PPC::LI8), NegSizeReg)
567 BuildMI(MBB, II, dl, TII.get(PPC::AND8), NegSizeReg)
573 BuildMI(MBB, II, dl, TII.get(PPC::STDUX), PPC::X1)
577 BuildMI(MBB, II, dl, TII.get(PPC::ADDI8), MI.getOperand(0).getReg())
587 BuildMI(MBB, II, dl, TII.get(PPC::LI), NegSizeReg)
592 BuildMI(MBB, II, dl, TII.get(PPC::AND), NegSizeReg)
598 BuildMI(MBB, II, dl, TII.get(PPC::STWUX), PPC::R1)
602 BuildMI(MBB, II, dl, TII.get(PPC::ADDI), MI.getOperand(0).getReg())
628 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI),
662 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
672 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
707 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
718 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
723 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF), DestReg)
773 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LI8 : PPC::LI), Reg)
777 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LIS8 : PPC::LIS), Reg)
786 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), Reg)
797 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWINM8 : PPC::RLWINM), Reg)
830 addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ),
833 BuildMI(MBB, II, dl, TII.get(TargetOpcode::IMPLICIT_DEF), DestReg);
836 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MFOCRF8 : PPC::MFOCRF), RegO)
841 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::RLWIMI8 : PPC::RLWIMI), RegO)
848 BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::MTOCRF8 : PPC::MTOCRF),
875 BuildMI(MBB, II, dl, TII.get(PPC::MFVRSAVEv), Reg)
903 addFrameReference(BuildMI(MBB, II, dl, TII.get(PPC::LWZ),
906 BuildMI(MBB, II, dl, TII.get(PPC::MTVRSAVEv), DestReg)
1101 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LI8 : PPC::LI), SReg)
1104 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::LIS8 : PPC::LIS), SRegHi)
1106 BuildMI(MBB, II, dl, TII.get(is64Bit ? PPC::ORI8 : PPC::ORI), SReg)
1237 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
lib/Target/PowerPC/PPCTLSDynamicCall.cpp 116 MachineInstr *Addi = BuildMI(MBB, I, DL, TII->get(Opc1), GPR3)
125 MachineInstr *Call = (BuildMI(MBB, I, DL, TII->get(Opc2), GPR3)
132 BuildMI(MBB, I, DL, TII->get(TargetOpcode::COPY), OutReg)
lib/Target/PowerPC/PPCVSXSwapRemoval.cpp 802 BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
916 BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
924 BuildMI(*MI->getParent(), InsertPoint, MI->getDebugLoc(),
lib/Target/RISCV/RISCVFrameLowering.cpp 74 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI), DestReg)
88 BuildMI(MBB, MBBI, DL, TII->get(Opc), DestReg)
213 BuildMI(MBB, MBBI, DL, TII->get(RISCV::ANDI), SPReg)
220 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SRLI), VR)
223 BuildMI(MBB, MBBI, DL, TII->get(RISCV::SLLI), SPReg)
lib/Target/RISCV/RISCVISelLowering.cpp 1334 BuildMI(*TailMBB, InsertionPoint, SelectMBBI->getDebugLoc(),
lib/Target/RISCV/RISCVInstrInfo.cpp 90 BuildMI(MBB, MBBI, DL, get(RISCV::ADDI), DstReg)
105 BuildMI(MBB, MBBI, DL, get(Opc), DstReg)
158 BuildMI(MBB, I, DL, get(Opcode), DstReg).addFrameIndex(FI).addImm(0);
186 BuildMI(MBB, MBBI, DL, get(RISCV::LUI), Result)
190 BuildMI(MBB, MBBI, DL, get(Inst.Opc), Result)
399 MachineInstr &LuiMI = *BuildMI(MBB, II, DL, get(RISCV::LUI), ScratchReg)
lib/Target/RISCV/RISCVRegisterInfo.cpp 133 BuildMI(MBB, II, DL, TII->get(RISCV::ADD), ScratchReg)
lib/Target/Sparc/SparcFrameLowering.cpp 52 BuildMI(MBB, MBBI, dl, TII.get(ADDri), SP::O6)
64 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
66 BuildMI(MBB, MBBI, dl, TII.get(SP::ORri), SP::G1)
68 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
77 BuildMI(MBB, MBBI, dl, TII.get(SP::SETHIi), SP::G1)
79 BuildMI(MBB, MBBI, dl, TII.get(SP::XORri), SP::G1)
81 BuildMI(MBB, MBBI, dl, TII.get(ADDrr), SP::O6)
186 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), regUnbiased)
193 BuildMI(MBB, MBBI, dl, TII.get(SP::ANDNri), regUnbiased)
198 BuildMI(MBB, MBBI, dl, TII.get(SP::ADDri), SP::O6)
230 BuildMI(MBB, MBBI, dl, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
lib/Target/Sparc/SparcISelLowering.cpp 3161 BuildMI(*SinkMBB, SinkMBB->begin(), dl, TII.get(SP::PHI),
lib/Target/Sparc/SparcInstrInfo.cpp 322 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0)
330 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg)
334 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg)
345 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg)
361 BuildMI(MBB, I, DL, get(SP::WRASRrr), DestReg)
366 BuildMI(MBB, I, DL, get(SP::RDASR), DestReg)
382 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(movOpc), Dst);
448 BuildMI(MBB, I, DL, get(SP::LDXri), DestReg).addFrameIndex(FI).addImm(0)
451 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0)
454 BuildMI(MBB, I, DL, get(SP::LDDri), DestReg).addFrameIndex(FI).addImm(0)
457 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0)
460 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0)
465 BuildMI(MBB, I, DL, get(SP::LDQFri), DestReg).addFrameIndex(FI).addImm(0)
489 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
lib/Target/Sparc/SparcRegisterInfo.cpp 132 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
137 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
150 BuildMI(*MI.getParent(), II, dl, TII.get(SP::SETHIi), SP::G1)
152 BuildMI(*MI.getParent(), II, dl, TII.get(SP::XORri), SP::G1)
155 BuildMI(*MI.getParent(), II, dl, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
201 BuildMI(*MI.getParent(), II, dl, TII.get(SP::LDDFri), DestEvenReg)
lib/Target/SystemZ/SystemZFrameLowering.cpp 333 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII->get(Opcode), Reg)
418 BuildMI(MBB, MBBI, DL, ZII->get(SystemZ::LGR), SystemZ::R11D)
lib/Target/SystemZ/SystemZISelLowering.cpp 6606 BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(SystemZ::PHI), DestReg)
lib/Target/SystemZ/SystemZInstrInfo.cpp 262 return BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
266 return BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
590 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), TReg).addReg(TrueReg);
591 BuildMI(MBB, I, DL, get(TargetOpcode::COPY), FReg).addReg(FalseReg);
603 BuildMI(MBB, I, DL, get(Opc), DstReg)
801 BuildMI(MBB, MBBI, DL, get(SystemZ::VMRHG), DestReg)
817 BuildMI(MBB, MBBI, DL, get(SystemZ::VREPG), DestRegLo)
824 auto MIB = BuildMI(MBB, MBBI, DL, get(SystemZ::IPM), DestReg);
867 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
896 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
1748 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
lib/Target/SystemZ/SystemZPostRewrite.cpp 122 BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
129 BuildMI(*MBBI->getParent(), MBBI, MBBI->getDebugLoc(),
200 BuildMI(*MoveMBB, MoveMBB->end(), DL, TII->get(SystemZ::COPY), DestReg)
lib/Target/SystemZ/SystemZRegisterInfo.cpp 317 BuildMI(MBB, MI, DL, TII->get(LAOpcode),ScratchReg)
323 BuildMI(MBB, MI, DL, TII->get(SystemZ::AGR),ScratchReg)
lib/Target/WebAssembly/WebAssemblyFastISel.cpp 388 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), Reg)
463 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
468 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
493 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
498 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
504 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
522 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
544 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
583 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
591 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(WebAssembly::COPY),
607 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
626 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
713 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
937 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
955 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1053 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1114 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
1204 auto MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
lib/Target/WebAssembly/WebAssemblyFrameLowering.cpp 180 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::GLOBAL_GET_I32), SPReg)
188 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::COPY), BasePtr)
194 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
196 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::SUB_I32),
206 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), BitmaskReg)
208 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::AND_I32),
217 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::COPY), WebAssembly::FP32)
248 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::CONST_I32), OffsetReg)
253 BuildMI(MBB, InsertPt, DL, TII->get(WebAssembly::ADD_I32), SPReg)
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 415 BuildMI(*DoneMBB, DoneMBB->begin(), DL, TII.get(TargetOpcode::PHI), OutReg)
lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp 83 BuildMI(MBB, I, DL, get(CopyOpcode), DestReg)
lib/Target/WebAssembly/WebAssemblyLateEHPrepare.cpp 136 BuildMI(MBB, InsertPos, MBB.begin()->getDebugLoc(),
lib/Target/WebAssembly/WebAssemblyPrepareForLiveIntervals.cpp 108 BuildMI(Entry, Entry.begin(), DebugLoc(),
lib/Target/X86/X86CmovConversion.cpp 834 MIB = BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(X86::PHI), DestReg)
lib/Target/X86/X86ExpandPseudo.cpp 92 BuildMI(*MBB, MBBI, DL, TII->get(X86::LEA64r), X86::R11)
292 BuildMI(MBB, MBBI, DL,
lib/Target/X86/X86FastISel.cpp 471 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
501 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
792 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), LoadReg);
1251 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1270 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1439 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV32r0),
1449 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV8ri),
1491 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
1493 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
1495 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(SETFOpc[2]),
1513 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
1551 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(MovInst), Result32)
1555 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::SUBREG_TO_REG),
1562 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOVZX32rr8),
1598 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::NEG8r),
1608 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOVSX32rr8),
1764 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1831 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpcode::COPY),
1837 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1842 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(OpReg), ResultReg)
1943 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1952 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1959 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1963 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1967 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1990 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
1994 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SHR16ri),
2004 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Copy), ResultReg)
2070 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
2072 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
2077 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, TmpReg)
2110 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2215 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2227 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2248 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2274 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2328 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2381 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2451 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2483 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2490 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(TargetOpc),
2638 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2660 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2703 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2715 addDirectMem(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2841 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2847 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc),
2923 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2950 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2961 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
2978 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::SETCCr),
3048 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg)
3146 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3404 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3446 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3467 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV8ri),
3573 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3589 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3704 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3793 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV64ri),
3796 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3806 addConstantPoolReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3831 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(X86::MOV64ri),
3839 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3886 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
3919 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg);
3989 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg)
4000 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
lib/Target/X86/X86FixupLEAs.cpp 395 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
400 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
416 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
419 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
426 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
430 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
510 BuildMI(MBB, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src);
518 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), ADDri, DstR)
583 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
589 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
617 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
622 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpc), DestReg)
lib/Target/X86/X86FlagsCopyLowering.cpp 744 auto SetI = BuildMI(TestMBB, TestPos, TestLoc,
lib/Target/X86/X86FrameLowering.cpp 275 BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Reg)
278 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AddSubRROpc), StackPtr)
301 BuildMI(MBB, MBBI, DL, TII.get(MovRIOpc), Rax)
304 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(X86::ADD64rr), Rax)
310 BuildMI(MBB, MBBI, DL, TII.get(X86::XCHG64rm), Rax).addReg(Rax),
313 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), StackPtr),
377 MI = addRegOffset(BuildMI(MBB, MBBI, DL,
386 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
720 addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
724 addRegOffset(BuildMI(*ContinueMBB, ContinueMBBI, DL,
732 BuildMI(*ContinueMBB, ContinueMBBI, DL, TII.get(X86::SUB64rr), X86::RSP)
789 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::R11)
812 BuildMI(MBB, MBBI, DL, TII.get(getSUBrrOpcode(Uses64BitFramePtr)), SP)
866 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(AndOp), Reg)
1136 BuildMI(MBB, MBBI, DL,
1267 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1271 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri32), X86::RAX)
1275 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64ri), X86::RAX)
1282 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
1324 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rm), Establisher),
1350 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), FramePtr),
1353 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV64rr), FramePtr)
1449 BuildMI(MBB, MBBI, DL, TII.get(Opc), BasePtr)
1641 BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::POP64r : X86::POP32r),
1702 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr),
1707 BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr)
2149 BuildMI(MBB, MBBI, DL, TII.get(X86::LEA64r), X86::RAX)
2157 BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX)
2215 BuildMI(MBB, MI, DL, TII.get(Opc), Reg)
2786 BuildMI(MBB, MBBI, DL,
2966 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), X86::ESP),
2979 BuildMI(MBB, MBBI, DL, TII.get(ADDri), FramePtr)
2989 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::LEA32r), BasePtr),
2997 addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32rm), FramePtr),
lib/Target/X86/X86ISelLowering.cpp29242 BuildMI(*sinkMBB, sinkMBB->begin(), DL, TII->get(X86::PHI), DstReg)
29500 BuildMI(*endMBB, endMBB->begin(), DL,
29700 MIB = BuildMI(*SinkMBB, SinkInsertionPoint, DL, TII->get(X86::PHI), DestReg)
29848 BuildMI(*SinkMBB, SinkMBB->begin(), DL, TII->get(X86::PHI), DestReg)
29858 BuildMI(*SinkMBB, std::next(MachineBasicBlock::iterator(MIB.getInstr())), DL,
30132 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI),
30593 BuildMI(*sinkMBB, sinkMBB->begin(), DL,
46202 BuildMI(*Entry, MBBI, DebugLoc(), TII->get(TargetOpcode::COPY), NewVR)
46207 BuildMI(*Exit, Exit->getFirstTerminator(), DebugLoc(),
lib/Target/X86/X86InstrInfo.cpp 797 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), InRegLEA);
804 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opcode), OutRegLEA);
2876 BuildMI(MBB, I, DL, get(Opc), DstReg)
3031 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3272 addFrameReference(BuildMI(MBB, MI, DebugLoc(), get(Opc), DestReg), FrameIdx);
3996 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
7776 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PC)
7791 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::LEA64r), PBReg)
7798 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOV64ri), GOTReg)
7801 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD64rr), PC)
7810 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
7817 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
lib/Target/X86/X86SpeculativeLoadHardening.cpp 447 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::MOV64ri32), PS->PoisonReg)
481 auto ZeroI = BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::MOV32r0),
489 BuildMI(Entry, EntryInsertPt, Loc, TII->get(X86::SUBREG_TO_REG),
756 auto CMovI = BuildMI(CheckingMBB, InsertPt, DebugLoc(),
1109 auto AddrI = BuildMI(*Pred, InsertPt, DebugLoc(),
1117 auto AddrI = BuildMI(*Pred, InsertPt, DebugLoc(), TII->get(X86::LEA64r),
1158 BuildMI(MBB, InsertPt, DebugLoc(), TII->get(X86::LEA64r), AddrReg)
1180 BuildMI(MBB, InsertPt, DebugLoc(), TII->get(CMovOp), UpdatedStateReg)
1884 BuildMI(MBB, InsertPt, Loc, TII->get(X86::COPY), Reg).addReg(X86::EFLAGS);
1897 BuildMI(MBB, InsertPt, Loc, TII->get(X86::COPY), X86::EFLAGS).addReg(Reg);
1912 auto ShiftI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::SHL64ri), TmpReg)
1917 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(X86::OR64rr), X86::RSP)
1934 BuildMI(MBB, InsertPt, Loc, TII->get(TargetOpcode::COPY), TmpReg)
1937 BuildMI(MBB, InsertPt, Loc, TII->get(X86::SAR64ri), PredStateReg)
2296 BuildMI(MBB, InsertPt, Loc, TII->get(TargetOpcode::COPY), NarrowStateReg)
2308 auto OrI = BuildMI(MBB, InsertPt, Loc, TII->get(OrOpCode), NewReg)
lib/Target/X86/X86WinAllocaExpander.cpp 238 BuildMI(*MBB, I, DL,
256 BuildMI(*MBB, I, DL,
lib/Target/XCore/XCoreFrameLowering.cpp 129 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm);
202 BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg)
242 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDWSP_ru6), XCore::R11).addImm(0);
307 BuildMI(MBB, MBBI, dl, TII.get(XCore::LDAWSP_ru6), FramePtr).addImm(0);
409 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(RemainingAdj);
lib/Target/XCore/XCoreISelLowering.cpp 1575 BuildMI(*BB, BB->begin(), dl, TII.get(XCore::PHI), MI.getOperand(0).getReg())
lib/Target/XCore/XCoreInstrInfo.cpp 339 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg)
346 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0);
396 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg)
435 return BuildMI(MBB, MI, dl, get(XCore::MKMSK_rus), Reg)
441 return BuildMI(MBB, MI, dl, get(Opcode), Reg).addImm(Value).getInstr();
447 return BuildMI(MBB, MI, dl, get(XCore::LDWCP_lru6), Reg)
lib/Target/XCore/XCoreRegisterInfo.cpp 70 BuildMI(MBB, II, dl, TII.get(XCore::LDW_2rus), Reg)
83 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l2rus), Reg)
106 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
119 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)
140 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
153 BuildMI(MBB, II, dl, TII.get(NewOpcode), Reg)
176 BuildMI(MBB, II, dl, TII.get(XCore::LDAWSP_ru6), ScratchBase).addImm(0);
183 BuildMI(MBB, II, dl, TII.get(XCore::LDW_3r), Reg)
196 BuildMI(MBB, II, dl, TII.get(XCore::LDAWF_l3r), Reg)