reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/LiveDebugVariables.cpp

 1276     if (I->definesRegister(Reg, &TRI))

lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp

  127     if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) {
  127     if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) {

lib/Target/AArch64/AArch64InstrInfo.cpp

 1092   if (MI.definesRegister(AArch64::WZR) || MI.definesRegister(AArch64::XZR))
 1092   if (MI.definesRegister(AArch64::WZR) || MI.definesRegister(AArch64::XZR))
 1190     if (CmpInstr.definesRegister(AArch64::WZR) ||
 1191         CmpInstr.definesRegister(AArch64::XZR)) {

lib/Target/AArch64/AArch64MacroFusion.cpp

  238     if (FirstMI->definesRegister(AArch64::WZR))
  256     if (FirstMI->definesRegister(AArch64::XZR))

lib/Target/AArch64/AArch64RedundantCopyElimination.cpp

  269     if (PredI.definesRegister(AArch64::NZCV))

lib/Target/AMDGPU/AMDGPUMacroFusion.cpp

   49     return FirstMI->definesRegister(Src2->getReg(), TRI);

lib/Target/AMDGPU/SIFixSGPRCopies.cpp

  572         if (R->readsRegister(Reg, TRI) || R->definesRegister(Reg, TRI) ||

lib/Target/AMDGPU/SIInsertSkips.cpp

  362       if (!A->definesRegister(CondReg, TRI) || A->getOpcode() != And)
  388       if (M->definesRegister(SReg, TRI))

lib/Target/AMDGPU/SIInstrInfo.cpp

  617         if (!Def->definesRegister(SrcReg, &RI))
 6547       InsPt->definesRegister(Src)) {

lib/Target/ARM/ARMBaseInstrInfo.cpp

 1606   if (!MI.definesRegister(DstRegD, TRI) || MI.readsRegister(DstRegD, TRI))
 1986   if (!MI.isCall() && MI.definesRegister(ARM::SP))
 4906   if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) {
 5186     if (!DReg || !MI.definesRegister(DReg, TRI))
 5215   assert(MI.definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");

lib/Target/ARM/ARMISelLowering.cpp

10375     if (mi.definesRegister(ARM::CPSR))

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

  559     if (MBBI->killsRegister(Base) || MBBI->definesRegister(Base))
 1978   if (Prev->getOpcode() != ARM::tMOVr || !Prev->definesRegister(ARM::LR))

lib/Target/ARM/Thumb2InstrInfo.cpp

  486         !MI.definesRegister(ARM::CPSR)) {

lib/Target/Mips/MipsDelaySlotFiller.cpp

  372   if (MI.definesRegister(Mips::RA) || MI.definesRegister(Mips::RA_64)) {
  372   if (MI.definesRegister(Mips::RA) || MI.definesRegister(Mips::RA_64)) {

lib/Target/PowerPC/PPCInstrInfo.cpp

 1395     if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
 1395     if (I->definesRegister(PPC::CTR) || I->definesRegister(PPC::CTR8))
 1982         if (!MI->definesRegister(*ImpDefs))
 1992   assert(MI->definesRegister(PPC::CR0) &&

lib/Target/PowerPC/PPCRegisterInfo.cpp

  704   assert(MI.definesRegister(DestReg) &&
  827   assert(MI.definesRegister(DestReg) &&
  900   assert(MI.definesRegister(DestReg) &&

lib/Target/SystemZ/SystemZElimCompare.cpp

  613     if (MI.definesRegister(SystemZ::CC)) {

lib/Target/SystemZ/SystemZISelLowering.cpp

 6529     if (mi.definesRegister(SystemZ::CC))
 6638     if (NextMIIt->definesRegister(SystemZ::CC))

lib/Target/WebAssembly/WebAssemblyRegStackify.cpp

   84   if (!MI->definesRegister(WebAssembly::VALUE_STACK))
  340     if (MO.isDead() && Insert->definesRegister(Reg) &&

lib/Target/X86/X86CmovConversion.cpp

  338       if (I.definesRegister(X86::EFLAGS)) {
  577     if (I->definesRegister(X86::EFLAGS))

lib/Target/X86/X86ISelLowering.cpp

29601     if (mi.definesRegister(X86::EFLAGS))
31391     while (RMBBI != BB->rend() && (RMBBI->definesRegister(X86::EAX) ||
31392                                    RMBBI->definesRegister(X86::EBX) ||
31393                                    RMBBI->definesRegister(X86::ECX) ||
31394                                    RMBBI->definesRegister(X86::EDX))) {

lib/Target/X86/X86InstrInfo.cpp

 3632         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");