reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

lib/CodeGen/LivePhysRegs.cpp

  195       removeReg(Info.getReg());
  206     Pristine.removeReg(Info.getReg());
  229           addReg(Info.getReg());

lib/CodeGen/LiveRegUnits.cpp

  111       removeReg(Info.getReg());
  122     Pristine.removeReg(Info.getReg());

lib/CodeGen/MIRPrinter.cpp

  415     printRegMIR(CSInfo.getReg(), Reg, TRI);

lib/CodeGen/MachineFrameInfo.cpp

  130     for (MCSubRegIterator S(I.getReg(), TRI, true); S.isValid(); ++S)

lib/CodeGen/PrologEpilogInserter.cpp

  417       unsigned Reg = CS.getReg();
  508       MCPhysReg Reg = CSI[i].getReg();
  544       unsigned Reg = CS.getReg();
  573       unsigned Reg = CI.getReg();

lib/CodeGen/TargetFrameLoweringImpl.cpp

   73     CalleeSaves.set(Info.getReg());

lib/Target/AArch64/AArch64FrameLowering.cpp

  338     if (Info.getReg() == AArch64::LR)
  359     unsigned Reg = Info.getReg();
 1853     RPI.Reg1 = CSI[i].getReg();
 1866       unsigned NextReg = CSI[i + 1].getReg();

lib/Target/AMDGPU/SIFrameLowering.cpp

 1087     if (CS.getReg() == FuncInfo->getFrameOffsetReg()) {

lib/Target/AMDGPU/SILowerSGPRSpills.cpp

   99       unsigned Reg = CS.getReg();
  134       unsigned Reg = CI.getReg();

lib/Target/ARC/ARCFrameLowering.cpp

   81     assert(Reg.getReg() >= ARC::R13 && Reg.getReg() <= ARC::R25 &&
   81     assert(Reg.getReg() >= ARC::R13 && Reg.getReg() <= ARC::R25 &&
   83     if (Reg.getReg() > Last)
   84       Last = Reg.getReg();
  224     unsigned Reg = Entry.getReg();
  340     if (reg == I->getReg())
  386     if (I.getReg() > ARC::R12)

lib/Target/ARM/ARMFrameLowering.cpp

  416     unsigned Reg = CSI[i].getReg();
  625       unsigned Reg = Entry.getReg();
  658       unsigned Reg = Entry.getReg();
  685       unsigned Reg = Entry.getReg();
  991       unsigned Reg = CSI[i-1].getReg();
 1081       unsigned Reg = Info.getReg();
 1177     unsigned DNum = CSI[i].getReg() - ARM::D8;
 1348     if (CSI[i].getReg() == ARM::D8) {

lib/Target/ARM/ARMLoadStoreOptimizer.cpp

 1959         if (Info.getReg() == ARM::LR) {

lib/Target/ARM/Thumb1FrameLowering.cpp

  207     unsigned Reg = CSI[i].getReg();
  269     unsigned Reg = I->getReg();
  350     unsigned Reg = I.getReg();
  378       unsigned Reg = I.getReg();
  533         unsigned Reg = I.getReg();
  574     if (CSI.getReg() == ARM::LR)
  827     unsigned Reg = CSI[i-1].getReg();
  953     unsigned Reg = I.getReg();
 1027     unsigned Reg = Info.getReg();

lib/Target/AVR/AVRFrameLowering.cpp

  251     unsigned Reg = CSI[i - 1].getReg();
  290     unsigned Reg = CCSI.getReg();

lib/Target/Hexagon/HexagonFrameLowering.cpp

  271     unsigned Max = getMax32BitSubRegister(CSI[0].getReg(), TRI);
  273       unsigned Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI);
  538         RetI->addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
  788       if (!MBB.isLiveIn(R.getReg()))
  789         MBB.addLiveIn(R.getReg());
  820         RetI.addOperand(MachineOperand::CreateReg(R.getReg(), false, true));
  829       if (!MBB.isLiveIn(R.getReg()))
  830         MBB.addLiveIn(R.getReg());
  940       return C.getReg() == Reg;
 1259       MBB.addLiveIn(CSI[I].getReg());
 1264     unsigned Reg = CSI[i].getReg();
 1333     unsigned Reg = CSI[i].getReg();
 1441     unsigned R = CSI[i].getReg();
 1545       dbgs() << ' ' << printReg(CSI[i].getReg(), TRI) << ":fi#" << FI << ":sp";
 2413     MI->addOperand(MachineOperand::CreateReg(R.getReg(), IsDef, true, IsKill));
 2434     unsigned R = CSI[i].getReg();

lib/Target/MSP430/MSP430FrameLowering.cpp

  196     unsigned Reg = CSI[i-1].getReg();
  220     BuildMI(MBB, MI, DL, TII.get(MSP430::POP16r), CSI[i].getReg());

lib/Target/Mips/Mips16FrameLowering.cpp

   78       unsigned Reg = I->getReg();
  130     unsigned Reg = CSI[i].getReg();

lib/Target/Mips/Mips16InstrInfo.cpp

  197     unsigned Reg = CSI[e-i-1].getReg();

lib/Target/Mips/MipsAsmPrinter.cpp

  341     unsigned Reg = I.getReg();

lib/Target/Mips/MipsSEFrameLowering.cpp

  458       unsigned Reg = I->getReg();
  806     unsigned Reg = CSI[i].getReg();

lib/Target/PowerPC/PPCFrameLowering.cpp

 1316       unsigned Reg = CSI[I].getReg();
 1885     unsigned Reg = CSI[i].getReg();
 2033       unsigned Reg = CSI[i].getReg();
 2054       unsigned Reg = CSI[i].getReg();
 2166     unsigned Reg = CS.getReg();
 2204     unsigned Reg = CSI[i].getReg();
 2376     unsigned Reg = CSI[i].getReg();

lib/Target/PowerPC/PPCRegisterInfo.cpp

  370     unsigned Reg = Info[i].getReg();

lib/Target/RISCV/RISCVFrameLowering.cpp

  168     Register Reg = Entry.getReg();
  302     Register Reg = Entry.getReg();

lib/Target/SystemZ/SystemZFrameLowering.cpp

  149     unsigned Reg = CSI[I].getReg();
  195       unsigned Reg = CSI[I].getReg();
  208     unsigned Reg = CSI[I].getReg();
  240     unsigned Reg = CSI[I].getReg();
  273       unsigned Reg = CSI[I].getReg();
  370       unsigned Reg = Save.getReg();
  438     unsigned Reg = Save.getReg();

lib/Target/X86/X86FrameLowering.cpp

  476     unsigned Reg = I->getReg();
 2006       if (TRI->regsOverlap(CSI[i].getReg(),FPReg)) {
 2015     unsigned Reg = CSI[i - 1].getReg();
 2032     unsigned Reg = CSI[i - 1].getReg();
 2079     unsigned Reg = CSI[i - 1].getReg();
 2113     unsigned Reg = CSI[i-1].getReg();
 2193     unsigned Reg = CSI[i].getReg();
 2210     unsigned Reg = CSI[i].getReg();

lib/Target/XCore/XCoreFrameLowering.cpp

  320       unsigned DRegNum = MRI->getDwarfRegNum(CSI.getReg(), true);
  434     unsigned Reg = it->getReg();
  464     unsigned Reg = it->getReg();