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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc114672 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
115426 return cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc78814 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
gen/lib/Target/AMDGPU/R600GenDAGISel.inc12353 return L->getExtensionType() == ISD::ZEXTLOAD ||
gen/lib/Target/ARC/ARCGenDAGISel.inc 1158 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
gen/lib/Target/ARM/ARMGenDAGISel.inc54491 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
54819 return cast<MaskedLoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
gen/lib/Target/BPF/BPFGenDAGISel.inc 1995 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc72352 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
gen/lib/Target/Lanai/LanaiGenDAGISel.inc 1363 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
gen/lib/Target/MSP430/MSP430GenDAGISel.inc 4860 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
gen/lib/Target/Mips/MipsGenDAGISel.inc30080 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
gen/lib/Target/PowerPC/PPCGenDAGISel.inc44341 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
gen/lib/Target/RISCV/RISCVGenDAGISel.inc13886 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
gen/lib/Target/Sparc/SparcGenDAGISel.inc 3515 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc30068 return Type == ISD::EXTLOAD || Type == ISD::ZEXTLOAD;
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc21285 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
gen/lib/Target/X86/X86GenDAGISel.inc253618 ExtType == ISD::ZEXTLOAD;
254065 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
gen/lib/Target/XCore/XCoreGenDAGISel.inc 2351 if (cast<LoadSDNode>(N)->getExtensionType() != ISD::ZEXTLOAD) return false;
include/llvm/CodeGen/BasicTTIImpl.h 724 ((Opcode == Instruction::ZExt) ? ISD::ZEXTLOAD : ISD::SEXTLOAD);
include/llvm/CodeGen/ISDOpcodes.h 1002 static const int LAST_LOADEXT_TYPE = ZEXTLOAD + 1;
include/llvm/CodeGen/SelectionDAGNodes.h 2618 cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
include/llvm/CodeGen/TargetLowering.h 2388 LType = ISD::ZEXTLOAD;
lib/CodeGen/CodeGenPrepare.cpp 5796 !TLI->isLoadExtLegal(ISD::ZEXTLOAD, LoadResultVT, TruncVT))
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 4669 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))) {
4685 !TLI.isLoadExtLegal(ISD::ZEXTLOAD, LoadResultTy, ExtVT))
4688 if (!TLI.shouldReduceLoadWidth(LoadN, ISD::ZEXTLOAD, ExtVT))
4797 isLegalNarrowLdSt(Load, ISD::ZEXTLOAD, ExtVT)) {
4800 if (Load->getExtensionType() == ISD::ZEXTLOAD &&
5180 bool CanZextLoadProfitably = TLI.isLoadExtLegal(ISD::ZEXTLOAD,
5193 case ISD::ZEXTLOAD:
5206 NewLoad = DAG.getLoad(Load->getAddressingMode(), ISD::ZEXTLOAD,
5297 TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT))) {
5299 DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(N0), VT, LN0->getChain(),
6400 return L->getExtensionType() == ISD::ZEXTLOAD
8748 auto LoadExtOpcode = IsSigned ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
9097 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
9183 if (!TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT) ||
9202 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(Load), VT,
9504 LN00->getExtensionType() != ISD::ZEXTLOAD && LN00->isUnindexed()) {
9792 ISD::ZEXTLOAD, ISD::ZERO_EXTEND))
9796 tryToFoldExtOfMaskedLoad(DAG, TLI, VT, N, N0, ISD::ZEXTLOAD,
9816 if (TLI.isLoadExtLegal(ISD::ZEXTLOAD, VT, MemVT) &&
9833 SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, SDLoc(LN00), VT,
9871 DAG, *this, TLI, VT, LegalOperations, N, N0, ISD::ZEXTLOAD))
10188 ExtType = ISD::ZEXTLOAD;
10221 ExtType = ISD::ZEXTLOAD;
13924 case ISD::ZEXTLOAD:
15881 TLI.isLoadExtLegal(ISD::ZEXTLOAD, LegalizedStoredValTy,
16726 ISD::LoadExtType ExtType = TLI.isLoadExtLegal(ISD::ZEXTLOAD, ResultVT,
16728 ? ISD::ZEXTLOAD
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 749 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
749 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD;
762 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType())
790 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
830 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), Chain, Ptr,
911 SDValue Result = DAG.getExtLoad(ISD::ZEXTLOAD, dl, ILoadVT, Chain,
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 2680 } else if (ExtType == ISD::ZEXTLOAD) {
2727 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr,
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 728 case ISD::ZEXTLOAD:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 336 case ISD::ZEXTLOAD:
3897 case ISD::ZEXTLOAD: // e.g. i16->i32 = '16' bits known.
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 651 case ISD::ZEXTLOAD: OS << ", zext"; break;
683 case ISD::ZEXTLOAD: OS << ", zext"; break;
lib/CodeGen/SelectionDAG/TargetLowering.cpp 3170 if (LN0->getExtensionType() == ISD::ZEXTLOAD) {
6576 HiExtType = ISD::ZEXTLOAD;
6581 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(),
6596 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr,
lib/Target/AArch64/AArch64ISelLowering.cpp 775 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
2070 cast<LoadSDNode>(LHS)->getExtensionType() == ISD::ZEXTLOAD &&
3290 ExtType = ISD::ZEXTLOAD;
11169 ExtType = ISD::ZEXTLOAD;
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 111 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, VT, Expand);
123 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
124 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Legal);
125 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Legal);
126 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
137 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i8, Expand);
140 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i8, Expand);
143 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i16, Expand);
146 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v3i16, Expand);
149 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v4i16, Expand);
lib/Target/AMDGPU/R600ISelLowering.cpp 79 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
80 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i8, Custom);
81 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Custom);
91 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, MVT::v2i1, Expand);
95 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i32, MVT::v4i1, Expand);
1467 (LoadNode->getExtensionType() == ISD::ZEXTLOAD))) {
lib/Target/AMDGPU/SIISelLowering.cpp 1538 ExtType = ISD::ZEXTLOAD;
7239 case ISD::ZEXTLOAD:
7297 } else if (Ld->getExtensionType() == ISD::ZEXTLOAD ||
lib/Target/ARM/ARMISelLowering.cpp 240 setLoadExtAction(ISD::ZEXTLOAD, From, To, Action);
915 setLoadExtAction(ISD::ZEXTLOAD, VT, Ty, Legal);
13865 N->getOpcode() == ISD::SIGN_EXTEND ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
lib/Target/AVR/AVRISelLowering.cpp 59 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
lib/Target/BPF/BPFISelLowering.cpp 125 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 77 bool IsZeroExt = (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD);
133 if (ExtType == ISD::ZEXTLOAD || ExtType == ISD::EXTLOAD) {
285 IntExt = ISD::ZEXTLOAD;
lib/Target/Hexagon/HexagonISelLowering.cpp 1391 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i32, Expand);
1451 setLoadExtAction(ISD::ZEXTLOAD, TargetVT, VT, Expand);
1470 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i16, MVT::v2i8, Legal);
1473 setLoadExtAction(ISD::ZEXTLOAD, MVT::v4i16, MVT::v4i8, Legal);
lib/Target/Lanai/LanaiISelLowering.cpp 137 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
lib/Target/MSP430/MSP430ISelLowering.cpp 63 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
lib/Target/Mips/MipsISelLowering.cpp 317 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
493 setLoadExtAction(ISD::ZEXTLOAD, MVT::i64, MVT::i32, Custom);
2599 assert((VT == MVT::i64) && (ExtType == ISD::ZEXTLOAD));
4277 ISD::ZEXTLOAD, DL, RegTy, Chain, LoadPtr, MachinePointerInfo(),
lib/Target/Mips/MipsSEISelLowering.cpp 78 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand);
lib/Target/NVPTX/NVPTXISelLowering.cpp 470 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
lib/Target/PowerPC/PPCISelLowering.cpp 223 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
665 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
3041 SDValue GprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
3063 SDValue FprIndex = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, InChain,
7828 canReuseLoadAddress(SINT, MVT::i32, RLI, DAG, ISD::ZEXTLOAD)) {
14881 LD->getExtensionType() == ISD::ZEXTLOAD))
lib/Target/RISCV/RISCVISelLowering.cpp 80 for (auto N : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD})
313 LD->getExtensionType() == ISD::ZEXTLOAD))
lib/Target/Sparc/SparcISelLowering.cpp 1443 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::v2i32, Expand);
1447 setLoadExtAction(ISD::ZEXTLOAD, MVT::v2i32, VT, Expand);
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 994 Load->getExtensionType() == ISD::ZEXTLOAD) &&
lib/Target/SystemZ/SystemZISelLowering.cpp 279 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
313 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
2021 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
2032 ISD::ZEXTLOAD);
2063 case ISD::ZEXTLOAD:
2217 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 235 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
243 for (auto Ext : {ISD::EXTLOAD, ISD::ZEXTLOAD, ISD::SEXTLOAD})
250 for (auto Ext : {ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD}) {
lib/Target/X86/X86ISelLowering.cpp 788 setLoadExtAction(ISD::ZEXTLOAD, InnerVT, VT, Expand);
1063 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1238 for (auto LoadExtOp : { ISD::SEXTLOAD, ISD::ZEXTLOAD }) {
1363 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
1695 for (auto ExtType : {ISD::ZEXTLOAD, ISD::SEXTLOAD}) {
18197 IDX = DAG.getExtLoad(ISD::ZEXTLOAD, dl, PtrVT, Chain, IDX,
44851 ISD::LoadExtType Ext = N->getOpcode() == ISD::SIGN_EXTEND_VECTOR_INREG ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
lib/Target/XCore/XCoreISelLowering.cpp 124 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
128 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i16, Expand);
446 DAG.getExtLoad(ISD::ZEXTLOAD, DL, MVT::i32, Chain, BasePtr,