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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/Mips/MipsGenDAGISel.inc16374 /* 30358*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::UREM),// ->30394
26597 /* 50358*/ /*SwitchOpcode*/ 90, TARGET_VAL(ISD::UREM),// ->50451
gen/lib/Target/Mips/MipsGenFastISel.inc 3431 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc58175 /*123624*/ /*SwitchOpcode*/ 81, TARGET_VAL(ISD::UREM),// ->123708
gen/lib/Target/PowerPC/PPCGenDAGISel.inc28466 /* 68431*/ /*SwitchOpcode*/ 28, TARGET_VAL(ISD::UREM),// ->68462
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3258 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc12251 /* 22801*/ /*SwitchOpcode*/ 42, TARGET_VAL(ISD::UREM),// ->22846
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc16828 /* 32625*/ /*SwitchOpcode*/ 24, TARGET_VAL(ISD::UREM),// ->32652
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1924 case ISD::UREM: return fastEmit_ISD_UREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/XCore/XCoreGenDAGISel.inc 2136 /* 3729*/ /*SwitchOpcode*/ 10, TARGET_VAL(ISD::UREM),// ->3742
include/llvm/CodeGen/TargetLowering.h 2307 case ISD::UREM:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1517 case ISD::UREM: return visitREM(N);
3532 OtherOpcode = isSigned ? ISD::SREM : ISD::UREM;
3570 else if (UserOpc == ISD::SREM || UserOpc == ISD::UREM)
3802 if (SDNode *RemNode = DAG.getNodeIfExists(ISD::UREM, N->getVTList(),
3899 return DAG.getNode(ISD::UREM, DL, VT, N0, N1);
19603 Opcode != ISD::UREM && Opcode != ISD::SREM &&
lib/CodeGen/SelectionDAG/FastISel.cpp 641 if (ISDOpcode == ISD::UREM && isa<BinaryOperator>(I) &&
1819 return selectBinaryOp(I, ISD::UREM);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3196 case ISD::UREM:
4057 case ISD::UREM:
4226 case ISD::UREM:
4246 case ISD::UREM:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 137 case ISD::UREM: Res = PromoteIntRes_ZExtIntBinOp(N); break;
1712 case ISD::UREM: ExpandIntRes_UREM(N, Lo, Hi); break;
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 367 case ISD::UREM:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 139 case ISD::UREM:
951 case ISD::UREM:
2764 case ISD::UREM:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3113 case ISD::UREM: {
4720 case ISD::UREM:
4774 case ISD::UREM: {
5101 case ISD::UREM:
5380 case ISD::UREM:
5402 case ISD::UREM:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 6233 SDValue ShAmt = DAG.getNode(ISD::UREM, sdl, VT, Z, BitWidthC);
6263 SDValue NShAmt = DAG.getNode(ISD::UREM, sdl, VT, NegZ, BitWidthC);
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h 680 void visitURem(const User &I) { visitBinary(I, ISD::UREM); }
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 231 case ISD::UREM: return "urem";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 3471 if (N0.getOpcode() == ISD::UREM && N1C->isNullValue() &&
3860 if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) &&
3867 if (N0.getOpcode() == ISD::UREM) {
5814 ShAmt = DAG.getNode(ISD::UREM, DL, ShVT, Z, BitWidthC);
lib/CodeGen/TargetLoweringBase.cpp 814 case ISD::UREM:
1601 case URem: return ISD::UREM;
lib/Target/AArch64/AArch64FastISel.cpp 4649 case ISD::UREM:
5165 if (!selectBinaryOp(I, ISD::UREM))
5166 return selectRem(I, ISD::UREM);
lib/Target/AArch64/AArch64ISelLowering.cpp 332 setOperationAction(ISD::UREM, MVT::i32, Expand);
333 setOperationAction(ISD::UREM, MVT::i64, Expand);
865 setOperationAction(ISD::UREM, VT, Expand);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 311 setOperationAction(ISD::UREM, VT, Expand);
381 setOperationAction(ISD::UREM, VT, Expand);
1802 SDValue REM_Part = DAG.getNode(ISD::UREM, DL, HalfVT, LHS_Hi, RHS_Lo);
lib/Target/AMDGPU/SIISelLowering.cpp 450 setOperationAction(ISD::UREM, MVT::i16, Promote);
lib/Target/ARM/ARMISelLowering.cpp 205 setOperationAction(ISD::UREM, VT, Expand);
276 setOperationAction(ISD::UREM, VT, Expand);
1110 setOperationAction(ISD::UREM, MVT::i32, Expand);
1117 setOperationAction(ISD::UREM, MVT::i64, Custom);
9183 case ISD::UREM: return LowerREM(Op.getNode(), DAG);
9294 case ISD::UREM:
15919 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&
15937 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&
lib/Target/ARM/ARMTargetTransformInfo.cpp 661 { ISD::UREM, MVT::v1i64, 1 * FunctionCallDivCost},
665 { ISD::UREM, MVT::v2i32, 2 * FunctionCallDivCost},
669 { ISD::UREM, MVT::v4i16, 4 * FunctionCallDivCost},
673 { ISD::UREM, MVT::v8i8, 8 * FunctionCallDivCost},
678 { ISD::UREM, MVT::v2i64, 2 * FunctionCallDivCost},
682 { ISD::UREM, MVT::v4i32, 4 * FunctionCallDivCost},
686 { ISD::UREM, MVT::v8i16, 8 * FunctionCallDivCost},
690 { ISD::UREM, MVT::v16i8, 16 * FunctionCallDivCost},
918 case ISD::UREM:
lib/Target/AVR/AVRISelLowering.cpp 146 setOperationAction(ISD::UREM, MVT::i8, Expand);
147 setOperationAction(ISD::UREM, MVT::i16, Expand);
lib/Target/BPF/BPFISelLowering.cpp 89 setOperationAction(ISD::UREM, VT, Expand);
lib/Target/Hexagon/HexagonISelLowering.cpp 1374 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
1421 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO,
lib/Target/Lanai/LanaiISelLowering.cpp 111 setOperationAction(ISD::UREM, MVT::i32, Expand);
lib/Target/Lanai/LanaiTargetTransformInfo.h 94 case ISD::UREM:
lib/Target/MSP430/MSP430ISelLowering.cpp 130 setOperationAction(ISD::UREM, MVT::i8, Promote);
136 setOperationAction(ISD::UREM, MVT::i16, LibCall);
lib/Target/Mips/MipsFastISel.cpp 1936 case ISD::UREM:
1953 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
2058 if (!selectBinaryOp(I, ISD::UREM))
2059 return selectDivRem(I, ISD::UREM);
lib/Target/Mips/MipsISelLowering.cpp 396 setOperationAction(ISD::UREM, MVT::i32, Expand);
400 setOperationAction(ISD::UREM, MVT::i64, Expand);
lib/Target/Mips/MipsSEISelLowering.cpp 242 setOperationAction(ISD::UREM, MVT::i32, Legal);
289 setOperationAction(ISD::UREM, MVT::i64, Legal);
347 setOperationAction(ISD::UREM, Ty, Legal);
2063 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
lib/Target/NVPTX/NVPTXISelLowering.cpp 523 setTargetDAGCombine(ISD::UREM);
4542 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM);
4769 case ISD::UREM:
lib/Target/PowerPC/PPCISelLowering.cpp 251 setOperationAction(ISD::UREM, MVT::i32, Custom);
253 setOperationAction(ISD::UREM, MVT::i64, Custom);
256 setOperationAction(ISD::UREM, MVT::i32, Expand);
258 setOperationAction(ISD::UREM, MVT::i64, Expand);
628 setOperationAction(ISD::UREM, VT, Expand);
9545 (Op.getOpcode() == ISD::UREM && UI->getOpcode() == ISD::UDIV))
10177 case ISD::UREM:
lib/Target/RISCV/RISCVISelLowering.cpp 117 setOperationAction(ISD::UREM, XLenVT, Expand);
124 setOperationAction(ISD::UREM, MVT::i32, Custom);
828 case ISD::UREM:
900 case ISD::UREM:
lib/Target/Sparc/SparcISelLowering.cpp 1495 setOperationAction(ISD::UREM, MVT::i32, Expand);
1502 setOperationAction(ISD::UREM, MVT::i64, Expand);
lib/Target/SystemZ/SystemZISelLowering.cpp 162 setOperationAction(ISD::UREM, VT, Expand);
620 setTargetDAGCombine(ISD::UREM);
6177 case ISD::UREM: return combineIntDIVREM(N, DCI);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 176 ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR}) {
lib/Target/X86/X86ISelLowering.cpp 315 setOperationAction(ISD::UREM, VT, Expand);
750 setOperationAction(ISD::UREM, VT, Expand);
851 setOperationAction(ISD::UREM, VT, Custom);
1819 setOperationAction(ISD::UREM, MVT::i128, Custom);
25396 case ISD::UREM: isSigned = false; LC = RTLIB::UREM_I128; break;
27940 case ISD::UREM: {
lib/Target/X86/X86TargetTransformInfo.cpp 248 ISD == ISD::UREM) &&
283 if (ISD == ISD::UREM)
352 { ISD::UREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
356 { ISD::UREM, MVT::v32i16, 8 }, // vpmulhuw+mul+sub sequence
371 { ISD::UREM, MVT::v16i32, 17 }, // vpmuludq+mul+sub sequence
386 { ISD::UREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
390 { ISD::UREM, MVT::v16i16, 8 }, // vpmulhuw+mul+sub sequence
394 { ISD::UREM, MVT::v8i32, 19 }, // vpmuludq+mul+sub sequence
410 { ISD::UREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split.
412 { ISD::UREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
418 { ISD::UREM, MVT::v16i16, 16+2 }, // 2*pmulhuw+mul+sub sequence + split.
420 { ISD::UREM, MVT::v8i16, 8 }, // pmulhuw+mul+sub sequence
426 { ISD::UREM, MVT::v8i32, 40+2 }, // 2*pmuludq+mul+sub sequence + split.
428 { ISD::UREM, MVT::v4i32, 20 }, // pmuludq+mul+sub sequence
877 ISD == ISD::UDIV || ISD == ISD::UREM)) {