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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc 2142 /* 3959*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
72963 /*173907*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
73623 /*175152*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
85101 /*196963*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
86226 /*199161*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
102000 /*228414*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
102036 /*228486*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
102715 /*229770*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
102762 /*229873*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
109286 /*244052*/ /*SwitchOpcode*/ 83, TARGET_VAL(ISD::UNDEF),// ->244138
109411 /*244403*/ /*SwitchOpcode*/ 43, TARGET_VAL(ISD::UNDEF),// ->244449
110808 /*247505*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc77154 /*171541*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
77164 /*171558*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
77282 /*171834*/ /*SwitchOpcode*/ 12, TARGET_VAL(ISD::UNDEF),// ->171849
77294 /*171853*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
gen/lib/Target/ARM/ARMGenDAGISel.inc49277 /*109670*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
gen/lib/Target/PowerPC/PPCGenDAGISel.inc43295 /*108335*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
43335 /*108415*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc26327 /* 50037*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
26645 /* 50650*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc 4145 /* 7529*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
4161 /* 7560*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
15080 /* 29554*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
15115 /* 29613*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
16276 /* 31629*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
16303 /* 31678*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
16329 /* 31725*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
16355 /* 31772*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
16382 /* 31821*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
16409 /* 31870*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
20853 /* 39864*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
20893 /* 39945*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
20920 /* 39996*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
20947 /* 40047*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
gen/lib/Target/X86/X86GenDAGISel.inc 7467 /* 16018*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
194881 /*394179*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
195758 /*396125*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
205532 /*415973*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
205580 /*416075*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
205628 /*416177*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
205676 /*416279*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
205772 /*416499*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
205995 /*417022*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
206223 /*417553*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
206388 /*417929*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
206484 /*418138*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
206577 /*418345*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
206782 /*418834*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
206810 /*418892*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
206838 /*418950*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
206866 /*419008*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
206917 /*419118*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
207053 /*419423*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
207247 /*419870*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
207412 /*420246*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
229140 /*467633*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
229222 /*467816*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
229293 /*467982*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
229348 /*468102*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
229410 /*468250*/ OPC_CheckOpcode, TARGET_VAL(ISD::UNDEF),
include/llvm/CodeGen/SelectionDAG.h 769 if (Op.getOpcode() == ISD::UNDEF) {
775 return getNode(ISD::UNDEF, SDLoc(), VT);
785 if (Op.getOpcode() == ISD::UNDEF) {
791 return getNode(ISD::UNDEF, SDLoc(), VT);
893 return getNode(ISD::UNDEF, SDLoc(), VT);
include/llvm/CodeGen/SelectionDAGNodes.h 670 bool isUndef() const { return NodeType == ISD::UNDEF; }
lib/CodeGen/SelectionDAG/DAGCombiner.cpp17718 SDValue ScalarUndef = DAG.getNode(ISD::UNDEF, DL, SVT);
17727 else if (ISD::UNDEF == Op.getOpcode())
17748 ScalarUndef = DAG.getNode(ISD::UNDEF, DL, SVT);
17916 return ISD::UNDEF == Op.getOpcode() || ISD::BUILD_VECTOR == Op.getOpcode();
17940 if (ISD::UNDEF == Op.getOpcode())
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 2804 case ISD::UNDEF: {
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 104 case ISD::UNDEF: R = SoftenFloatRes_UNDEF(N); break;
1128 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
2097 case ISD::UNDEF: R = PromoteFloatRes_UNDEF(N); break;
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 90 case ISD::UNDEF: Res = PromoteIntRes_UNDEF(N); break;
1678 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 64 case ISD::UNDEF: R = ScalarizeVecRes_UNDEF(N); break;
848 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break;
2721 case ISD::UNDEF: Res = WidenVecRes_UNDEF(N); break;
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 4511 else if (OpOpcode == ISD::UNDEF)
4530 else if (OpOpcode == ISD::UNDEF)
4552 else if (OpOpcode == ISD::UNDEF)
4589 if (OpOpcode == ISD::UNDEF)
4605 if (OpOpcode == ISD::UNDEF)
4613 if (OpOpcode == ISD::UNDEF)
4619 if (OpOpcode == ISD::UNDEF)
4629 if (OpOpcode == ISD::UNDEF)
4639 if (OpOpcode == ISD::UNDEF)
4650 if (OpOpcode == ISD::UNDEF)
9511 if (Opc != ISD::UNDEF && Opc != ISD::Constant && Opc != ISD::ConstantFP)
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 172 case ISD::UNDEF: return "undef";
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp 2796 case ISD::UNDEF:
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 145 case ISD::UNDEF:
lib/Target/AMDGPU/SIISelLowering.cpp 536 setOperationAction(ISD::UNDEF, MVT::v2i16, Legal);
537 setOperationAction(ISD::UNDEF, MVT::v2f16, Legal);
8828 case ISD::UNDEF:
lib/Target/ARC/ARCISelLowering.cpp 107 setOperationAction(ISD::UNDEF, MVT::i32, Legal);
lib/Target/ARM/ARMISelLowering.cpp 234 setOperationAction(ISD::UNDEF, VT, Legal);
1966 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
4041 ArgValue = DAG.getNode(ISD::UNDEF, dl, MVT::v2f64);
8127 SDValue ConVec = DAG.getNode(ISD::UNDEF, dl, ConcatVT);
8197 SDValue SubVec = DAG.getNode(ISD::UNDEF, dl, SubVT);
lib/Target/Hexagon/HexagonISelLowering.h 360 return Op.getOpcode() == ISD::UNDEF;
lib/Target/Mips/MipsSEISelLowering.cpp 330 setOperationAction(ISD::UNDEF, Ty, Legal);
lib/Target/NVPTX/NVPTXISelLowering.cpp 2525 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2536 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2543 InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
lib/Target/Sparc/SparcISelLowering.cpp 990 SDValue Vec = DAG.getNode(ISD::UNDEF, dl, MVT::v2i32);
lib/Target/SystemZ/SystemZISelLowering.cpp 326 setOperationAction(ISD::UNDEF, VT, Legal);
lib/Target/X86/X86ISelLowering.cpp 567 setOperationAction(ISD::UNDEF, MVT::f64, Expand);
592 setOperationAction(ISD::UNDEF, VT, Expand);
630 setOperationAction(ISD::UNDEF, MVT::f80, Expand);
8428 if (Opc == ISD::UNDEF)
8775 if (Opcode == ISD::UNDEF)