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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc113184 /*252029*/ /*SwitchOpcode*/ 76, TARGET_VAL(ISD::UMAX),// ->252108
gen/lib/Target/AArch64/AArch64GenFastISel.inc 7744 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc28048 /* 58830*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
28107 /* 58939*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
56195 /*122952*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
56202 /*122964*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
56345 /*123229*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
56396 /*123322*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
56440 /*123404*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
56599 /*123764*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
56667 /*123926*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
56778 /*124197*/ /*SwitchOpcode*/ 97|128,9/*1249*/, TARGET_VAL(ISD::UMAX),// ->125450
56791 /*124223*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
56834 /*124312*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
56862 /*124363*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
56893 /*124417*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
56922 /*124469*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
56974 /*124563*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
57029 /*124663*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
57051 /*124713*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
57091 /*124808*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
57134 /*124906*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
57176 /*125004*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
57245 /*125167*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
59965 /*131169*/ /*SwitchOpcode*/ 61, TARGET_VAL(ISD::UMAX),// ->131233
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 7762 /* 29617*/ /*SwitchOpcode*/ 104, TARGET_VAL(ISD::UMAX),// ->29724
gen/lib/Target/ARM/ARMGenDAGISel.inc52529 /*117185*/ /*SwitchOpcode*/ 83|128,1/*211*/, TARGET_VAL(ISD::UMAX),// ->117400
gen/lib/Target/ARM/ARMGenFastISel.inc 5186 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/Mips/MipsGenDAGISel.inc28448 /* 53785*/ /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::UMAX),// ->53949
gen/lib/Target/Mips/MipsGenFastISel.inc 3429 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc58265 /*123792*/ /*SwitchOpcode*/ 81, TARGET_VAL(ISD::UMAX),// ->123876
gen/lib/Target/PowerPC/PPCGenDAGISel.inc42760 /*107223*/ /*SwitchOpcode*/ 74, TARGET_VAL(ISD::UMAX),// ->107300
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3256 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc78692 /*165405*/ /*SwitchOpcode*/ 117|128,1/*245*/, TARGET_VAL(ISD::UMAX),// ->165654
83758 /*175479*/ /*SwitchOpcode*/ 117|128,1/*245*/, TARGET_VAL(ISD::UMAX),// ->175728
88581 /*184986*/ /*SwitchOpcode*/ 14|128,2/*270*/, TARGET_VAL(ISD::UMAX),// ->185260
94859 /*197520*/ /*SwitchOpcode*/ 10|128,2/*266*/, TARGET_VAL(ISD::UMAX),// ->197790
101544 /*210842*/ /*SwitchOpcode*/ 56|128,2/*312*/, TARGET_VAL(ISD::UMAX),// ->211158
108890 /*225670*/ /*SwitchOpcode*/ 54|128,2/*310*/, TARGET_VAL(ISD::UMAX),// ->225984
115355 /*238722*/ /*SwitchOpcode*/ 52|128,2/*308*/, TARGET_VAL(ISD::UMAX),// ->239034
119017 /*245767*/ /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::UMAX),// ->245931
121639 /*250961*/ /*SwitchOpcode*/ 126|128,1/*254*/, TARGET_VAL(ISD::UMAX),// ->251219
124428 /*256246*/ /*SwitchOpcode*/ 47, TARGET_VAL(ISD::UMAX),// ->256296
126853 /*260829*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::UMAX),// ->260880
145627 /*297955*/ OPC_CheckOpcode, TARGET_VAL(ISD::UMAX),
147546 /*301532*/ /*SwitchOpcode*/ 48, TARGET_VAL(ISD::UMAX),// ->301583
159526 /*324211*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::UMAX),// ->324248
161258 /*327453*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::UMAX),// ->327490
177353 /*359599*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::UMAX),// ->359621
178302 /*361298*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::UMAX),// ->361319
187300 /*378544*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::UMAX),// ->378581
188069 /*380001*/ /*SwitchOpcode*/ 34, TARGET_VAL(ISD::UMAX),// ->380038
188717 /*381241*/ /*SwitchOpcode*/ 19, TARGET_VAL(ISD::UMAX),// ->381263
189033 /*381819*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::UMAX),// ->381840
216226 /*439287*/ /*SwitchOpcode*/ 37|128,14/*1829*/, TARGET_VAL(ISD::UMAX),// ->441120
gen/lib/Target/X86/X86GenFastISel.inc13532 case ISD::UMAX: return fastEmit_ISD_UMAX_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
include/llvm/CodeGen/TargetLowering.h 2265 case ISD::UMAX:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1527 case ISD::UMAX: return visitIMINMAX(N);
2226 if (N0.getOpcode() == ISD::UMAX && hasOperation(ISD::USUBSAT, VT)) {
4235 case ISD::SMAX: AltOpcode = ISD::UMAX; break;
4237 case ISD::UMAX: AltOpcode = ISD::SMAX; break;
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3091 case ISD::UMAX: {
3098 case ISD::UMAX: Pred = ISD::SETUGT; break;
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 82 case ISD::UMAX: Res = PromoteIntRes_ZExtIntBinOp(N); break;
702 DAG.getNode(ISD::UMAX, dl, PromotedType, Op1Promoted, Op2Promoted);
1758 case ISD::UMAX:
2082 return std::make_pair(ISD::SETGT, ISD::UMAX);
2083 case ISD::UMAX:
2084 return std::make_pair(ISD::SETUGT, ISD::UMAX);
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 438 case ISD::UMAX:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 123 case ISD::UMAX:
957 case ISD::UMAX:
2131 case ISD::VECREDUCE_UMAX: CombineOpc = ISD::UMAX; break;
2747 case ISD::UMAX:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3256 case ISD::UMAX: {
3630 case ISD::UMAX:
4711 case ISD::UMAX: return std::make_pair(C1.uge(C2) ? C1 : C2, true);
5110 case ISD::UMAX:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 3288 case SPF_UMAX: Opc = ISD::UMAX; break;
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 267 case ISD::UMAX: return "umax";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 6893 if (Opcode == ISD::USUBSAT && isOperationLegalOrCustom(ISD::UMAX, VT)) {
6894 SDValue Max = DAG.getNode(ISD::UMAX, dl, VT, LHS, RHS);
7330 case ISD::VECREDUCE_UMAX: BaseOpcode = ISD::UMAX; break;
lib/CodeGen/TargetLoweringBase.cpp 645 setOperationAction(ISD::UMAX, VT, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 877 for (unsigned Opcode : {ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
2846 return DAG.getNode(ISD::UMAX, dl, Op.getValueType(),
12086 ReplaceReductionResults(N, Results, DAG, ISD::UMAX, AArch64ISD::UMAXV);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 349 setOperationAction(ISD::UMAX, MVT::i32, Legal);
lib/Target/AMDGPU/SIISelLowering.cpp 439 setOperationAction(ISD::UMAX, MVT::i16, Legal);
607 setOperationAction(ISD::UMAX, MVT::v2i16, Legal);
634 setOperationAction(ISD::UMAX, MVT::v4i16, Custom);
714 setTargetDAGCombine(ISD::UMAX);
4076 case ISD::UMAX:
8997 case ISD::UMAX:
9163 if (Opc == ISD::UMIN && Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) {
9288 case ISD::UMAX:
9959 case ISD::UMAX:
lib/Target/ARM/ARMISelLowering.cpp 210 for (auto Opcode : {ISD::ABS, ISD::SMIN, ISD::SMAX, ISD::UMIN, ISD::UMAX})
259 setOperationAction(ISD::UMAX, VT, Legal);
3723 ? ISD::UMIN : ISD::UMAX;
lib/Target/Mips/MipsSEISelLowering.cpp 348 setOperationAction(ISD::UMAX, Ty, Legal);
2015 return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
2027 return DAG.getNode(ISD::UMAX, DL, Op->getValueType(0),
lib/Target/NVPTX/NVPTXISelLowering.cpp 499 setOperationAction(ISD::UMAX, Ty, Legal);
lib/Target/PowerPC/PPCISelLowering.cpp 571 setOperationAction(ISD::UMAX, VT, Legal);
577 setOperationAction(ISD::UMAX, VT, Expand);
672 setOperationAction(ISD::UMAX, MVT::v2i64, Expand);
lib/Target/X86/X86ISelLowering.cpp 875 setOperationAction(ISD::UMAX, VT, VT == MVT::v16i8 ? Legal : Custom);
1041 setOperationAction(ISD::UMAX, MVT::v8i16, Legal);
1042 setOperationAction(ISD::UMAX, MVT::v4i32, Legal);
1206 setOperationAction(ISD::UMAX, MVT::v4i64, Custom);
1222 setOperationAction(ISD::UMAX, VT, HasInt256 ? Legal : Custom);
1451 setOperationAction(ISD::UMAX, VT, Legal);
1545 setOperationAction(ISD::UMAX, VT, Legal);
1679 setOperationAction(ISD::UMAX, VT, Legal);
20827 case ISD::SETUGE: Opc = ISD::UMAX; break;
24929 if (Opcode == ISD::USUBSAT && !TLI.isOperationLegal(ISD::UMAX, VT)) {
24994 assert((Opcode == ISD::UMIN || Opcode == ISD::UMAX) &&
25010 case ISD::UMAX: CC = ISD::CondCode::SETUGT; break;
27772 case ISD::UMAX:
35758 Extract, BinOp, {ISD::SMAX, ISD::SMIN, ISD::UMAX, ISD::UMIN}, true);
35792 else if (BinOp == ISD::UMAX)
44139 if (Op0.getOpcode() == ISD::UMAX) {