reference, declarationdefinition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/ARM/ARMGenDAGISel.inc
53321 /*119184*/  /*SwitchOpcode*/ 85, TARGET_VAL(ISD::UADDSAT),// ->119272
gen/lib/Target/ARM/ARMGenFastISel.inc
 5184   case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc
21050 /* 40238*/  /*SwitchOpcode*/ 28, TARGET_VAL(ISD::UADDSAT),// ->40269
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc
 1922   case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/X86/X86GenDAGISel.inc
77945 /*163988*/          /*SwitchOpcode*/ 0|128,1/*128*/, TARGET_VAL(ISD::UADDSAT),// ->164120
83067 /*174079*/          /*SwitchOpcode*/ 0|128,1/*128*/, TARGET_VAL(ISD::UADDSAT),// ->174211
100628 /*209132*/          /*SwitchOpcode*/ 82, TARGET_VAL(ISD::UADDSAT),// ->209217
108050 /*223990*/          /*SwitchOpcode*/ 80, TARGET_VAL(ISD::UADDSAT),// ->224073
118640 /*245064*/        /*SwitchOpcode*/ 32|128,1/*160*/, TARGET_VAL(ISD::UADDSAT),// ->245228
120603 /*248930*/        /*SwitchOpcode*/ 126|128,1/*254*/, TARGET_VAL(ISD::UADDSAT),// ->249188
124218 /*255878*/          /*SwitchOpcode*/ 19, TARGET_VAL(ISD::UADDSAT),// ->255900
126671 /*260471*/          /*SwitchOpcode*/ 18, TARGET_VAL(ISD::UADDSAT),// ->260492
145371 /*297514*/            OPC_CheckOpcode, TARGET_VAL(ISD::UADDSAT),
147333 /*301113*/          /*SwitchOpcode*/ 34, TARGET_VAL(ISD::UADDSAT),// ->301150
187083 /*378166*/          /*SwitchOpcode*/ 34, TARGET_VAL(ISD::UADDSAT),// ->378203
187880 /*379633*/          /*SwitchOpcode*/ 34, TARGET_VAL(ISD::UADDSAT),// ->379670
188623 /*381081*/          /*SwitchOpcode*/ 19, TARGET_VAL(ISD::UADDSAT),// ->381103
188953 /*381666*/          /*SwitchOpcode*/ 18, TARGET_VAL(ISD::UADDSAT),// ->381687
213518 /*433249*/  /*SwitchOpcode*/ 78|128,5/*718*/, TARGET_VAL(ISD::UADDSAT),// ->433971
gen/lib/Target/X86/X86GenFastISel.inc
13531   case ISD::UADDSAT: return fastEmit_ISD_UADDSAT_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
include/llvm/CodeGen/TargetLowering.h
 2281     case ISD::UADDSAT:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp
 1496   case ISD::UADDSAT:            return visitADDSAT(N);
 2351   if (Opcode == ISD::UADDSAT)
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
 1119   case ISD::UADDSAT:
 3332   case ISD::UADDSAT:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
  152   case ISD::UADDSAT:
  662   if (Opcode == ISD::UADDSAT || Opcode == ISD::USUBSAT) {
  679     case ISD::UADDSAT:
  706     if (Opcode == ISD::UADDSAT) {
 1787   case ISD::UADDSAT:
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
  449   case ISD::UADDSAT:
  828   case ISD::UADDSAT:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
  126   case ISD::UADDSAT:
  959   case ISD::UADDSAT:
 2748   case ISD::UADDSAT:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
 4713   case ISD::UADDSAT: return std::make_pair(C1.uadd_sat(C2), true);
 5113   case ISD::UADDSAT:
 5412     case ISD::UADDSAT:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
 6298     setValue(&I, DAG.getNode(ISD::UADDSAT, sdl, Op1.getValueType(), Op1, Op2));
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp
  302   case ISD::UADDSAT:                    return "uaddsat";
lib/CodeGen/SelectionDAG/TargetLowering.cpp
 6898   if (Opcode == ISD::UADDSAT && isOperationLegalOrCustom(ISD::UMIN, VT)) {
 6909   case ISD::UADDSAT:
 6932   if (Opcode == ISD::UADDSAT) {
lib/CodeGen/TargetLoweringBase.cpp
  650     setOperationAction(ISD::UADDSAT, VT, Expand);
lib/Target/ARM/ARMISelLowering.cpp
  269     setOperationAction(ISD::UADDSAT, VT, Legal);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp
  127     for (auto Op : {ISD::SADDSAT, ISD::UADDSAT})
lib/Target/X86/X86ISelLowering.cpp
  879     setOperationAction(ISD::UADDSAT,            MVT::v16i8, Legal);
  883     setOperationAction(ISD::UADDSAT,            MVT::v8i16, Legal);
  887     setOperationAction(ISD::UADDSAT,            MVT::v4i32, Custom);
  889     setOperationAction(ISD::UADDSAT,            MVT::v2i64, Custom);
 1210     setOperationAction(ISD::UADDSAT,   MVT::v32i8,  HasInt256 ? Legal : Custom);
 1214     setOperationAction(ISD::UADDSAT,   MVT::v16i16, HasInt256 ? Legal : Custom);
 1336       setOperationAction(ISD::UADDSAT,          VT, Custom);
 1599       setOperationAction(ISD::UADDSAT,            VT, Custom);
 1683       setOperationAction(ISD::UADDSAT,      VT, Legal);
24906     case ISD::UADDSAT:
24923     if (Opcode == ISD::UADDSAT && !TLI.isOperationLegal(ISD::UMIN, VT)) {
27766   case ISD::UADDSAT:
37194         return DAG.getNode(ISD::UADDSAT, DL, VT, OpLHS, OpRHS);
37206           return DAG.getNode(ISD::UADDSAT, DL, VT, OpLHS, OpRHS);
lib/Target/X86/X86TargetTransformInfo.cpp
 1921     { ISD::UADDSAT,    MVT::v32i16,  1 },
 1922     { ISD::UADDSAT,    MVT::v64i8,   1 },
 1939     { ISD::UADDSAT,    MVT::v16i32,  3 }, // not + pminud + paddd
 1940     { ISD::UADDSAT,    MVT::v2i64,   3 }, // not + pminuq + paddq
 1941     { ISD::UADDSAT,    MVT::v4i64,   3 }, // not + pminuq + paddq
 1942     { ISD::UADDSAT,    MVT::v8i64,   3 }, // not + pminuq + paddq
 1982     { ISD::UADDSAT,    MVT::v16i16,  1 },
 1983     { ISD::UADDSAT,    MVT::v32i8,   1 },
 1984     { ISD::UADDSAT,    MVT::v8i32,   3 }, // not + pminud + paddd
 2019     { ISD::UADDSAT,    MVT::v16i16,  4 }, // 2 x 128-bit Op + extract/insert
 2020     { ISD::UADDSAT,    MVT::v32i8,   4 }, // 2 x 128-bit Op + extract/insert
 2021     { ISD::UADDSAT,    MVT::v8i32,   8 }, // 2 x 128-bit Op + extract/insert
 2046     { ISD::UADDSAT,    MVT::v4i32,   3 }, // not + pminud + paddd
 2095     { ISD::UADDSAT,    MVT::v8i16,   1 },
 2096     { ISD::UADDSAT,    MVT::v16i8,   1 },
 2174     ISD = ISD::UADDSAT;