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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
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References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc99887 /*224801*/ /*SwitchOpcode*/ 11, TARGET_VAL(ISD::TRAP),// ->224815
gen/lib/Target/ARM/ARMGenDAGISel.inc37679 /* 83036*/ /*SwitchOpcode*/ 30, TARGET_VAL(ISD::TRAP),// ->83069
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc68014 /*131567*/ /*SwitchOpcode*/ 7, TARGET_VAL(ISD::TRAP),// ->131577
gen/lib/Target/Mips/MipsGenDAGISel.inc24164 /* 45312*/ /*SwitchOpcode*/ 30, TARGET_VAL(ISD::TRAP),// ->45345
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc69513 /*146889*/ /*SwitchOpcode*/ 7, TARGET_VAL(ISD::TRAP),// ->146899
gen/lib/Target/PowerPC/PPCGenDAGISel.inc28094 /* 67733*/ /*SwitchOpcode*/ 7, TARGET_VAL(ISD::TRAP),// ->67743
gen/lib/Target/RISCV/RISCVGenDAGISel.inc11894 /* 22130*/ /*SwitchOpcode*/ 7, TARGET_VAL(ISD::TRAP),// ->22140
gen/lib/Target/Sparc/SparcGenDAGISel.inc 2908 /* 5370*/ /*SwitchOpcode*/ 7, TARGET_VAL(ISD::TRAP),// ->5380
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc21331 /* 40088*/ /*SwitchOpcode*/ 7, TARGET_VAL(ISD::TRAP),// ->40098
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc16611 /* 32223*/ /*SwitchOpcode*/ 7, TARGET_VAL(ISD::TRAP),// ->32233
gen/lib/Target/X86/X86GenDAGISel.inc58422 /*123287*/ /*SwitchOpcode*/ 7, TARGET_VAL(ISD::TRAP),// ->123297
gen/lib/Target/XCore/XCoreGenDAGISel.inc 2202 /* 3851*/ /*SwitchOpcode*/ 18, TARGET_VAL(ISD::TRAP),// ->3872
lib/CodeGen/SelectionDAG/FastISel.cpp 1858 return fastEmit_(MVT::Other, MVT::Other, ISD::TRAP) != 0;
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 1101 NewVal = DAG.getNode(ISD::TRAP, SDLoc(Node), Node->getVTList(),
3801 case ISD::TRAP: {
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp 2611 Chain = DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, Chain);
2958 DAG.setRoot(DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
6496 ISD::TRAP : ISD::DEBUGTRAP;
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 374 case ISD::TRAP: return "trap";
lib/CodeGen/SelectionDAG/StatepointLowering.cpp 1066 DAG.getNode(ISD::TRAP, getCurSDLoc(), MVT::Other, DAG.getRoot()));
lib/CodeGen/TargetLoweringBase.cpp 785 setOperationAction(ISD::TRAP, MVT::Other, Expand);
lib/Target/AArch64/AArch64ISelLowering.cpp 577 setOperationAction(ISD::TRAP, MVT::Other, Legal);
lib/Target/AMDGPU/SIISelLowering.cpp 357 setOperationAction(ISD::TRAP, MVT::Other, Custom);
4054 case ISD::TRAP:
lib/Target/ARM/ARMISelLowering.cpp 1182 setOperationAction(ISD::TRAP, MVT::Other, Legal);
lib/Target/Hexagon/HexagonISelLowering.cpp 1294 setOperationAction(ISD::TRAP, MVT::Other, Legal);
lib/Target/Mips/MipsISelLowering.cpp 498 setOperationAction(ISD::TRAP, MVT::Other, Legal);
lib/Target/NVPTX/NVPTXISelLowering.cpp 480 setOperationAction(ISD::TRAP, MVT::Other, Legal);
lib/Target/PowerPC/PPCISelLowering.cpp 425 setOperationAction(ISD::TRAP, MVT::Other, Legal);
lib/Target/RISCV/RISCVISelLowering.cpp 196 setOperationAction(ISD::TRAP, MVT::Other, Legal);
lib/Target/Sparc/SparcISelLowering.cpp 1687 setOperationAction(ISD::TRAP , MVT::Other, Legal);
lib/Target/SystemZ/SystemZISelLowering.cpp 247 setOperationAction(ISD::TRAP, MVT::Other, Legal);
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 262 setOperationAction(ISD::TRAP, MVT::Other, Legal);
lib/Target/X86/X86ISelLowering.cpp 496 setOperationAction(ISD::TRAP, MVT::Other, Legal);
lib/Target/XCore/XCoreISelLowering.cpp 110 setOperationAction(ISD::TRAP, MVT::Other, Legal);