reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced

References

gen/lib/Target/AVR/AVRGenDAGISel.inc

  967 /*  1640*/  /*SwitchOpcode*/ 62, TARGET_VAL(ISD::SUBC),// ->1705

gen/lib/Target/Lanai/LanaiGenDAGISel.inc

  736 /*  1290*/  /*SwitchOpcode*/ 61, TARGET_VAL(ISD::SUBC),// ->1354

gen/lib/Target/MSP430/MSP430GenDAGISel.inc

 2103 /*  4361*/      /*SwitchOpcode*/ 18|128,1/*146*/, TARGET_VAL(ISD::SUBC),// ->4511
 4300 /*  8630*/  /*SwitchOpcode*/ 113, TARGET_VAL(ISD::SUBC),// ->8746

gen/lib/Target/Mips/MipsGenDAGISel.inc

24629 /* 46120*/  /*SwitchOpcode*/ 53, TARGET_VAL(ISD::SUBC),// ->46176

gen/lib/Target/Mips/MipsGenFastISel.inc

 3427   case ISD::SUBC: return fastEmit_ISD_SUBC_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);

gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc

57888 /*123094*/  /*SwitchOpcode*/ 33, TARGET_VAL(ISD::SUBC),// ->123130

gen/lib/Target/PowerPC/PPCGenDAGISel.inc

25077 /* 60410*/  /*SwitchOpcode*/ 72, TARGET_VAL(ISD::SUBC),// ->60485

gen/lib/Target/Sparc/SparcGenDAGISel.inc

 2315 /*  4258*/  /*SwitchOpcode*/ 35, TARGET_VAL(ISD::SUBC),// ->4296

lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 1502   case ISD::SUBC:               return visitSUBC(N);
 3273     return DAG.getNode(ISD::SUBC, SDLoc(N), N->getVTList(), N0, N1);

lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

 1767   case ISD::SUBC: ExpandIntRes_ADDSUBC(N, Lo, Hi); break;
 2161                                    ISD::ADDC : ISD::SUBC,
 2171       Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);
 2268     Lo = DAG.getNode(ISD::SUBC, dl, VTList, LoOps);

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 3045   case ISD::SUBC: {

lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp

  294   case ISD::SUBC:                       return "subc";

lib/CodeGen/TargetLoweringBase.cpp

  674     setOperationAction(ISD::SUBC, VT, Expand);

lib/Target/AArch64/AArch64ISelLowering.cpp

  300   setOperationAction(ISD::SUBC, MVT::i32, Custom);
  304   setOperationAction(ISD::SUBC, MVT::i64, Custom);
 2329   case ISD::SUBC:
 2998   case ISD::SUBC:

lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp

  741   case ISD::SUBC:
  987       ConsumeCarry || Opcode == ISD::ADDC || Opcode == ISD::SUBC;

lib/Target/AMDGPU/AMDGPUISelLowering.cpp

  327     setOperationAction(ISD::SUBC, VT, Legal);

lib/Target/AMDGPU/R600ISelLowering.cpp

  259     setOperationAction(ISD::SUBC, VT, Expand);

lib/Target/AVR/AVRISelLowering.cpp

   69     setOperationAction(ISD::SUBC, VT, Legal);

lib/Target/PowerPC/PPCISelLowering.cpp

  194     setOperationAction(ISD::SUBC, VT, Legal);
15253     SDValue Subc = DAG.getNode(ISD::SUBC, DL, DAG.getVTList(MVT::i64, MVT::Glue),

lib/Target/Sparc/SparcISelLowering.cpp

 1550   setOperationAction(ISD::SUBC, MVT::i32, Custom);
 1556     setOperationAction(ISD::SUBC, MVT::i64, Custom);
 2906   case ISD::SUBC: hiOpc = ISD::SUBE; break;
 3054   case ISD::SUBC:

lib/Target/WebAssembly/WebAssemblyISelLowering.cpp

  114         ISD::SRL_PARTS, ISD::ADDC, ISD::ADDE, ISD::SUBC, ISD::SUBE}) {