|
|
reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
unreferenced
|
References
gen/lib/Target/AArch64/AArch64GenDAGISel.inc69676 /*167300*/ /*SwitchOpcode*/ 43|128,51/*6571*/, TARGET_VAL(ISD::STORE),// ->173875
gen/lib/Target/AMDGPU/AMDGPUGenDAGISel.inc31568 /* 66811*/ /*SwitchOpcode*/ 109|128,32/*4205*/, TARGET_VAL(ISD::STORE),// ->71020
gen/lib/Target/AMDGPU/R600GenDAGISel.inc 5806 /* 22919*/ /*SwitchOpcode*/ 74|128,2/*330*/, TARGET_VAL(ISD::STORE),// ->23253
gen/lib/Target/ARC/ARCGenDAGISel.inc 57 /* 0*/ OPC_SwitchOpcode /*30 cases */, 32|128,1/*160*/, TARGET_VAL(ISD::STORE),// ->165
gen/lib/Target/ARM/ARMGenDAGISel.inc21800 /* 46841*/ /*SwitchOpcode*/ 65|128,43/*5569*/, TARGET_VAL(ISD::STORE),// ->52414
gen/lib/Target/AVR/AVRGenDAGISel.inc 97 /* 72*/ /*SwitchOpcode*/ 117|128,3/*501*/, TARGET_VAL(ISD::STORE),// ->577
gen/lib/Target/BPF/BPFGenDAGISel.inc 146 /* 154*/ /*SwitchOpcode*/ 114|128,1/*242*/, TARGET_VAL(ISD::STORE),// ->400
gen/lib/Target/Hexagon/HexagonGenDAGISel.inc 57 /* 0*/ OPC_SwitchOpcode /*92 cases */, 41|128,45|128,2/*38569*/, TARGET_VAL(ISD::STORE),// ->38575
gen/lib/Target/Lanai/LanaiGenDAGISel.inc 191 /* 262*/ /*SwitchOpcode*/ 0|128,1/*128*/, TARGET_VAL(ISD::STORE),// ->394
gen/lib/Target/MSP430/MSP430GenDAGISel.inc 57 /* 0*/ OPC_SwitchOpcode /*36 cases */, 25|128,39/*5017*/, TARGET_VAL(ISD::STORE),// ->5022
gen/lib/Target/Mips/MipsGenDAGISel.inc 57 /* 0*/ OPC_SwitchOpcode /*177 cases */, 73|128,7/*969*/, TARGET_VAL(ISD::STORE),// ->974
gen/lib/Target/PowerPC/PPCGenDAGISel.inc 57 /* 0*/ OPC_SwitchOpcode /*197 cases */, 97|128,38/*4961*/, TARGET_VAL(ISD::STORE),// ->4966
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 2743 /* 5060*/ /*SwitchOpcode*/ 59|128,17/*2235*/, TARGET_VAL(ISD::STORE),// ->7299
gen/lib/Target/Sparc/SparcGenDAGISel.inc 57 /* 0*/ OPC_SwitchOpcode /*69 cases */, 39|128,4/*551*/, TARGET_VAL(ISD::STORE),// ->556
gen/lib/Target/SystemZ/SystemZGenDAGISel.inc 57 /* 0*/ OPC_SwitchOpcode /*205 cases */, 67|128,65/*8387*/, TARGET_VAL(ISD::STORE),// ->8392
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc11320 /* 21718*/ /*SwitchOpcode*/ 3|128,19/*2435*/, TARGET_VAL(ISD::STORE),// ->24157
gen/lib/Target/X86/X86GenDAGISel.inc 57 /* 0*/ OPC_SwitchOpcode /*423 cases */, 127|128,124/*15999*/, TARGET_VAL(ISD::STORE),// ->16004
gen/lib/Target/XCore/XCoreGenDAGISel.inc 413 /* 645*/ /*SwitchOpcode*/ 22|128,2/*278*/, TARGET_VAL(ISD::STORE),// ->927
include/llvm/CodeGen/SelectionDAGNodes.h 1397 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
1405 N->getOpcode() == ISD::STORE ||
2227 N->getOpcode() == ISD::STORE;
2266 : LSBaseSDNode(ISD::STORE, Order, dl, VTs, AM, MemVT, MMO) {
2286 return N->getOpcode() == ISD::STORE;
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1589 case ISD::STORE: return visitSTORE(N);
6495 if (LegalOperations && !TLI.isOperationLegal(ISD::STORE, VT))
14980 !TLI.isOperationLegal(ISD::STORE, IntVT) ||
14982 !TLI.isDesirableToTransformToIntegerOp(ISD::STORE, VT))
16072 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
16084 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
16093 TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
16141 TLI.isOperationLegal(ISD::STORE, SVT)) &&
16363 case ISD::STORE: {
20625 case ISD::STORE: {
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 501 switch (TLI.getOperationAction(ISD::STORE, VT)) {
525 MVT NVT = TLI.getTypeToPromoteTo(ISD::STORE, VT);
1045 case ISD::STORE:
1273 case ISD::STORE:
lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp 852 case ISD::STORE: Res = SoftenFloatOp_STORE(N, OpNo); break;
1657 case ISD::STORE: Res = ExpandFloatOp_STORE(cast<StoreSDNode>(N),
1924 case ISD::STORE: R = PromoteFloatOp_STORE(N, OpNo); break;
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 1178 case ISD::STORE: Res = PromoteIntOp_STORE(cast<StoreSDNode>(N),
3612 case ISD::STORE: Res = ExpandIntOp_STORE(cast<StoreSDNode>(N), OpNo); break;
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 273 } else if (Op.getOpcode() == ISD::STORE) {
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 625 case ISD::STORE:
1991 case ISD::STORE:
4148 case ISD::STORE: Res = WidenVecOp_STORE(N); break;
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 554 case ISD::STORE: {
6848 AddNodeIDNode(ID, ISD::STORE, VTs, Ops);
6915 AddNodeIDNode(ID, ISD::STORE, VTs, Ops);
6944 AddNodeIDNode(ID, ISD::STORE, VTs, Ops);
lib/CodeGen/SelectionDAG/SelectionDAGAddressAnalysis.cpp 210 case ISD::STORE: {
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 360 case ISD::STORE: return "store";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 228 if (isOperationLegalOrCustom(ISD::STORE, NewVT) &&
232 isOperationLegalOrCustom(ISD::STORE, MVT::f64) &&
6631 if (!isOperationLegalOrCustom(ISD::STORE, intVT) &&
lib/CodeGen/TargetLoweringBase.cpp 1612 case Store: return ISD::STORE;
lib/Target/AArch64/AArch64ISelDAGToDAG.cpp 699 if (Use->getOpcode() != ISD::LOAD && Use->getOpcode() != ISD::STORE &&
lib/Target/AArch64/AArch64ISelLowering.cpp 606 setTargetDAGCombine(ISD::STORE);
823 setOperationPromotedToType(ISD::STORE, VT, PromoteTo);
3073 case ISD::STORE:
11761 case ISD::STORE:
lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp 723 if (Opc == ISD::LOAD || Opc == ISD::STORE || isa<AtomicSDNode>(N) ||
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 170 setOperationAction(ISD::STORE, MVT::f32, Promote);
171 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32);
173 setOperationAction(ISD::STORE, MVT::v2f32, Promote);
174 AddPromotedToType(ISD::STORE, MVT::v2f32, MVT::v2i32);
176 setOperationAction(ISD::STORE, MVT::v3f32, Promote);
177 AddPromotedToType(ISD::STORE, MVT::v3f32, MVT::v3i32);
179 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
180 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
182 setOperationAction(ISD::STORE, MVT::v5f32, Promote);
183 AddPromotedToType(ISD::STORE, MVT::v5f32, MVT::v5i32);
185 setOperationAction(ISD::STORE, MVT::v8f32, Promote);
186 AddPromotedToType(ISD::STORE, MVT::v8f32, MVT::v8i32);
188 setOperationAction(ISD::STORE, MVT::v16f32, Promote);
189 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
191 setOperationAction(ISD::STORE, MVT::v32f32, Promote);
192 AddPromotedToType(ISD::STORE, MVT::v32f32, MVT::v32i32);
194 setOperationAction(ISD::STORE, MVT::i64, Promote);
195 AddPromotedToType(ISD::STORE, MVT::i64, MVT::v2i32);
197 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
198 AddPromotedToType(ISD::STORE, MVT::v2i64, MVT::v4i32);
200 setOperationAction(ISD::STORE, MVT::f64, Promote);
201 AddPromotedToType(ISD::STORE, MVT::f64, MVT::v2i32);
203 setOperationAction(ISD::STORE, MVT::v2f64, Promote);
204 AddPromotedToType(ISD::STORE, MVT::v2f64, MVT::v4i32);
499 setTargetDAGCombine(ISD::STORE);
4068 case ISD::STORE:
lib/Target/AMDGPU/R600ISelLowering.cpp 97 setOperationAction(ISD::STORE, MVT::i8, Custom);
98 setOperationAction(ISD::STORE, MVT::i32, Custom);
99 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
100 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
488 case ISD::STORE: return LowerSTORE(Op, DAG);
lib/Target/AMDGPU/SIISelLowering.cpp 173 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
174 setOperationAction(ISD::STORE, MVT::v3i32, Custom);
175 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
176 setOperationAction(ISD::STORE, MVT::v5i32, Custom);
177 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
178 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
179 setOperationAction(ISD::STORE, MVT::i1, Custom);
180 setOperationAction(ISD::STORE, MVT::v32i32, Custom);
255 case ISD::STORE:
485 setOperationAction(ISD::STORE, MVT::f16, Promote);
486 AddPromotedToType(ISD::STORE, MVT::f16, MVT::i16);
513 case ISD::STORE:
539 setOperationAction(ISD::STORE, MVT::v2i16, Promote);
540 AddPromotedToType(ISD::STORE, MVT::v2i16, MVT::i32);
541 setOperationAction(ISD::STORE, MVT::v2f16, Promote);
542 AddPromotedToType(ISD::STORE, MVT::v2f16, MVT::i32);
561 setOperationAction(ISD::STORE, MVT::v4i16, Promote);
562 AddPromotedToType(ISD::STORE, MVT::v4i16, MVT::v2i32);
563 setOperationAction(ISD::STORE, MVT::v4f16, Promote);
564 AddPromotedToType(ISD::STORE, MVT::v4f16, MVT::v2i32);
731 setTargetDAGCombine(ISD::STORE);
1375 case ISD::STORE:
4032 case ISD::STORE: return LowerSTORE(Op, DAG);
8105 NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr;
9971 case ISD::STORE:
lib/Target/ARC/ARCISelLowering.cpp 114 setOperationAction(ISD::STORE, MVT::i32, Legal);
lib/Target/ARM/ARMISelDAGToDAG.cpp 2927 case ISD::STORE: {
lib/Target/ARM/ARMISelLowering.cpp 156 setOperationAction(ISD::STORE, VT, Promote);
157 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT);
233 setOperationAction(ISD::STORE, VT, Legal);
398 setOperationAction(ISD::STORE, VT, Custom);
925 setTargetDAGCombine(ISD::STORE);
9222 case ISD::STORE:
12877 const bool isStore = N->getOpcode() == ISD::STORE;
12957 case ISD::STORE: NewOpc = ARMISD::VST1_UPD;
13058 if (AlignedVecTy != VecTy && N->getOpcode() == ISD::STORE) {
14437 case ISD::STORE: return PerformSTORECombine(N, DCI, Subtarget);
14565 return (VT == MVT::f32) && (Opc == ISD::LOAD || Opc == ISD::STORE);
lib/Target/AVR/AVRISelDAGToDAG.cpp 323 template <> bool AVRDAGToDAGISel::select<ISD::STORE>(SDNode *N) {
544 case ISD::STORE: return select<ISD::STORE>(N);
544 case ISD::STORE: return select<ISD::STORE>(N);
lib/Target/Hexagon/HexagonISelDAGToDAG.cpp 885 case ISD::STORE: return SelectStore(N);
965 if (UUse->getOpcode() == ISD::STORE && SYNode->getOpcode() == ISD::LOAD) {
1029 if (I->getOpcode() != ISD::STORE)
1094 if (Opc != ISD::LOAD && Opc != ISD::STORE)
2235 if (N->getOpcode() != ISD::LOAD && N->getOpcode() != ISD::STORE)
lib/Target/Hexagon/HexagonISelLowering.cpp 1501 setOperationAction(ISD::STORE, VT, Custom);
2853 case ISD::STORE: return LowerStore(Op, DAG);
2895 if (N->getOpcode() != ISD::STORE)
lib/Target/Hexagon/HexagonISelLoweringHVX.cpp 143 setOperationAction(ISD::STORE, T, Custom);
1507 assert(MemOpc == ISD::STORE);
1530 case ISD::STORE:
lib/Target/Mips/MipsISelDAGToDAG.cpp 297 case ISD::STORE:
lib/Target/Mips/MipsISelLowering.cpp 376 setOperationAction(ISD::STORE, MVT::i64, Custom);
1241 case ISD::STORE: return lowerSTORE(Op, DAG);
lib/Target/Mips/MipsSEISelLowering.cpp 97 setOperationAction(ISD::STORE, VecTys[i], Legal);
208 setOperationAction(ISD::STORE, MVT::i32, Custom);
223 setOperationAction(ISD::STORE, MVT::f64, Custom);
326 setOperationAction(ISD::STORE, Ty, Legal);
379 setOperationAction(ISD::STORE, Ty, Legal);
452 case ISD::STORE: return lowerSTORE(Op, DAG);
lib/Target/NVPTX/NVPTXISelDAGToDAG.cpp 89 case ISD::STORE:
lib/Target/NVPTX/NVPTXISelLowering.cpp 466 setOperationAction(ISD::STORE, MVT::i1, Custom);
486 setOperationAction(ISD::STORE, VT, Custom);
2190 case ISD::STORE:
lib/Target/PowerPC/PPCISelDAGToDAG.cpp 1049 case ISD::STORE: {
4462 case ISD::STORE: {
lib/Target/PowerPC/PPCISelLowering.cpp 215 setOperationAction(ISD::STORE, MVT::i1, Custom);
620 setOperationAction(ISD::STORE, VT, Promote);
621 AddPromotedToType (ISD::STORE, VT, MVT::v4i32);
697 setOperationAction(ISD::STORE , MVT::v4i32, Legal);
787 setOperationAction(ISD::STORE, MVT::v2f64, Legal);
829 setOperationAction(ISD::STORE, MVT::v2i64, Promote);
830 AddPromotedToType (ISD::STORE, MVT::v2i64, MVT::v2f64);
939 setOperationAction(ISD::STORE , MVT::v4f64, Custom);
990 setOperationAction(ISD::STORE , MVT::v4f32, Custom);
1035 setOperationAction(ISD::STORE , MVT::v4i1, Custom);
1119 setTargetDAGCombine(ISD::STORE);
10140 case ISD::STORE: return LowerSTORE(Op, DAG);
13199 case ISD::STORE: {
13352 if (LSBase->getOpcode() == ISD::STORE) {
13416 case ISD::STORE: {
lib/Target/PowerPC/PPCISelLowering.h 861 if (Opc != ISD::LOAD && Opc != ISD::STORE)
lib/Target/Sparc/SparcISelLowering.cpp 1455 setOperationAction(ISD::STORE, MVT::v2i32, Legal);
1461 setOperationAction(ISD::STORE, MVT::i64, Custom);
1704 setOperationAction(ISD::STORE, MVT::f128, Legal);
1707 setOperationAction(ISD::STORE, MVT::f128, Custom);
3037 case ISD::STORE: return LowerSTORE(Op, DAG);
lib/Target/SystemZ/SystemZISelDAGToDAG.cpp 1606 case ISD::STORE: {
lib/Target/SystemZ/SystemZISelLowering.cpp 323 setOperationAction(ISD::STORE, VT, Legal);
611 setTargetDAGCombine(ISD::STORE);
6164 case ISD::STORE: return combineSTORE(N, DCI);
lib/Target/X86/X86ISelDAGToDAG.cpp 355 if (User->getOpcode() == ISD::STORE &&
5189 case ISD::STORE:
lib/Target/X86/X86ISelLowering.cpp 826 setOperationAction(ISD::STORE, MVT::v2f32, Custom);
974 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
975 setOperationAction(ISD::STORE, MVT::v4i16, Custom);
976 setOperationAction(ISD::STORE, MVT::v8i8, Custom);
1272 setOperationAction(ISD::STORE, VT, Custom);
1316 setOperationAction(ISD::STORE, MVT::v1i1, Custom);
1317 setOperationAction(ISD::STORE, MVT::v2i1, Custom);
1318 setOperationAction(ISD::STORE, MVT::v4i1, Custom);
1319 setOperationAction(ISD::STORE, MVT::v8i1, Custom);
1861 setTargetDAGCombine(ISD::STORE);
4883 UI->use_begin()->getOpcode() != ISD::STORE)
17303 if ((User->getOpcode() != ISD::STORE ||
20086 UI->getOpcode() != ISD::STORE)
27708 case ISD::STORE: return LowerStore(Op, Subtarget, DAG);
44930 case ISD::STORE: return combineStore(N, DAG, DCI, Subtarget);
lib/Target/XCore/XCoreISelLowering.cpp 133 setOperationAction(ISD::STORE, MVT::i32, Custom);
169 setTargetDAGCombine(ISD::STORE);
206 case ISD::STORE: return LowerSTORE(Op, DAG);
1779 case ISD::STORE: {