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reference, declaration → definition
definition → references, declarations, derived classes, virtual overrides
reference to multiple definitions → definitions
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References
gen/lib/Target/Mips/MipsGenDAGISel.inc16359 /* 30322*/ /*SwitchOpcode*/ 33, TARGET_VAL(ISD::SREM),// ->30358
26549 /* 50265*/ /*SwitchOpcode*/ 90, TARGET_VAL(ISD::SREM),// ->50358
gen/lib/Target/Mips/MipsGenFastISel.inc 3424 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/NVPTX/NVPTXGenDAGISel.inc58130 /*123540*/ /*SwitchOpcode*/ 81, TARGET_VAL(ISD::SREM),// ->123624
gen/lib/Target/PowerPC/PPCGenDAGISel.inc28450 /* 68400*/ /*SwitchOpcode*/ 28, TARGET_VAL(ISD::SREM),// ->68431
gen/lib/Target/PowerPC/PPCGenFastISel.inc 3252 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/RISCV/RISCVGenDAGISel.inc 5339 /* 9892*/ OPC_CheckOpcode, TARGET_VAL(ISD::SREM),
5377 /* 9960*/ OPC_CheckOpcode, TARGET_VAL(ISD::SREM),
5791 /* 10672*/ /*SwitchOpcode*/ 17|128,1/*145*/, TARGET_VAL(ISD::SREM),// ->10821
gen/lib/Target/WebAssembly/WebAssemblyGenDAGISel.inc16814 /* 32598*/ /*SwitchOpcode*/ 24, TARGET_VAL(ISD::SREM),// ->32625
gen/lib/Target/WebAssembly/WebAssemblyGenFastISel.inc 1919 case ISD::SREM: return fastEmit_ISD_SREM_rr(VT, RetVT, Op0, Op0IsKill, Op1, Op1IsKill);
gen/lib/Target/XCore/XCoreGenDAGISel.inc 2129 /* 3716*/ /*SwitchOpcode*/ 10, TARGET_VAL(ISD::SREM),// ->3729
include/llvm/CodeGen/TargetLowering.h 2306 case ISD::SREM:
lib/CodeGen/SelectionDAG/DAGCombiner.cpp 1516 case ISD::SREM:
3512 bool isSigned = (Opcode == ISD::SDIV) || (Opcode == ISD::SREM);
3532 OtherOpcode = isSigned ? ISD::SREM : ISD::UREM;
3570 else if (UserOpc == ISD::SREM || UserOpc == ISD::UREM)
3664 if (SDNode *RemNode = DAG.getNodeIfExists(ISD::SREM, N->getVTList(),
3875 bool isSigned = (Opcode == ISD::SREM);
7271 ISD::SREM, dl, ShiftVT, CombinedShift.getNode(),
19603 Opcode != ISD::UREM && Opcode != ISD::SREM &&
lib/CodeGen/SelectionDAG/FastISel.cpp 1817 return selectBinaryOp(I, ISD::SREM);
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp 3197 case ISD::SREM: {
3199 bool isSigned = Node->getOpcode() == ISD::SREM;
4051 case ISD::SREM:
4224 case ISD::SREM:
4242 case ISD::SREM:
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp 134 case ISD::SREM: Res = PromoteIntRes_SExtIntBinOp(N); break;
1709 case ISD::SREM: ExpandIntRes_SREM(N, Lo, Hi); break;
lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp 366 case ISD::SREM:
lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp 136 case ISD::SREM:
952 case ISD::SREM:
2763 case ISD::SREM:
lib/CodeGen/SelectionDAG/SelectionDAG.cpp 3089 case ISD::SREM:
4728 case ISD::SREM:
4773 case ISD::SREM:
5106 case ISD::SREM:
5381 case ISD::SREM:
5403 case ISD::SREM:
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h 681 void visitSRem(const User &I) { visitBinary(I, ISD::SREM); }
lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp 230 case ISD::SREM: return "srem";
lib/CodeGen/SelectionDAG/TargetLowering.cpp 3860 if ((N0.getOpcode() == ISD::UREM || N0.getOpcode() == ISD::SREM) &&
3870 } else if (N0.getOpcode() == ISD::SREM) {
lib/CodeGen/TargetLoweringBase.cpp 813 case ISD::SREM:
1602 case SRem: return ISD::SREM;
lib/Target/AArch64/AArch64FastISel.cpp 4646 case ISD::SREM:
5161 if (!selectBinaryOp(I, ISD::SREM))
5162 return selectRem(I, ISD::SREM);
lib/Target/AArch64/AArch64ISelLowering.cpp 328 setOperationAction(ISD::SREM, MVT::i32, Expand);
329 setOperationAction(ISD::SREM, MVT::i64, Expand);
866 setOperationAction(ISD::SREM, VT, Expand);
lib/Target/AMDGPU/AMDGPUISelLowering.cpp 310 setOperationAction(ISD::SREM, VT, Expand);
380 setOperationAction(ISD::SREM, VT, Expand);
lib/Target/AMDGPU/SIISelLowering.cpp 449 setOperationAction(ISD::SREM, MVT::i16, Promote);
lib/Target/ARM/ARMISelLowering.cpp 204 setOperationAction(ISD::SREM, VT, Expand);
277 setOperationAction(ISD::SREM, VT, Expand);
1109 setOperationAction(ISD::SREM, MVT::i32, Expand);
1116 setOperationAction(ISD::SREM, MVT::i64, Custom);
9182 case ISD::SREM: return LowerREM(Op.getNode(), DAG);
9293 case ISD::SREM:
15919 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&
15922 N->getOpcode() == ISD::SREM;
15937 N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM) &&
15940 N->getOpcode() == ISD::SREM;
16040 bool isSigned = N->getOpcode() == ISD::SREM;
lib/Target/ARM/ARMTargetTransformInfo.cpp 660 { ISD::SREM, MVT::v1i64, 1 * FunctionCallDivCost},
664 { ISD::SREM, MVT::v2i32, 2 * FunctionCallDivCost},
668 { ISD::SREM, MVT::v4i16, 4 * FunctionCallDivCost},
672 { ISD::SREM, MVT::v8i8, 8 * FunctionCallDivCost},
677 { ISD::SREM, MVT::v2i64, 2 * FunctionCallDivCost},
681 { ISD::SREM, MVT::v4i32, 4 * FunctionCallDivCost},
685 { ISD::SREM, MVT::v8i16, 8 * FunctionCallDivCost},
689 { ISD::SREM, MVT::v16i8, 16 * FunctionCallDivCost},
917 case ISD::SREM:
lib/Target/AVR/AVRISelLowering.cpp 150 setOperationAction(ISD::SREM, MVT::i8, Expand);
151 setOperationAction(ISD::SREM, MVT::i16, Expand);
lib/Target/BPF/BPFISelLowering.cpp 88 setOperationAction(ISD::SREM, VT, Expand);
lib/Target/Hexagon/HexagonISelLowering.cpp 1374 {ISD::SDIV, ISD::UDIV, ISD::SREM, ISD::UREM,
1421 ISD::SREM, ISD::UREM, ISD::SDIVREM, ISD::UDIVREM, ISD::SADDO,
lib/Target/Lanai/LanaiISelLowering.cpp 110 setOperationAction(ISD::SREM, MVT::i32, Expand);
lib/Target/MSP430/MSP430ISelLowering.cpp 133 setOperationAction(ISD::SREM, MVT::i8, Promote);
139 setOperationAction(ISD::SREM, MVT::i16, LibCall);
lib/Target/Mips/MipsFastISel.cpp 1932 case ISD::SREM:
1953 unsigned MFOpc = (ISDOpcode == ISD::SREM || ISDOpcode == ISD::UREM)
2054 if (!selectBinaryOp(I, ISD::SREM))
2055 return selectDivRem(I, ISD::SREM);
lib/Target/Mips/MipsISelLowering.cpp 394 setOperationAction(ISD::SREM, MVT::i32, Expand);
398 setOperationAction(ISD::SREM, MVT::i64, Expand);
lib/Target/Mips/MipsSEISelLowering.cpp 241 setOperationAction(ISD::SREM, MVT::i32, Legal);
288 setOperationAction(ISD::SREM, MVT::i64, Legal);
339 setOperationAction(ISD::SREM, Ty, Legal);
2057 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
lib/Target/NVPTX/NVPTXISelLowering.cpp 522 setTargetDAGCombine(ISD::SREM);
4542 assert(N->getOpcode() == ISD::SREM || N->getOpcode() == ISD::UREM);
4551 bool IsSigned = N->getOpcode() == ISD::SREM;
4770 case ISD::SREM:
lib/Target/PowerPC/PPCISelLowering.cpp 250 setOperationAction(ISD::SREM, MVT::i32, Custom);
252 setOperationAction(ISD::SREM, MVT::i64, Custom);
255 setOperationAction(ISD::SREM, MVT::i32, Expand);
257 setOperationAction(ISD::SREM, MVT::i64, Expand);
626 setOperationAction(ISD::SREM, VT, Expand);
9544 if ((Op.getOpcode() == ISD::SREM && UI->getOpcode() == ISD::SDIV) ||
10176 case ISD::SREM:
lib/Target/RISCV/RISCVISelLowering.cpp 116 setOperationAction(ISD::SREM, XLenVT, Expand);
lib/Target/Sparc/SparcISelLowering.cpp 1496 setOperationAction(ISD::SREM, MVT::i32, Expand);
1503 setOperationAction(ISD::SREM, MVT::i64, Expand);
lib/Target/SystemZ/SystemZISelLowering.cpp 161 setOperationAction(ISD::SREM, VT, Expand);
619 setTargetDAGCombine(ISD::SREM);
6176 case ISD::SREM:
lib/Target/WebAssembly/WebAssemblyISelLowering.cpp 176 ISD::SREM, ISD::UREM, ISD::ROTL, ISD::ROTR}) {
lib/Target/X86/X86ISelLowering.cpp 314 setOperationAction(ISD::SREM, VT, Expand);
749 setOperationAction(ISD::SREM, VT, Expand);
849 setOperationAction(ISD::SREM, VT, Custom);
1818 setOperationAction(ISD::SREM, MVT::i128, Custom);
25395 case ISD::SREM: isSigned = true; LC = RTLIB::SREM_I128; break;
27939 case ISD::SREM:
lib/Target/X86/X86TargetTransformInfo.cpp 247 if ((ISD == ISD::SDIV || ISD == ISD::SREM || ISD == ISD::UDIV ||
252 if (ISD == ISD::SDIV || ISD == ISD::SREM) {
268 if (ISD == ISD::SREM) {
350 { ISD::SREM, MVT::v64i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
354 { ISD::SREM, MVT::v32i16, 8 }, // vpmulhw+mul+sub sequence
369 { ISD::SREM, MVT::v16i32, 17 }, // vpmuldq+mul+sub sequence
384 { ISD::SREM, MVT::v32i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
388 { ISD::SREM, MVT::v16i16, 8 }, // vpmulhw+mul+sub sequence
392 { ISD::SREM, MVT::v8i32, 19 }, // vpmuldq+mul+sub sequence
406 { ISD::SREM, MVT::v32i8, 32+2 }, // 4*ext+4*pmulhw+mul+sub sequence + split.
408 { ISD::SREM, MVT::v16i8, 16 }, // 2*ext+2*pmulhw+mul+sub sequence
414 { ISD::SREM, MVT::v16i16, 16+2 }, // 2*pmulhw+mul+sub sequence + split.
416 { ISD::SREM, MVT::v8i16, 8 }, // pmulhw+mul+sub sequence
422 { ISD::SREM, MVT::v8i32, 48+2 }, // 2*pmuludq+mul+sub sequence + split.
424 { ISD::SREM, MVT::v4i32, 24 }, // pmuludq+mul+sub sequence
437 if (ISD == ISD::SREM && LT.second == MVT::v8i32 && ST->hasAVX())
441 if (ISD == ISD::SREM && LT.second == MVT::v4i32 && ST->hasSSE41())
876 if (LT.second.isVector() && (ISD == ISD::SDIV || ISD == ISD::SREM ||